Index: kernel/arch/arm32/src/cpu/cpu.c
===================================================================
--- kernel/arch/arm32/src/cpu/cpu.c	(revision bfb57fb06c82051f52eb9f565b7956fa7c6e058e)
+++ kernel/arch/arm32/src/cpu/cpu.c	(revision 1a3a6324d0b518b6a2bb70b339b7ebb916432c2a)
@@ -98,5 +98,4 @@
 void cpu_arch_init(void)
 {
-#if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
 	uint32_t control_reg = 0;
 	asm volatile (
@@ -109,4 +108,9 @@
 	/* Turn off accessed flag, RAZ/WI prior to armv7 */
 	control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
+	/* Enable branch prediction RAZ/WI if not supported */
+	control_reg |= CP15_R1_BRANCH_PREDICT_EN;
+
+	/* Unaligned access is supported on armv6+ */
+#if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
 	/* Enable unaligned access, RAZ/WI prior to armv6
 	 * switchable on armv6, RAO/WI writes on armv7,
@@ -124,16 +128,20 @@
 	 *    ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
 	 *    B3.11.1 (p. 1383)
-	 * ICache coherency is elaborate on in barrier.h.
-	 * We are safe to turn these on.
+	 * We are safe to turn this on. For arm v6 see ch L.6.2 (p. 2469)
+	 * L2 Cache for armv7 was enabled in boot code.
 	 */
-	control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;
+	control_reg |= CP15_R1_CACHE_EN;
+#endif
+#ifdef PROCESSOR_cortex_a8
+	 /* ICache coherency is elaborate on in barrier.h.
+	  * Cortex-A8 implements IVIPT extension.
+	  * Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
+	control_reg |= CP15_R1_INST_CACHE_EN;
+#endif
 	
-	/* Enable branch prediction */
-	control_reg |= CP15_R1_BRANCH_PREDICT_EN;
 	asm volatile (
 		"mcr p15, 0, %[control_reg], c1, c0"
 		:: [control_reg] "r" (control_reg)
 	);
-#endif
 #ifdef CONFIG_FPU
 	fpu_setup();