Index: kernel/arch/arm32/include/arch/barrier.h
===================================================================
--- kernel/arch/arm32/include/arch/barrier.h	(revision d5610b97cb04ef50092daf40ac8aaab0770e0199)
+++ kernel/arch/arm32/include/arch/barrier.h	(revision 1a2a6e7fe539dc0c3c10afeaf20a054d6132d99a)
@@ -40,4 +40,5 @@
 #include <arch/cache.h>
 #include <arch/cp15.h>
+#include <align.h>
 #else
 #include <libarch/cp15.h>
@@ -115,5 +116,5 @@
 #define smc_coherence(a) \
 do { \
-	dcache_clean_mva_pou((uintptr_t) a);\
+	dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \
 	write_barrier();               /* Wait for completion */\
 	icache_invalidate();\
@@ -124,5 +125,6 @@
 #define smc_coherence_block(a, l) \
 do { \
-	for (uintptr_t addr = (uintptr_t)a; addr < (uintptr_t)a + l; addr += 4)\
+	for (uintptr_t addr = (uintptr_t) a; addr < (uintptr_t) a + l; \
+	    addr += CP15_C7_MVA_ALIGN) \
 		smc_coherence(addr); \
 } while (0)
Index: kernel/arch/arm32/include/arch/cp15.h
===================================================================
--- kernel/arch/arm32/include/arch/cp15.h	(revision d5610b97cb04ef50092daf40ac8aaab0770e0199)
+++ kernel/arch/arm32/include/arch/cp15.h	(revision 1a2a6e7fe539dc0c3c10afeaf20a054d6132d99a)
@@ -395,4 +395,16 @@
  */
 
+#if defined(PROCESSOR_cortex_a8)
+#define CP15_C7_MVA_ALIGN	64
+#elif defined(PROCESSOR_arm1176)
+#define CP15_C7_MVA_ALIGN	32
+#elif defined(PROCESSOR_arm926ej_s)
+#define CP15_C7_MVA_ALIGN	32
+#elif defined(PROCESSOR_arm920t)
+#define CP15_C7_MVA_ALIGN	32
+#else
+#error Unknow MVA alignment
+#endif
+
 #if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
 CONTROL_REG_GEN_WRITE(CP15ISB, c7, 0, c5, 4);