Index: uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h	(revision 9c0eba6875a0185ea33b9707806ce82a7b946051)
+++ uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h	(revision 19acf24d58c72e5acd9143fc337c64403df0b556)
@@ -114,9 +114,12 @@
 	ioport32_t clksel1_pll;
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_MASK   (0x1f << 27)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_(x)   (((x) & 0x1f) << 27)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_CREATE(x)   (((x) & 0x1f) << 27)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(x)   (((x) >> 27) & 0x1f)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_MASK   (0x7ff << 16)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT(x)   (((x) & 0x7ff) << 16)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_CREATE(x)   (((x) & 0x7ff) << 16)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(x)   (((x) >> 16) & 0x7ff)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_MASK   (0x7f << 8)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV(x)   (((x) & 0x7f) << 8)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_CREATE(x)   (((x) & 0x7f) << 8)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(x)   (((x) >> 8) & 0x7f)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_96M_FLAG   (1 << 6)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_54M_FLAG   (1 << 5)
Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision 9c0eba6875a0185ea33b9707806ce82a7b946051)
+++ uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision 19acf24d58c72e5acd9143fc337c64403df0b556)
@@ -227,4 +227,40 @@
 	 * interconnects.
 	 */
+	if (pio_read_32(&device->cm.clocks->idlest_ckgen) & CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG) {
+		/* DPLL active and locked */
+		const uint32_t reg =
+		    pio_read_32(&device->cm.clocks->clksel1_pll);
+		const unsigned multiplier =
+		    CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(reg);
+		const unsigned divisor =
+		    CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(reg);
+		const unsigned divisor2 =
+		    CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(reg);
+		if (multiplier && divisor && divisor2) {
+			const unsigned freq =
+			    ((base_freq / divisor) * multiplier) / divisor2;
+			ddf_msg(LVL_NOTE, "CORE CLK running at %d.%d MHz",
+			    freq / 1000, freq % 1000);
+			const unsigned l3_div =
+			    pio_read_32(&device->cm.core->clksel)
+			    & CORE_CM_CLKSEL_CLKSEL_L3_MASK;
+			if (l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 ||
+			    l3_div == CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2) {
+				ddf_msg(LVL_NOTE, "L3 interface at %d.%d MHz",
+				    (freq / l3_div) / 1000,
+				    (freq / l3_div) % 1000);
+			} else {
+				ddf_msg(LVL_WARN,"L3 interface clock divisor is"
+				    " invalid: %d", l3_div);
+			}
+		} else {
+			ddf_msg(LVL_WARN, "DPLL3 frequency divisor and/or "
+			    "multiplier value invalid: %d %d %d",
+			    multiplier, divisor, divisor2);
+		}
+	} else {
+		ddf_msg(LVL_WARN, "CORE CLK in bypass mode, fruunig at SYS_CLK"
+		   " frreq of %d.%d MHz", base_freq / 1000, base_freq % 1000);
+	}
 
 	/* Set DPLL3 to automatic to save power */