Index: arch/ia32/include/asm.h =================================================================== --- arch/ia32/include/asm.h (revision d89652555244d155a50d0893a409004587e7c475) +++ arch/ia32/include/asm.h (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -38,8 +38,4 @@ extern void paging_on(void); -extern __address cpu_read_dba(void); -extern void cpu_write_dba(__address dba); - -extern __address cpu_read_cr2(void); extern void interrupt_handlers(void); @@ -55,12 +51,108 @@ extern void enable_l_apic_in_msr(void); -extern void halt_cpu(void); -extern void cpu_sleep(void); +/** Halt CPU + * + * Halt the current CPU until interrupt event. + */ +static inline void cpu_halt(void) { __asm__("hlt"); }; +static inline void cpu_sleep(void) { __asm__("hlt"); }; -static inline void write_dr0(__u32 v); -static inline __u32 read_dr0(void); +/** Read CR2 + * + * Return value in CR2 + * + * @return Value read. + */ +static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0" : "=r" (v)); return v; } -inline void write_dr0(__u32 v) { __asm__ volatile ("movl %0,%%dr0\n" : : "r" (v)); } -inline __u32 read_dr0(void) { __u32 v; __asm__ volatile ("movl %%dr0,%0" : "=r" (v)); return v; } +/** Write CR3 + * + * Write value to CR3. + * + * @param v Value to be written. + */ +static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); } + +/** Read CR3 + * + * Return value in CR3 + * + * @return Value read. + */ +static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0" : "=r" (v)); return v; } + +/** Write DR0 + * + * Write value to DR0. + * + * @param v Value to be written. + */ +static inline void write_dr0(__u32 v) { __asm__ volatile ("movl %0,%%dr0\n" : : "r" (v)); } + +/** Read DR0 + * + * Return value in DR0 + * + * @return Value read. + */ +static inline __u32 read_dr0(void) { __u32 v; __asm__ volatile ("movl %%dr0,%0" : "=r" (v)); return v; } + +/** Set priority level low + * + * Enable interrupts and return previous + * value of EFLAGS. + */ +static inline pri_t cpu_priority_low(void) { + pri_t v; + __asm__ volatile ( + "pushf\n" + "popl %0\n" + "sti\n" + : "=r" (v) + ); + return v; +} + +/** Set priority level high + * + * Disable interrupts and return previous + * value of EFLAGS. + */ +static inline pri_t cpu_priority_high(void) { + pri_t v; + __asm__ volatile ( + "pushf\n" + "popl %0\n" + "cli\n" + : "=r" (v) + ); + return v; +} + +/** Restore priority level + * + * Restore EFLAGS. + */ +static inline void cpu_priority_restore(pri_t pri) { + __asm__ volatile ( + "pushl %0\n" + "popf\n" + : : "r" (pri) + ); +} + +/** Return raw priority level + * + * Return EFLAFS. + */ +static inline pri_t cpu_priority_read(void) { + pri_t v; + __asm__ volatile ( + "pushf\n" + "popl %0\n" + : "=r" (v) + ); + return v; +} #endif Index: arch/ia32/include/atomic.h =================================================================== --- arch/ia32/include/atomic.h (revision d89652555244d155a50d0893a409004587e7c475) +++ arch/ia32/include/atomic.h (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -32,8 +32,34 @@ #include -extern void atomic_inc(volatile int *val); -extern void atomic_dec(volatile int *val); +static inline void atomic_inc(volatile int *val) { +#ifdef __SMP__ + __asm__ volatile ("lock incl (%0)\n" : : "r" (val)); +#else + __asm__ volatile ("incl (%0)\n" : : "r" (val)); +#endif /* __SMP__ */ +} -extern int test_and_set(int *val); +static inline void atomic_dec(volatile int *val) { +#ifdef __SMP__ + __asm__ volatile ("lock decl (%0)\n" : : "r" (val)); +#else + __asm__ volatile ("decl (%0)\n" : : "r" (val)); +#endif /* __SMP__ */ +} + +static inline int test_and_set(int *val) { + int v; + + __asm__ volatile ( + "movl $1, %0\n" + "xchgl %0, (%1)\n" + : "=r" (v) + : "r" (val) + ); + + return v; +} + + extern void spinlock_arch(int *val); Index: arch/ia32/src/asm.s =================================================================== --- arch/ia32/src/asm.s (revision d89652555244d155a50d0893a409004587e7c475) +++ arch/ia32/src/asm.s (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -31,14 +31,7 @@ .text -.global cpu_priority_high -.global cpu_priority_low -.global cpu_priority_restore -.global cpu_priority_read .global cpu_halt .global cpu_sleep .global paging_on -.global cpu_read_dba -.global cpu_write_dba -.global cpu_read_cr2 .global enable_l_apic_in_msr .global interrupt_handlers @@ -55,57 +48,4 @@ -## Set priority level high -# -# Disable interrupts and return previous -# EFLAGS in EAX. -# -cpu_priority_high: - pushf - pop %eax - cli - ret - - -## Set priority level low -# -# Enable interrupts and return previous -# EFLAGS in EAX. -# -cpu_priority_low: - pushf - pop %eax - sti - ret - - -## Restore priority level -# -# Restore EFLAGS. -# -cpu_priority_restore: - push 4(%esp) - popf - ret - -## Return raw priority level -# -# Return EFLAFS in EAX. -# -cpu_priority_read: - pushf - pop %eax - ret - - -## Halt the CPU -# -# Halt the CPU using HLT. -# -cpu_halt: -cpu_sleep: - hlt - ret - - ## Turn paging on # @@ -124,34 +64,4 @@ -## Read CR3 -# -# Store CR3 in EAX. -# -cpu_read_dba: - movl %cr3,%eax - ret - - -## Write CR3 -# -# Set CR3. -# -cpu_write_dba: - pushl %eax - movl 8(%esp),%eax - movl %eax,%cr3 - popl %eax - ret - - -## Read CR2 -# -# Store CR2 in EAX. -# -cpu_read_cr2: - movl %cr2,%eax - ret - - ## Enable local APIC # Index: arch/ia32/src/atomic.S =================================================================== --- arch/ia32/src/atomic.S (revision d89652555244d155a50d0893a409004587e7c475) +++ arch/ia32/src/atomic.S (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -29,45 +29,7 @@ .text -.global atomic_inc -atomic_inc: - pushl %ebx - movl 8(%esp),%ebx -#ifdef __SMP__ - lock incl (%ebx) -#else - incl (%ebx) -#endif - popl %ebx - ret - -.global atomic_dec -atomic_dec: - pushl %ebx - movl 8(%esp),%ebx -#ifdef __SMP__ - lock decl (%ebx) -#else - decl (%ebx) -#endif - popl %ebx - ret - - #ifdef __SMP__ - -.global test_and_set .global spinlock_arch - -test_and_set: - pushl %ebx - - movl 8(%esp),%ebx - movl $1,%eax - xchgl %eax,(%ebx) # xchg implicitly turns on the LOCK signal - - popl %ebx - ret - # Index: arch/ia32/src/interrupt.c =================================================================== --- arch/ia32/src/interrupt.c (revision d89652555244d155a50d0893a409004587e7c475) +++ arch/ia32/src/interrupt.c (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -112,5 +112,5 @@ void page_fault(__u8 n, __u32 stack[]) { - printf("page fault address: %X\n", cpu_read_cr2()); + printf("page fault address: %X\n", read_cr2()); printf("stack[0]=%X, %%eip=%X, %%cs=%X, flags=%X\n", stack[0], stack[1], stack[2], stack[3]); printf("%%eax=%L, %%ebx=%L, %%ecx=%L, %%edx=%L,\n%%edi=%L, %%esi=%L, %%ebp=%L, %%esp=%L\n", stack[-2], stack[-5], stack[-3], stack[-4], stack[-9], stack[-8], stack[-1], stack); Index: arch/ia32/src/mm/page.c =================================================================== --- arch/ia32/src/mm/page.c (revision d89652555244d155a50d0893a409004587e7c475) +++ arch/ia32/src/mm/page.c (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -70,5 +70,5 @@ trap_register(14, page_fault); - cpu_write_dba(KA2PA(dba)); + write_cr3(KA2PA(dba)); } else { @@ -82,5 +82,5 @@ dba = frame_alloc(FRAME_KA | FRAME_PANIC); memcopy(bootstrap_dba, dba, PAGE_SIZE); - cpu_write_dba(KA2PA(dba)); + write_cr3(KA2PA(dba)); } @@ -108,5 +108,5 @@ if (root) dba = root; - else dba = cpu_read_dba(); + else dba = read_cr3(); pde = page >> 22; /* page directory entry */ Index: arch/ia32/src/mm/tlb.c =================================================================== --- arch/ia32/src/mm/tlb.c (revision d89652555244d155a50d0893a409004587e7c475) +++ arch/ia32/src/mm/tlb.c (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -32,4 +32,4 @@ void tlb_invalidate(int asid) { - cpu_write_dba(cpu_read_dba()); + write_cr3(read_cr3()); } Index: arch/ia32/src/smp/apic.c =================================================================== --- arch/ia32/src/smp/apic.c (revision d89652555244d155a50d0893a409004587e7c475) +++ arch/ia32/src/smp/apic.c (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -45,4 +45,5 @@ * Tested on: * Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs + * Simics 2.0.28 * ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs */ Index: doc/requirements =================================================================== --- doc/requirements (revision d89652555244d155a50d0893a409004587e7c475) +++ doc/requirements (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -2,21 +2,23 @@ ========= - HARDWARE REQUIREMENTS - o IA-32 processor (Pentium and successors) + HARDWARE REQUIREMENTS + o IA-32 processor (Pentium and successors) - COMPILER REQUIREMENTS - o binutils 2.15 - o gcc 2.95 - o gcc 3.3.2 - gcc 3.3.5 + COMPILER REQUIREMENTS + o binutils 2.15 + o gcc 2.95 + o gcc 3.3.2 - gcc 3.3.5 - SMP COMPATIBILITY - o Bochs 2.0.2 - Bochs 2.2 - o 2x-8x 686 CPU - o ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 - o 2x 200Mhz Pentium CPU + SMP COMPATIBILITY + o Bochs 2.0.2 - Bochs 2.2 + o 2x-8x 686 CPU + o Simics 2.0.28 + o 4x Pentium 4 CPU + o ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 + o 2x 200Mhz Pentium CPU - EMULATORS AND VIRTUALIZERS - o Bochs 2.0.2 - Bochs 2.2-cvs - o VMware Workstation 4, VMware Workstation 5 + EMULATORS AND VIRTUALIZERS + o Bochs 2.0.2 - Bochs 2.2 + o VMware Workstation 4, VMware Workstation 5 @@ -24,22 +26,22 @@ ========= - HARDWARE REQUIREMENTS - o no real hardware supported - o msim emulated MIPS R4000 CPU (see mips) + HARDWARE REQUIREMENTS + o no real hardware supported + o msim emulated MIPS R4000 CPU (see mips) - COMPILER REQUIREMENTS - o binutils 2.14 mips cross binutils - o gcc 2.8.1 mips cross compiler - o gcc 3.2.3 mips cross compiler + COMPILER REQUIREMENTS + o binutils 2.14 mips cross binutils + o gcc 2.8.1 mips cross compiler + o gcc 3.2.3 mips cross compiler - EMULATORS AND VIRTUALIZERS - o msim + EMULATORS AND VIRTUALIZERS + o msim ia64 port ========= - HARDWARE REQUIREMENTS - o no real hardware supported + HARDWARE REQUIREMENTS + o no real hardware supported - EMULATORS AND VIRTUALIZERS - o ski + EMULATORS AND VIRTUALIZERS + o ski Index: src/debug/print.c =================================================================== --- src/debug/print.c (revision d89652555244d155a50d0893a409004587e7c475) +++ src/debug/print.c (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -31,4 +31,5 @@ #include #include +#include Index: src/mm/frame.c =================================================================== --- src/mm/frame.c (revision d89652555244d155a50d0893a409004587e7c475) +++ src/mm/frame.c (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -42,4 +42,6 @@ #include + +#include count_t frames = 0; Index: src/mm/heap.c =================================================================== --- src/mm/heap.c (revision d89652555244d155a50d0893a409004587e7c475) +++ src/mm/heap.c (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -33,4 +33,5 @@ #include #include +#include /* Index: src/mm/vm.c =================================================================== --- src/mm/vm.c (revision d89652555244d155a50d0893a409004587e7c475) +++ src/mm/vm.c (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -39,4 +39,5 @@ #include #include +#include vm_t *vm_create(void) Index: src/proc/scheduler.c =================================================================== --- src/proc/scheduler.c (revision d89652555244d155a50d0893a409004587e7c475) +++ src/proc/scheduler.c (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -132,5 +132,5 @@ } - /* avoid deadlock with relink_rq */ + /* avoid deadlock with relink_rq() */ if (!spinlock_trylock(&CPU->lock)) { /* @@ -447,5 +447,4 @@ cpu = &cpus[(i + k) % config.cpu_active]; - r = &cpu->rq[j]; /* @@ -454,7 +453,8 @@ */ if (CPU == cpu) - continue; + continue; restart: pri = cpu_priority_high(); + r = &cpu->rq[j]; spinlock_lock(&r->lock); if (r->n == 0) { @@ -471,8 +471,9 @@ * We don't want to steal CPU-wired threads neither threads already stolen. * The latter prevents threads from migrating between CPU's without ever being run. - * We don't want to steal threads whose FPU context is still in CPU + * We don't want to steal threads whose FPU context is still in CPU. */ spinlock_lock(&t->lock); if ( (!(t->flags & (X_WIRED | X_STOLEN))) && (!(t->fpu_context_engaged)) ) { + /* * Remove t from r. Index: src/proc/thread.c =================================================================== --- src/proc/thread.c (revision d89652555244d155a50d0893a409004587e7c475) +++ src/proc/thread.c (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -177,5 +177,5 @@ frame_ks = frame_alloc(FRAME_KA); if (THREAD_USER_STACK & flags) { - frame_us = frame_alloc(0); + frame_us = frame_alloc(FRAME_KA); } Index: src/synch/semaphore.c =================================================================== --- src/synch/semaphore.c (revision d89652555244d155a50d0893a409004587e7c475) +++ src/synch/semaphore.c (revision 18e0a6cbb4a87376b6e5f46a009b38a9b0e50592) @@ -31,4 +31,5 @@ #include #include +#include void semaphore_initialize(semaphore_t *s, int val)