Index: kernel/arch/sparc64/Makefile.inc =================================================================== --- kernel/arch/sparc64/Makefile.inc (revision 5a4fef9166269adb2f4c2650c7bbc9f3b70f56ba) +++ kernel/arch/sparc64/Makefile.inc (revision 18baf9c0c35a8ee98eda033f039299251c422462) @@ -66,4 +66,5 @@ arch/$(KARCH)/src/cpu/$(USARCH)/cpu.c \ arch/$(KARCH)/src/asm.S \ + arch/$(KARCH)/src/$(USARCH)/asm.S \ arch/$(KARCH)/src/panic.S \ arch/$(KARCH)/src/console.c \ @@ -78,5 +79,5 @@ arch/$(KARCH)/src/$(USARCH)/sparc64.c \ arch/$(KARCH)/src/$(USARCH)/start.S \ - arch/$(KARCH)/src/proc/scheduler.c \ + arch/$(KARCH)/src/proc/$(USARCH)/scheduler.c \ arch/$(KARCH)/src/proc/thread.c \ arch/$(KARCH)/src/trap/$(USARCH)/mmu.S \ Index: kernel/arch/sparc64/include/arch.h =================================================================== --- kernel/arch/sparc64/include/arch.h (revision 5a4fef9166269adb2f4c2650c7bbc9f3b70f56ba) +++ kernel/arch/sparc64/include/arch.h (revision 18baf9c0c35a8ee98eda033f039299251c422462) @@ -38,9 +38,12 @@ #define KERN_sparc64_ARCH_H_ +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + #define ASI_AIUP 0x10 /** Access to primary context with user privileges. */ #define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ -#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ -#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ -#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ #define NWINDOWS 8 /** Number of register window sets. */ @@ -52,4 +55,5 @@ #endif /* __ASM__ */ + #endif Index: kernel/arch/sparc64/include/mm/mmu.h =================================================================== --- kernel/arch/sparc64/include/mm/mmu.h (revision 5a4fef9166269adb2f4c2650c7bbc9f3b70f56ba) +++ kernel/arch/sparc64/include/mm/mmu.h (revision 18baf9c0c35a8ee98eda033f039299251c422462) @@ -36,85 +36,10 @@ #define KERN_sparc64_MMU_H_ -#if defined(US) -/* LSU Control Register ASI. */ -#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include #endif -/* I-MMU ASIs. */ -#define ASI_IMMU 0x50 -#define ASI_IMMU_TSB_8KB_PTR_REG 0x51 -#define ASI_IMMU_TSB_64KB_PTR_REG 0x52 -#define ASI_ITLB_DATA_IN_REG 0x54 -#define ASI_ITLB_DATA_ACCESS_REG 0x55 -#define ASI_ITLB_TAG_READ_REG 0x56 -#define ASI_IMMU_DEMAP 0x57 - -/* Virtual Addresses within ASI_IMMU. */ -#define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ -#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ -#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ -#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ -#if defined (US3) -#define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */ -#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ -#endif - - -/* D-MMU ASIs. */ -#define ASI_DMMU 0x58 -#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 -#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a -#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b -#define ASI_DTLB_DATA_IN_REG 0x5c -#define ASI_DTLB_DATA_ACCESS_REG 0x5d -#define ASI_DTLB_TAG_READ_REG 0x5e -#define ASI_DMMU_DEMAP 0x5f - -/* Virtual Addresses within ASI_DMMU. */ -#define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ -#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ -#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ -#define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ -#define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ -#define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ -#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ -#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ -#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ -#if defined (US3) -#define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */ -#define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */ -#define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */ -#endif - -#ifndef __ASM__ - -#include -#include -#include - -#if defined(US) -/** LSU Control Register. */ -typedef union { - uint64_t value; - struct { - unsigned : 23; - unsigned pm : 8; - unsigned vm : 8; - unsigned pr : 1; - unsigned pw : 1; - unsigned vr : 1; - unsigned vw : 1; - unsigned : 1; - unsigned fm : 16; - unsigned dm : 1; /**< D-MMU enable. */ - unsigned im : 1; /**< I-MMU enable. */ - unsigned dc : 1; /**< D-Cache enable. */ - unsigned ic : 1; /**< I-Cache enable. */ - - } __attribute__ ((packed)); -} lsu_cr_reg_t; -#endif /* US */ - -#endif /* !def __ASM__ */ #endif Index: kernel/arch/sparc64/include/mm/sun4v/mmu.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/mmu.h (revision 5a4fef9166269adb2f4c2650c7bbc9f3b70f56ba) +++ kernel/arch/sparc64/include/mm/sun4v/mmu.h (revision 18baf9c0c35a8ee98eda033f039299251c422462) @@ -45,4 +45,106 @@ #define ASI_SECONDARY_CONTEXT_REG 0x21 /**< secondary context register ASI. */ + + + + + + + + + + +/* I-MMU ASIs. */ +#define ASI_IMMU 0x50 +#define ASI_IMMU_TSB_8KB_PTR_REG 0x51 +#define ASI_IMMU_TSB_64KB_PTR_REG 0x52 +#define ASI_ITLB_DATA_IN_REG 0x54 +#define ASI_ITLB_DATA_ACCESS_REG 0x55 +#define ASI_ITLB_TAG_READ_REG 0x56 +#define ASI_IMMU_DEMAP 0x57 + +/* Virtual Addresses within ASI_IMMU. */ +#define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ +#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ +#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ +#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ +#if defined (US3) +#define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */ +#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ +#endif + + +/* D-MMU ASIs. */ +#define ASI_DMMU 0x58 +#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 +#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a +#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b +#define ASI_DTLB_DATA_IN_REG 0x5c +#define ASI_DTLB_DATA_ACCESS_REG 0x5d +#define ASI_DTLB_TAG_READ_REG 0x5e +#define ASI_DMMU_DEMAP 0x5f + +/* Virtual Addresses within ASI_DMMU. */ +#define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ +#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ +#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ +#define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ +#define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ +#define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ +#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ +#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ +#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ +#if defined (US3) +#define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */ +#define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */ +#define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */ +#endif + +#ifndef __ASM__ + +#include +#include +#include + +#if defined(US) +/** LSU Control Register. */ +typedef union { + uint64_t value; + struct { + unsigned : 23; + unsigned pm : 8; + unsigned vm : 8; + unsigned pr : 1; + unsigned pw : 1; + unsigned vr : 1; + unsigned vw : 1; + unsigned : 1; + unsigned fm : 16; + unsigned dm : 1; /**< D-MMU enable. */ + unsigned im : 1; /**< I-MMU enable. */ + unsigned dc : 1; /**< D-Cache enable. */ + unsigned ic : 1; /**< I-Cache enable. */ + + } __attribute__ ((packed)); +} lsu_cr_reg_t; +#endif /* US */ + +#endif /* !def __ASM__ */ + + + + + + + + + + + + + + + + #endif Index: kernel/arch/sparc64/include/sun4u/arch.h =================================================================== --- kernel/arch/sparc64/include/sun4u/arch.h (revision 18baf9c0c35a8ee98eda033f039299251c422462) +++ kernel/arch/sparc64/include/sun4u/arch.h (revision 18baf9c0c35a8ee98eda033f039299251c422462) @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** + * @file + * @brief Various sun4u-specific macros. + */ + +#ifndef KERN_sparc64_sun4u_ARCH_H_ +#define KERN_sparc64_sun4u_ARCH_H_ + +#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ +#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ +#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/sun4v/arch.h =================================================================== --- kernel/arch/sparc64/include/sun4v/arch.h (revision 5a4fef9166269adb2f4c2650c7bbc9f3b70f56ba) +++ kernel/arch/sparc64/include/sun4v/arch.h (revision 18baf9c0c35a8ee98eda033f039299251c422462) @@ -58,4 +58,9 @@ #define SCRATCHPAD_WBUF 0x18 +//MH - remove when cpu.h is forked +#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ +#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ +#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ + #endif Index: kernel/arch/sparc64/include/sun4v/cpu.h =================================================================== --- kernel/arch/sparc64/include/sun4v/cpu.h (revision 5a4fef9166269adb2f4c2650c7bbc9f3b70f56ba) +++ kernel/arch/sparc64/include/sun4v/cpu.h (revision 18baf9c0c35a8ee98eda033f039299251c422462) @@ -55,4 +55,6 @@ } exec_unit_t; +// MH +#if 0 typedef struct cpu_arch { uint64_t id; /**< virtual processor ID */ @@ -65,4 +67,5 @@ so that cores are equally balanced. */ } cpu_arch_t; +#endif #endif Index: kernel/arch/sparc64/src/asm.S =================================================================== --- kernel/arch/sparc64/src/asm.S (revision 5a4fef9166269adb2f4c2650c7bbc9f3b70f56ba) +++ kernel/arch/sparc64/src/asm.S (revision 18baf9c0c35a8ee98eda033f039299251c422462) @@ -29,6 +29,4 @@ #include #include -#include -#include .text @@ -234,83 +232,2 @@ nop - -.macro WRITE_ALTERNATE_REGISTER reg, bit - rdpr %pstate, %g1 ! save PSTATE.PEF - wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate - mov %o0, \reg - wrpr %g0, PSTATE_PRIV_BIT, %pstate - retl - wrpr %g1, 0, %pstate ! restore PSTATE.PEF -.endm - -.macro READ_ALTERNATE_REGISTER reg, bit - rdpr %pstate, %g1 ! save PSTATE.PEF - wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate - mov \reg, %o0 - wrpr %g0, PSTATE_PRIV_BIT, %pstate - retl - wrpr %g1, 0, %pstate ! restore PSTATE.PEF -.endm - -.global write_to_ag_g6 -write_to_ag_g6: - WRITE_ALTERNATE_REGISTER %g6, PSTATE_AG_BIT - -.global write_to_ag_g7 -write_to_ag_g7: - WRITE_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT - -.global write_to_ig_g6 -write_to_ig_g6: - WRITE_ALTERNATE_REGISTER %g6, PSTATE_IG_BIT - -.global read_from_ag_g7 -read_from_ag_g7: - READ_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT - - -/** Switch to userspace. - * - * %o0 Userspace entry address. - * %o1 Userspace stack pointer address. - * %o2 Userspace address of uarg structure. - */ -.global switch_to_userspace -switch_to_userspace: - save %o1, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp - flushw - wrpr %g0, 0, %cleanwin ! avoid information leak - - mov %i2, %o0 ! uarg - xor %o1, %o1, %o1 ! %o1 is defined to hold pcb_ptr - ! set it to 0 - - clr %i2 - clr %i3 - clr %i4 - clr %i5 - clr %i6 - - wrpr %g0, 1, %tl ! enforce mapping via nucleus - - rdpr %cwp, %g1 - wrpr %g1, TSTATE_IE_BIT, %tstate - wrpr %i0, 0, %tnpc - - /* - * Set primary context according to secondary context. - * Secondary context has been already installed by - * higher-level functions. - */ - wr %g0, ASI_DMMU, %asi - ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1 - stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi - flush %i7 - - /* - * Spills and fills will be handled by the userspace handlers. - */ - wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate - - done ! jump to userspace - Index: rnel/arch/sparc64/src/proc/scheduler.c =================================================================== --- kernel/arch/sparc64/src/proc/scheduler.c (revision 5a4fef9166269adb2f4c2650c7bbc9f3b70f56ba) +++ (revision ) @@ -1,83 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64proc - * @{ - */ -/** @file - */ - -#include -#include -#include -#include -#include - -/** Perform sparc64 specific tasks needed before the new task is run. */ -void before_task_runs_arch(void) -{ -} - -/** Perform sparc64 specific steps before scheduling a thread. - * - * For userspace threads, initialize reserved global registers in the alternate - * and interrupt sets. - */ -void before_thread_runs_arch(void) -{ - if ((THREAD->flags & THREAD_FLAG_USPACE)) { - /* - * Write kernel stack address to %g6 of the alternate and - * interrupt global sets. - * - * Write pointer to the last item in the userspace window buffer - * to %g7 in the alternate set. Write to the interrupt %g7 is - * not necessary because: - * - spill traps operate only in the alternate global set, - * - preemptible trap handler switches to alternate globals - * before it explicitly uses %g7. - */ - uint64_t sp = (uintptr_t) THREAD->kstack + STACK_SIZE - - (STACK_BIAS + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)); - write_to_ig_g6(sp); - write_to_ag_g6(sp); - write_to_ag_g7((uintptr_t) THREAD->arch.uspace_window_buffer); - } -} - -/** Perform sparc64 specific steps before a thread stops running. */ -void after_thread_ran_arch(void) -{ - if ((THREAD->flags & THREAD_FLAG_USPACE)) { - /* sample the state of the userspace window buffer */ - THREAD->arch.uspace_window_buffer = (uint8_t *) read_from_ag_g7(); - } -} - -/** @} - */ Index: kernel/arch/sparc64/src/proc/sun4v/scheduler.c =================================================================== --- kernel/arch/sparc64/src/proc/sun4v/scheduler.c (revision 5a4fef9166269adb2f4c2650c7bbc9f3b70f56ba) +++ kernel/arch/sparc64/src/proc/sun4v/scheduler.c (revision 18baf9c0c35a8ee98eda033f039299251c422462) @@ -1,5 +1,4 @@ /* * Copyright (c) 2006 Jakub Jermar - * Copyright (c) 2009 Pavel Rimsky * All rights reserved. * @@ -38,7 +37,7 @@ #include #include +#include #include #include -#include #include Index: kernel/arch/sparc64/src/sun4u/asm.S =================================================================== --- kernel/arch/sparc64/src/sun4u/asm.S (revision 18baf9c0c35a8ee98eda033f039299251c422462) +++ kernel/arch/sparc64/src/sun4u/asm.S (revision 18baf9c0c35a8ee98eda033f039299251c422462) @@ -0,0 +1,117 @@ +# +# Copyright (c) 2005 Jakub Jermar +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +#include +#include +#include +#include + +.text + +.register %g2, #scratch +.register %g3, #scratch + +.macro WRITE_ALTERNATE_REGISTER reg, bit + rdpr %pstate, %g1 ! save PSTATE.PEF + wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate + mov %o0, \reg + wrpr %g0, PSTATE_PRIV_BIT, %pstate + retl + wrpr %g1, 0, %pstate ! restore PSTATE.PEF +.endm + +.macro READ_ALTERNATE_REGISTER reg, bit + rdpr %pstate, %g1 ! save PSTATE.PEF + wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate + mov \reg, %o0 + wrpr %g0, PSTATE_PRIV_BIT, %pstate + retl + wrpr %g1, 0, %pstate ! restore PSTATE.PEF +.endm + +.global write_to_ag_g6 +write_to_ag_g6: + WRITE_ALTERNATE_REGISTER %g6, PSTATE_AG_BIT + +.global write_to_ag_g7 +write_to_ag_g7: + WRITE_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT + +.global write_to_ig_g6 +write_to_ig_g6: + WRITE_ALTERNATE_REGISTER %g6, PSTATE_IG_BIT + +.global read_from_ag_g7 +read_from_ag_g7: + READ_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT + +/** Switch to userspace. + * + * %o0 Userspace entry address. + * %o1 Userspace stack pointer address. + * %o2 Userspace address of uarg structure. + */ +.global switch_to_userspace +switch_to_userspace: + save %o1, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp + flushw + wrpr %g0, 0, %cleanwin ! avoid information leak + + mov %i2, %o0 ! uarg + xor %o1, %o1, %o1 ! %o1 is defined to hold pcb_ptr + ! set it to 0 + + clr %i2 + clr %i3 + clr %i4 + clr %i5 + clr %i6 + + wrpr %g0, 1, %tl ! enforce mapping via nucleus + + rdpr %cwp, %g1 + wrpr %g1, TSTATE_IE_BIT, %tstate + wrpr %i0, 0, %tnpc + + /* + * Set primary context according to secondary context. + * Secondary context has been already installed by + * higher-level functions. + */ + wr %g0, ASI_DMMU, %asi + ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1 + stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi + flush %i7 + + /* + * Spills and fills will be handled by the userspace handlers. + */ + wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate + + done ! jump to userspace + Index: kernel/arch/sparc64/src/sun4v/asm.S =================================================================== --- kernel/arch/sparc64/src/sun4v/asm.S (revision 18baf9c0c35a8ee98eda033f039299251c422462) +++ kernel/arch/sparc64/src/sun4v/asm.S (revision 18baf9c0c35a8ee98eda033f039299251c422462) @@ -0,0 +1,78 @@ +# +# Copyright (c) 2008 Pavel Rimsky +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +#include +#include +#include + +.text + +/** Switch to userspace. + * + * %o0 Userspace entry address. + * %o1 Userspace stack pointer address. + * %o2 Userspace address of uarg structure. + */ +.global switch_to_userspace +switch_to_userspace: + wrpr PSTATE_PRIV_BIT, %pstate + save %o1, -STACK_WINDOW_SAVE_AREA_SIZE, %sp + flushw + wrpr %g0, 0, %cleanwin ! avoid information leak + + mov %i2, %o0 ! uarg + xor %o1, %o1, %o1 ! %o1 is defined to hold pcb_ptr + ! set it to 0 + clr %i2 + clr %i3 + clr %i4 + clr %i5 + clr %i6 + wrpr %g0, 1, %tl ! enforce mapping via nucleus + + rdpr %cwp, %g1 + wrpr %g1, TSTATE_IE_BIT, %tstate + wrpr %i0, 0, %tnpc + + /* + * Set primary context according to secondary context. + * Secondary context has been already installed by + * higher-level functions. + */ + wr %g0, ASI_SECONDARY_CONTEXT_REG, %asi + ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1 + wr %g0, ASI_PRIMARY_CONTEXT_REG, %asi + stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi + flush %i7 + + /* + * Spills and fills will be handled by the userspace handlers. + */ + wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate + + done ! jump to userspace