Changeset 18baf9c0 in mainline


Ignore:
Timestamp:
2009-11-20T17:14:32Z (15 years ago)
Author:
Pavel Rimsky <pavel@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
3da11f37
Parents:
5a4fef9
Message:

Sources forked into sun4u and sun4v versions such that sun4u and sun4v have separate switch_to_userspace routines.

Location:
kernel/arch/sparc64
Files:
3 added
1 deleted
8 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/Makefile.inc

    r5a4fef9 r18baf9c0  
    6666        arch/$(KARCH)/src/cpu/$(USARCH)/cpu.c \
    6767        arch/$(KARCH)/src/asm.S \
     68        arch/$(KARCH)/src/$(USARCH)/asm.S \
    6869        arch/$(KARCH)/src/panic.S \
    6970        arch/$(KARCH)/src/console.c \
    … …  
    7879        arch/$(KARCH)/src/$(USARCH)/sparc64.c \
    7980        arch/$(KARCH)/src/$(USARCH)/start.S \
    80         arch/$(KARCH)/src/proc/scheduler.c \
     81        arch/$(KARCH)/src/proc/$(USARCH)/scheduler.c \
    8182        arch/$(KARCH)/src/proc/thread.c \
    8283        arch/$(KARCH)/src/trap/$(USARCH)/mmu.S \

  • kernel/arch/sparc64/include/arch.h

    r5a4fef9 r18baf9c0  
    3838#define KERN_sparc64_ARCH_H_
    3939
     40#if defined (SUN4U)
     41#include <arch/sun4u/arch.h>
     42#elif defined (SUN4V)
     43#include <arch/sun4v/arch.h>
     44#endif
     45
    4046#define ASI_AIUP                0x10    /** Access to primary context with user privileges. */
    4147#define ASI_AIUS                0x11    /** Access to secondary context with user privileges. */
    42 #define ASI_NUCLEUS_QUAD_LDD    0x24    /** ASI for 16-byte atomic loads. */
    43 #define ASI_DCACHE_TAG          0x47    /** ASI D-Cache Tag. */
    44 #define ASI_ICBUS_CONFIG                0x4a    /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */
    4548
    4649#define NWINDOWS                8       /** Number of register window sets. */
    … …  
    5255#endif /* __ASM__ */
    5356
     57
    5458#endif
    5559

  • kernel/arch/sparc64/include/mm/mmu.h

    r5a4fef9 r18baf9c0  
    3636#define KERN_sparc64_MMU_H_
    3737
    38 #if defined(US)
    39 /* LSU Control Register ASI. */
    40 #define ASI_LSU_CONTROL_REG             0x45    /**< Load/Store Unit Control Register. */
     38#if defined (SUN4U)
     39#include <arch/mm/sun4u/mmu.h>
     40#elif defined (SUN4V)
     41#include <arch/mm/sun4v/mmu.h>
    4142#endif
    4243
    43 /* I-MMU ASIs. */
    44 #define ASI_IMMU                        0x50
    45 #define ASI_IMMU_TSB_8KB_PTR_REG        0x51   
    46 #define ASI_IMMU_TSB_64KB_PTR_REG       0x52
    47 #define ASI_ITLB_DATA_IN_REG            0x54
    48 #define ASI_ITLB_DATA_ACCESS_REG        0x55
    49 #define ASI_ITLB_TAG_READ_REG           0x56
    50 #define ASI_IMMU_DEMAP                  0x57
    51 
    52 /* Virtual Addresses within ASI_IMMU. */
    53 #define VA_IMMU_TSB_TAG_TARGET          0x0     /**< IMMU TSB tag target register. */
    54 #define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
    55 #define VA_IMMU_TSB_BASE                0x28    /**< IMMU TSB base register. */
    56 #define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
    57 #if defined (US3)
    58 #define VA_IMMU_PRIMARY_EXTENSION       0x48    /**< IMMU TSB primary extension register */
    59 #define VA_IMMU_NUCLEUS_EXTENSION       0x58    /**< IMMU TSB nucleus extension register */
    60 #endif
    61 
    62 
    63 /* D-MMU ASIs. */
    64 #define ASI_DMMU                        0x58
    65 #define ASI_DMMU_TSB_8KB_PTR_REG        0x59   
    66 #define ASI_DMMU_TSB_64KB_PTR_REG       0x5a
    67 #define ASI_DMMU_TSB_DIRECT_PTR_REG     0x5b
    68 #define ASI_DTLB_DATA_IN_REG            0x5c
    69 #define ASI_DTLB_DATA_ACCESS_REG        0x5d
    70 #define ASI_DTLB_TAG_READ_REG           0x5e
    71 #define ASI_DMMU_DEMAP                  0x5f
    72 
    73 /* Virtual Addresses within ASI_DMMU. */
    74 #define VA_DMMU_TSB_TAG_TARGET          0x0     /**< DMMU TSB tag target register. */
    75 #define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */
    76 #define VA_SECONDARY_CONTEXT_REG        0x10    /**< DMMU secondary context register. */
    77 #define VA_DMMU_SFSR                    0x18    /**< DMMU sync fault status register. */
    78 #define VA_DMMU_SFAR                    0x20    /**< DMMU sync fault address register. */
    79 #define VA_DMMU_TSB_BASE                0x28    /**< DMMU TSB base register. */
    80 #define VA_DMMU_TAG_ACCESS              0x30    /**< DMMU TLB tag access register. */
    81 #define VA_DMMU_VA_WATCHPOINT_REG       0x38    /**< DMMU VA data watchpoint register. */
    82 #define VA_DMMU_PA_WATCHPOINT_REG       0x40    /**< DMMU PA data watchpoint register. */
    83 #if defined (US3)
    84 #define VA_DMMU_PRIMARY_EXTENSION       0x48    /**< DMMU TSB primary extension register */
    85 #define VA_DMMU_SECONDARY_EXTENSION     0x50    /**< DMMU TSB secondary extension register */
    86 #define VA_DMMU_NUCLEUS_EXTENSION       0x58    /**< DMMU TSB nucleus extension register */
    87 #endif
    88 
    89 #ifndef __ASM__
    90 
    91 #include <arch/asm.h>
    92 #include <arch/barrier.h>
    93 #include <arch/types.h>
    94 
    95 #if defined(US)
    96 /** LSU Control Register. */
    97 typedef union {
    98         uint64_t value;
    99         struct {
    100                 unsigned : 23;
    101                 unsigned pm : 8;
    102                 unsigned vm : 8;
    103                 unsigned pr : 1;
    104                 unsigned pw : 1;
    105                 unsigned vr : 1;
    106                 unsigned vw : 1;
    107                 unsigned : 1;
    108                 unsigned fm : 16;       
    109                 unsigned dm : 1;        /**< D-MMU enable. */
    110                 unsigned im : 1;        /**< I-MMU enable. */
    111                 unsigned dc : 1;        /**< D-Cache enable. */
    112                 unsigned ic : 1;        /**< I-Cache enable. */
    113                
    114         } __attribute__ ((packed));
    115 } lsu_cr_reg_t;
    116 #endif /* US */
    117 
    118 #endif /* !def __ASM__ */
    11944
    12045#endif

  • kernel/arch/sparc64/include/mm/sun4v/mmu.h

    r5a4fef9 r18baf9c0  
    4545#define ASI_SECONDARY_CONTEXT_REG       0x21    /**< secondary context register ASI. */
    4646
     47
     48
     49
     50
     51
     52
     53
     54
     55
     56
     57/* I-MMU ASIs. */
     58#define ASI_IMMU                        0x50
     59#define ASI_IMMU_TSB_8KB_PTR_REG        0x51   
     60#define ASI_IMMU_TSB_64KB_PTR_REG       0x52
     61#define ASI_ITLB_DATA_IN_REG            0x54
     62#define ASI_ITLB_DATA_ACCESS_REG        0x55
     63#define ASI_ITLB_TAG_READ_REG           0x56
     64#define ASI_IMMU_DEMAP                  0x57
     65
     66/* Virtual Addresses within ASI_IMMU. */
     67#define VA_IMMU_TSB_TAG_TARGET          0x0     /**< IMMU TSB tag target register. */
     68#define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
     69#define VA_IMMU_TSB_BASE                0x28    /**< IMMU TSB base register. */
     70#define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
     71#if defined (US3)
     72#define VA_IMMU_PRIMARY_EXTENSION       0x48    /**< IMMU TSB primary extension register */
     73#define VA_IMMU_NUCLEUS_EXTENSION       0x58    /**< IMMU TSB nucleus extension register */
     74#endif
     75
     76
     77/* D-MMU ASIs. */
     78#define ASI_DMMU                        0x58
     79#define ASI_DMMU_TSB_8KB_PTR_REG        0x59   
     80#define ASI_DMMU_TSB_64KB_PTR_REG       0x5a
     81#define ASI_DMMU_TSB_DIRECT_PTR_REG     0x5b
     82#define ASI_DTLB_DATA_IN_REG            0x5c
     83#define ASI_DTLB_DATA_ACCESS_REG        0x5d
     84#define ASI_DTLB_TAG_READ_REG           0x5e
     85#define ASI_DMMU_DEMAP                  0x5f
     86
     87/* Virtual Addresses within ASI_DMMU. */
     88#define VA_DMMU_TSB_TAG_TARGET          0x0     /**< DMMU TSB tag target register. */
     89#define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */
     90#define VA_SECONDARY_CONTEXT_REG        0x10    /**< DMMU secondary context register. */
     91#define VA_DMMU_SFSR                    0x18    /**< DMMU sync fault status register. */
     92#define VA_DMMU_SFAR                    0x20    /**< DMMU sync fault address register. */
     93#define VA_DMMU_TSB_BASE                0x28    /**< DMMU TSB base register. */
     94#define VA_DMMU_TAG_ACCESS              0x30    /**< DMMU TLB tag access register. */
     95#define VA_DMMU_VA_WATCHPOINT_REG       0x38    /**< DMMU VA data watchpoint register. */
     96#define VA_DMMU_PA_WATCHPOINT_REG       0x40    /**< DMMU PA data watchpoint register. */
     97#if defined (US3)
     98#define VA_DMMU_PRIMARY_EXTENSION       0x48    /**< DMMU TSB primary extension register */
     99#define VA_DMMU_SECONDARY_EXTENSION     0x50    /**< DMMU TSB secondary extension register */
     100#define VA_DMMU_NUCLEUS_EXTENSION       0x58    /**< DMMU TSB nucleus extension register */
     101#endif
     102
     103#ifndef __ASM__
     104
     105#include <arch/asm.h>
     106#include <arch/barrier.h>
     107#include <arch/types.h>
     108
     109#if defined(US)
     110/** LSU Control Register. */
     111typedef union {
     112        uint64_t value;
     113        struct {
     114                unsigned : 23;
     115                unsigned pm : 8;
     116                unsigned vm : 8;
     117                unsigned pr : 1;
     118                unsigned pw : 1;
     119                unsigned vr : 1;
     120                unsigned vw : 1;
     121                unsigned : 1;
     122                unsigned fm : 16;       
     123                unsigned dm : 1;        /**< D-MMU enable. */
     124                unsigned im : 1;        /**< I-MMU enable. */
     125                unsigned dc : 1;        /**< D-Cache enable. */
     126                unsigned ic : 1;        /**< I-Cache enable. */
     127               
     128        } __attribute__ ((packed));
     129} lsu_cr_reg_t;
     130#endif /* US */
     131
     132#endif /* !def __ASM__ */
     133
     134
     135
     136
     137
     138
     139
     140
     141
     142
     143
     144
     145
     146
     147
     148
    47149#endif
    48150

  • kernel/arch/sparc64/include/sun4v/arch.h

    r5a4fef9 r18baf9c0  
    5858#define SCRATCHPAD_WBUF         0x18
    5959
     60//MH - remove when cpu.h is forked
     61#define ASI_NUCLEUS_QUAD_LDD    0x24    /** ASI for 16-byte atomic loads. */
     62#define ASI_DCACHE_TAG          0x47    /** ASI D-Cache Tag. */
     63#define ASI_ICBUS_CONFIG        0x4a    /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */
     64
    6065#endif
    6166

  • kernel/arch/sparc64/include/sun4v/cpu.h

    r5a4fef9 r18baf9c0  
    5555} exec_unit_t;
    5656
     57// MH
     58#if 0
    5759typedef struct cpu_arch {
    5860        uint64_t id;                    /**< virtual processor ID */
    … …  
    6567                                             so that cores are equally balanced. */
    6668} cpu_arch_t;
     69#endif
    6770
    6871#endif 

  • kernel/arch/sparc64/src/asm.S

    r5a4fef9 r18baf9c0  
    2929#include <arch/arch.h>
    3030#include <arch/stack.h>
    31 #include <arch/regdef.h>
    32 #include <arch/mm/mmu.h>
    3331
    3432.text
    … …  
    234232        nop
    235233
    236 
    237 .macro WRITE_ALTERNATE_REGISTER reg, bit
    238         rdpr %pstate, %g1                               ! save PSTATE.PEF
    239         wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
    240         mov %o0, \reg
    241         wrpr %g0, PSTATE_PRIV_BIT, %pstate
    242         retl
    243         wrpr %g1, 0, %pstate                            ! restore PSTATE.PEF
    244 .endm
    245 
    246 .macro READ_ALTERNATE_REGISTER reg, bit
    247         rdpr %pstate, %g1                               ! save PSTATE.PEF
    248         wrpr %g0, (\bit | PSTATE_PRIV_BIT), %pstate
    249         mov \reg, %o0
    250         wrpr %g0, PSTATE_PRIV_BIT, %pstate
    251         retl
    252         wrpr %g1, 0, %pstate                            ! restore PSTATE.PEF
    253 .endm
    254 
    255 .global write_to_ag_g6
    256 write_to_ag_g6:
    257         WRITE_ALTERNATE_REGISTER %g6, PSTATE_AG_BIT
    258 
    259 .global write_to_ag_g7
    260 write_to_ag_g7:
    261         WRITE_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT
    262 
    263 .global write_to_ig_g6
    264 write_to_ig_g6:
    265         WRITE_ALTERNATE_REGISTER %g6, PSTATE_IG_BIT
    266 
    267 .global read_from_ag_g7
    268 read_from_ag_g7:
    269         READ_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT
    270 
    271 
    272 /** Switch to userspace.
    273  *
    274  * %o0  Userspace entry address.
    275  * %o1  Userspace stack pointer address.
    276  * %o2  Userspace address of uarg structure.
    277  */
    278 .global switch_to_userspace
    279 switch_to_userspace:
    280         save %o1, -(STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE), %sp
    281         flushw
    282         wrpr %g0, 0, %cleanwin          ! avoid information leak
    283 
    284         mov %i2, %o0                    ! uarg
    285         xor %o1, %o1, %o1               ! %o1 is defined to hold pcb_ptr
    286                                         ! set it to 0
    287 
    288         clr %i2
    289         clr %i3
    290         clr %i4
    291         clr %i5
    292         clr %i6
    293 
    294         wrpr %g0, 1, %tl                ! enforce mapping via nucleus
    295 
    296         rdpr %cwp, %g1
    297         wrpr %g1, TSTATE_IE_BIT, %tstate
    298         wrpr %i0, 0, %tnpc
    299        
    300         /*
    301          * Set primary context according to secondary context.
    302          * Secondary context has been already installed by
    303          * higher-level functions.
    304          */
    305         wr %g0, ASI_DMMU, %asi
    306         ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1
    307         stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi
    308         flush %i7
    309 
    310         /*
    311          * Spills and fills will be handled by the userspace handlers.
    312          */
    313         wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate
    314        
    315         done                            ! jump to userspace
    316 

  • kernel/arch/sparc64/src/proc/sun4v/scheduler.c

    r5a4fef9 r18baf9c0  
    11/*
    22 * Copyright (c) 2006 Jakub Jermar
    3  * Copyright (c) 2009 Pavel Rimsky
    43 * All rights reserved.
    54 *
    … …  
    3837#include <arch.h>
    3938#include <arch/asm.h>
     39#include <arch/arch.h>
    4040#include <arch/stack.h>
    4141#include <arch/sun4v/cpu.h>
    42 #include <arch/sun4v/arch.h>
    4342#include <arch/sun4v/hypercall.h>
    4443
Note: See TracChangeset for help on using the changeset viewer.