Index: HelenOS.config
===================================================================
--- HelenOS.config	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ HelenOS.config	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -65,4 +65,5 @@
 @ "integratorcp" Integratorcp
 @ "beagleboardxm" BeogleBoard-xM
+@ "beaglebone" BeogleBone
 ! [PLATFORM=arm32] MACHINE (choice)
 
@@ -96,5 +97,5 @@
 % CPU type
 @ "armv7_a" ARMv7-A
-! [PLATFORM=arm32&MACHINE=beagleboardxm] PROCESSOR (choice)
+! [PLATFORM=arm32&(MACHINE=beagleboardxm|MACHINE=beaglebone)] PROCESSOR (choice)
 
 % RAM disk format
@@ -425,5 +426,5 @@
 % Output device class
 @ "generic" Monitor or serial line
-! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp|MACHINE=beagleboardxm)] CONFIG_HID_OUT (choice)
+! [PLATFORM=arm32&(MACHINE=gta02|MACHINE=integratorcp|MACHINE=beagleboardxm|MACHINE=beaglebone)] CONFIG_HID_OUT (choice)
 
 % Output device class
@@ -472,5 +473,11 @@
 ! [PLATFORM=arm32&MACHINE=gta02] CONFIG_S3C24XX_IRQC (y)
 
-% Support for TI AMDM37X on-chip UART
+% Support for TI AM335x on-chip UART
+! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beaglebone] CONFIG_AM335X_UART (y/n)
+
+% Support for TI AM335x timers support
+! [PLATFORM=arm32&MACHINE=beaglebone] CONFIG_AM335X_TIMERS (y)
+
+% Support for TI AMDM37x on-chip UART
 ! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&PLATFORM=arm32&MACHINE=beagleboardxm] CONFIG_AMDM37X_UART (y/n)
 
@@ -494,5 +501,5 @@
 
 % Serial line input module
-! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=arm32&MACHINE=beagleboardxm&CONFIG_AMDM37X_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
+! [CONFIG_DSRLNIN=y|(PLATFORM=arm32&MACHINE=gta02)|(PLATFORM=arm32&MACHINE=integratorcp&CONFIG_ARM926_UART=y)|(PLATFORM=arm32&MACHINE=beaglebone&CONFIG_AM335X_UART=y)|(PLATFORM=arm32&MACHINE=beagleboardxm&CONFIG_AMDM37X_UART=y)|(PLATFORM=ia64&MACHINE=i460GX&CONFIG_NS16550=y)|(PLATFORM=ia64&MACHINE=ski)|(PLATFORM=sparc64&PROCESSOR=sun4v)] CONFIG_SRLN (y)
 
 % EGA support
Index: boot/arch/arm32/Makefile.inc
===================================================================
--- boot/arch/arm32/Makefile.inc	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ boot/arch/arm32/Makefile.inc	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -35,5 +35,5 @@
 endif
 
-ifeq ($(MACHINE), beagleboardxm)
+ifeq ($(MACHINE), $(filter $(MACHINE),beagleboardxm beaglebone))
 	BOOT_OUTPUT = image.boot
 	POST_OUTPUT = $(ROOT_PATH)/uImage.bin
Index: defaults/arm32/beaglebone/Makefile.config
===================================================================
--- defaults/arm32/beaglebone/Makefile.config	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ defaults/arm32/beaglebone/Makefile.config	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,8 @@
+# Machine type
+MACHINE = beaglebone
+
+# RAM disk format
+RDFMT = fat
+
+#framebuffer
+CONFIG_FB = n
Index: kernel/arch/arm32/Makefile.inc
===================================================================
--- kernel/arch/arm32/Makefile.inc	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ kernel/arch/arm32/Makefile.inc	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -84,4 +84,8 @@
 endif
 
+ifeq ($(MACHINE),beaglebone)
+        ARCH_SOURCES += arch/$(KARCH)/src/mach/beaglebone/beaglebone.c
+endif
+
 ifeq ($(CONFIG_PL050),y)
 	ARCH_SOURCES += genarch/src/drivers/pl050/pl050.c
Index: kernel/arch/arm32/include/mach/beaglebone/beaglebone.h
===================================================================
--- kernel/arch/arm32/include/mach/beaglebone/beaglebone.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/arch/arm32/include/mach/beaglebone/beaglebone.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2012 Matteo Facchinetti
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup arm32beaglebone beaglebone
+ *  @brief BeagleBone platform.
+ *  @ingroup arm32
+ * @{
+ */
+/** @file
+ *  @brief BeagleBone platform driver.
+ */
+
+#ifndef KERN_arm32_beaglebone_H_
+#define KERN_arm32_beaglebone_H_
+
+#include <arch/machine_func.h>
+
+extern struct arm_machine_ops bbone_machine_ops;
+
+#endif
+
+/** @}
+ */
+
Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c
===================================================================
--- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -35,8 +35,8 @@
 #include <arch/exception.h>
 #include <arch/mach/beagleboardxm/beagleboardxm.h>
-#include <genarch/drivers/amdm37x_irc/amdm37x_irc.h>
-#include <genarch/drivers/amdm37x_uart/amdm37x_uart.h>
-#include <genarch/drivers/amdm37x_gpt/amdm37x_gpt.h>
-#include <genarch/drivers/amdm37x_dispc/amdm37x_dispc.h>
+#include <genarch/drivers/amdm37x/uart.h>
+#include <genarch/drivers/amdm37x/irc.h>
+#include <genarch/drivers/amdm37x/gpt.h>
+#include <genarch/drivers/amdm37x/dispc.h>
 #include <genarch/fb/fb.h>
 #include <genarch/srln/srln.h>
Index: kernel/arch/arm32/src/mach/beaglebone/beaglebone.c
===================================================================
--- kernel/arch/arm32/src/mach/beaglebone/beaglebone.c	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/arch/arm32/src/mach/beaglebone/beaglebone.c	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2012 Matteo Facchinetti
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup arm32beaglebone
+ * @{
+ */
+/** @file
+ *  @brief BeagleBone platform driver.
+ */
+
+#include <arch/exception.h>
+#include <arch/mach/beaglebone/beaglebone.h>
+#include <genarch/drivers/am335x/irc.h>
+#include <genarch/drivers/am335x/uart.h>
+#include <genarch/drivers/am335x/timer.h>
+#include <genarch/srln/srln.h>
+#include <interrupt.h>
+#include <ddi/ddi.h>
+#include <ddi/device.h>
+#include <mm/km.h>
+
+static void bbone_init(void);
+static void bbone_timer_irq_start(void);
+static void bbone_cpu_halt(void);
+static void bbone_get_memory_extents(uintptr_t *start, size_t *size);
+static void bbone_irq_exception(unsigned int exc_no, istate_t *istate);
+static void bbone_frame_init(void);
+static void bbone_output_init(void);
+static void bbone_input_init(void);
+static size_t bbone_get_irq_count(void);
+static const char *bbone_get_platform_name(void);
+
+static struct beaglebone {
+	am335x_irc_regs_t *irc_addr;
+	am335x_timer_t timer;
+	am335x_uart_t uart;
+} bbone;
+
+struct arm_machine_ops bbone_machine_ops = {
+	.machine_init = bbone_init,
+	.machine_timer_irq_start = bbone_timer_irq_start,
+	.machine_cpu_halt = bbone_cpu_halt,
+	.machine_get_memory_extents = bbone_get_memory_extents,
+	.machine_irq_exception = bbone_irq_exception,
+	.machine_frame_init = bbone_frame_init,
+	.machine_output_init = bbone_output_init,
+	.machine_input_init = bbone_input_init,
+	.machine_get_irq_count = bbone_get_irq_count,
+	.machine_get_platform_name = bbone_get_platform_name,
+};
+
+static void bbone_init(void)
+{
+	/* Initialize the interrupt controller */
+	bbone.irc_addr = (void *) km_map(AM335x_IRC_BASE_ADDRESS,
+	    AM335x_IRC_SIZE, PAGE_NOT_CACHEABLE);
+
+	am335x_irc_init(bbone.irc_addr);
+}
+
+static irq_ownership_t bbone_timer_irq_claim(irq_t *irq)
+{
+	return IRQ_ACCEPT;
+}
+
+static void bbone_timer_irq_handler(irq_t *irq)
+{
+	am335x_timer_intr_ack(&bbone.timer);
+	spinlock_unlock(&irq->lock);
+	clock();
+	spinlock_lock(&irq->lock);
+}
+
+static void bbone_timer_irq_start(void)
+{
+	/* Initialize the IRQ */
+	static irq_t timer_irq;
+	irq_initialize(&timer_irq);
+	timer_irq.devno = device_assign_devno();
+	timer_irq.inr = AM335x_DMTIMER0_IRQ;
+	timer_irq.claim = bbone_timer_irq_claim;
+	timer_irq.handler = bbone_timer_irq_handler;
+	irq_register(&timer_irq);
+
+	/* Initialize the DMTIMER0 */
+	am335x_timer_init(&bbone.timer, DMTIMER0, HZ);
+	/* Enable the interrupt */
+	am335x_irc_enable(bbone.irc_addr, AM335x_DMTIMER0_IRQ);
+	/* Start the timer */
+	am335x_timer_start(&bbone.timer);
+}
+
+static void bbone_cpu_halt(void)
+{
+	while (1);
+}
+
+/** Get extents of available memory.
+ *
+ * @param start		Place to store memory start address (physical).
+ * @param size		Place to store memory size.
+ */
+static void bbone_get_memory_extents(uintptr_t *start, size_t *size)
+{
+}
+
+static void bbone_irq_exception(unsigned int exc_no, istate_t *istate)
+{
+}
+
+static void bbone_frame_init(void)
+{
+}
+
+static void bbone_output_init(void)
+{
+	const bool ok = am335x_uart_init(&bbone.uart,
+	    AM335x_UART0_IRQ, AM335x_UART0_BASE_ADDRESS,
+	    AM335x_UART0_SIZE);
+
+	if (ok)
+		stdout_wire(&bbone.uart.outdev);
+}
+
+static void bbone_input_init(void)
+{
+	srln_instance_t *srln_instance = srln_init();
+	if (srln_instance) {
+		indev_t *sink = stdin_wire();
+		indev_t *srln = srln_wire(srln_instance, sink);
+		am335x_uart_input_wire(&bbone.uart, srln);
+		am335x_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ);
+	}
+}
+
+size_t bbone_get_irq_count(void)
+{
+	return AM335x_IRC_IRQ_COUNT;
+}
+
+const char *bbone_get_platform_name(void)
+{
+	return "beaglebone";
+}
+
+/**
+ * @}
+ */
+
Index: kernel/arch/arm32/src/machine_func.c
===================================================================
--- kernel/arch/arm32/src/machine_func.c	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ kernel/arch/arm32/src/machine_func.c	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -42,4 +42,5 @@
 #include <arch/mach/integratorcp/integratorcp.h>
 #include <arch/mach/beagleboardxm/beagleboardxm.h>
+#include <arch/mach/beaglebone/beaglebone.h>
 
 /** Pointer to machine_ops structure being used. */
@@ -55,4 +56,6 @@
 #elif defined(MACHINE_beagleboardxm)
 	machine_ops = &bbxm_machine_ops;
+#elif defined(MACHINE_beaglebone)
+	machine_ops = &bbone_machine_ops;
 #else
 #error Machine type not defined.
Index: kernel/genarch/Makefile.inc
===================================================================
--- kernel/genarch/Makefile.inc	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ kernel/genarch/Makefile.inc	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -106,7 +106,17 @@
 endif
 
+ifeq ($(CONFIG_AM335X_UART),y)
+	GENARCH_SOURCES += \
+		genarch/src/drivers/am335x/uart.c
+endif
+
+ifeq ($(CONFIG_AM335X_TIMERS),y)
+	GENARCH_SOURCES += \
+		genarch/src/drivers/am335x/timer.c
+endif
+
 ifeq ($(CONFIG_AMDM37X_UART),y)
 	GENARCH_SOURCES += \
-		genarch/src/drivers/amdm37x_uart/amdm37x_uart.c
+		genarch/src/drivers/amdm37x/uart.c
 endif
 
Index: kernel/genarch/include/drivers/am335x/iomux.h
===================================================================
--- kernel/genarch/include/drivers/am335x/iomux.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/include/drivers/am335x/iomux.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2012 Matteo Facchinetti
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x CONTROL_MODULE: I/O multiplexing.
+ */
+
+#ifndef KERN_AM335X_IOMUX_H_
+#define KERN_AM335X_IOMUX_H_
+
+#include <typedefs.h>
+
+/* Pad Control Register for each configurable pin p. 876 */
+#define AM335X_IOMUX_SLEWRATE_SLOW_FLAG  (1 << 6)
+#define AM335X_IOMUX_RX_ENABLE_FLAG  (1 << 5)
+#define AM335X_IOMUX_PULLUP_FLAG  (1 << 4)
+#define AM335X_IOMUX_PULLUPDOWN_ENABLE_FLAG  (1 << 3)
+#define AM335X_IOMUX_MODE0  0
+#define AM335X_IOMUX_MODE1  1
+#define AM335X_IOMUX_MODE2  2
+#define AM335X_IOMUX_MODE3  3
+#define AM335X_IOMUX_MODE4  4
+#define AM335X_IOMUX_MODE5  5
+#define AM335X_IOMUX_MODE6  6
+#define AM335X_IOMUX_MODE7  7
+
+/* AM335X CONTROL_MODULE configurable I/O pin. Table 9-10 at p. 886 */
+#define AM335X_IOMUX_CONF_BASE_ADDRESS 0x44E10800
+
+typedef struct {
+	ioport32_t gpmc_ad1;
+	ioport32_t gpmc_ad2;
+	ioport32_t gpmc_ad3;
+	ioport32_t gpmc_ad4;
+	ioport32_t gpmc_ad5;
+	ioport32_t gpmc_ad6;
+	ioport32_t gpmc_ad7;
+	ioport32_t gpmc_ad8;
+	ioport32_t gpmc_ad9;
+	ioport32_t gpmc_ad10;
+	ioport32_t gpmc_ad11;
+	ioport32_t gpmc_ad12;
+	ioport32_t gpmc_ad13;
+	ioport32_t gpmc_ad14;
+	ioport32_t gpmc_ad15;
+	ioport32_t gpmc_a0;
+	ioport32_t gpmc_a1;
+	ioport32_t gpmc_a2;
+	ioport32_t gpmc_a3;
+	ioport32_t gpmc_a4;
+	ioport32_t gpmc_a5;
+	ioport32_t gpmc_a6;
+	ioport32_t gpmc_a7;
+	ioport32_t gpmc_a8;
+	ioport32_t gpmc_a9;
+	ioport32_t gpmc_a10;
+	ioport32_t gpmc_a11;
+	ioport32_t gpmc_wait0;
+	ioport32_t gpmc_wpn;
+	ioport32_t gpmc_be1n;
+	ioport32_t gpmc_csn0;
+	ioport32_t gpmc_csn1;
+	ioport32_t gpmc_csn2;
+	ioport32_t gpmc_csn3;
+	ioport32_t gpmc_clk;
+	ioport32_t gpmc_advn_ale;
+	ioport32_t gpmc_oen_ren;
+	ioport32_t gpmc_wen;
+	ioport32_t gpmc_be0n_cle;
+	ioport32_t lcd_data0;
+	ioport32_t lcd_data1;
+	ioport32_t lcd_data2;
+	ioport32_t lcd_data3;
+	ioport32_t lcd_data4;
+	ioport32_t lcd_data5;
+	ioport32_t lcd_data6;
+	ioport32_t lcd_data7;
+	ioport32_t lcd_data8;
+	ioport32_t lcd_data9;
+	ioport32_t lcd_data10;
+	ioport32_t lcd_data11;
+	ioport32_t lcd_data12;
+	ioport32_t lcd_data13;
+	ioport32_t lcd_data14;
+	ioport32_t lcd_data15;
+	ioport32_t lcd_vsync;
+	ioport32_t lcd_hsync;
+	ioport32_t lcd_pclk;
+	ioport32_t lcd_ac_bias_en;
+	ioport32_t mmc0_dat3;
+	ioport32_t mmc0_dat2;
+	ioport32_t mmc0_dat1;
+	ioport32_t mmc0_dat0;
+	ioport32_t mmc0_clk;
+	ioport32_t mmc0_cmd;
+	ioport32_t mii1_col;
+	ioport32_t mii1_crs;
+	ioport32_t mii1_rxerr;
+	ioport32_t mii1_txen;
+	ioport32_t mii1_rxdv;
+	ioport32_t mii1_txd3;
+	ioport32_t mii1_txd2;
+	ioport32_t mii1_txd1;
+	ioport32_t mii1_txd0;
+	ioport32_t mii1_txclk;
+	ioport32_t mii1_rxclk;
+	ioport32_t mii1_rxd3;
+	ioport32_t mii1_rxd2;
+	ioport32_t mii1_rxd1;
+	ioport32_t mii1_rxd0;
+	ioport32_t rmii1_refclk;
+	ioport32_t mdio_data;
+	ioport32_t mdio_clk;
+	ioport32_t spi0_sclk;
+	ioport32_t spi0_d0;
+	ioport32_t spi0_d1;
+	ioport32_t spi0_cs0;
+	ioport32_t spi0_cs1;
+	ioport32_t ecap0_in_pwm0_out;
+	ioport32_t uart0_ctsn;
+	ioport32_t uart0_rtsn;
+	ioport32_t uart0_rxd;
+	ioport32_t uart0_txd;
+	ioport32_t uart1_ctsn;
+	ioport32_t uart1_rtsn;
+	ioport32_t uart1_rxd;
+	ioport32_t uart1_txd;
+	ioport32_t i2c0_sda;
+	ioport32_t i2c0_scl;
+	ioport32_t mcasp0_aclkx;
+	ioport32_t mcasp0_fsx;
+	ioport32_t mcasp0_axr0;
+	ioport32_t mcasp0_ahclkr;
+	ioport32_t mcasp0_aclkr;
+	ioport32_t mcasp0_fsr;
+	ioport32_t mcasp0_axr1;
+	ioport32_t mcasp0_ahclkx;
+	ioport32_t xdma_event_intr0;
+	ioport32_t xdma_event_intr1;
+	ioport32_t nresetin_out;
+	ioport32_t porz;
+	ioport32_t nnmi;
+	ioport32_t osc0_in;
+	ioport32_t osc0_out;
+	ioport32_t osc0_vss;
+	ioport32_t tms;
+	ioport32_t tdi;
+	ioport32_t tdo;
+	ioport32_t tck;
+	ioport32_t ntrst;
+	ioport32_t emu0;
+	ioport32_t emu1;
+	ioport32_t osc1_in;
+	ioport32_t osc1_out;
+	ioport32_t osc1_vss;
+	ioport32_t rtc_porz;
+	ioport32_t pmic_power_en;
+	ioport32_t ext_wakeup;
+	ioport32_t enz_kaldo_1p8v;
+	ioport32_t usb0_dm;
+	ioport32_t usb0_dp;
+	ioport32_t usb0_ce;
+	ioport32_t usb0_id;
+	ioport32_t usb0_vbus;
+	ioport32_t usb0_drvvbus;
+	ioport32_t usb1_dm;
+	ioport32_t usb1_dp;
+	ioport32_t usb1_ce;
+	ioport32_t usb1_id;
+	ioport32_t usb1_vbus;
+	ioport32_t usb1_drvvbus;
+	ioport32_t ddr_resetn;
+	ioport32_t ddr_csn0;
+	ioport32_t ddr_cke;
+	ioport32_t ddr_ck;
+	ioport32_t ddr_nck;
+	ioport32_t ddr_casn;
+	ioport32_t ddr_rasn;
+	ioport32_t ddr_wen;
+	ioport32_t ddr_ba0;
+	ioport32_t ddr_ba1;
+	ioport32_t ddr_ba2;
+	ioport32_t ddr_a0;
+	ioport32_t ddr_a1;
+	ioport32_t ddr_a2;
+	ioport32_t ddr_a3;
+	ioport32_t ddr_a4;
+	ioport32_t ddr_a5;
+	ioport32_t ddr_a6;
+	ioport32_t ddr_a7;
+	ioport32_t ddr_a8;
+	ioport32_t ddr_a9;
+	ioport32_t ddr_a10;
+	ioport32_t ddr_a11;
+	ioport32_t ddr_a12;
+	ioport32_t ddr_a13;
+	ioport32_t ddr_a14;
+	ioport32_t ddr_a15;
+	ioport32_t ddr_odt;
+	ioport32_t ddr_d0;
+	ioport32_t ddr_d1;
+	ioport32_t ddr_d2;
+	ioport32_t ddr_d3;
+	ioport32_t ddr_d4;
+	ioport32_t ddr_d5;
+	ioport32_t ddr_d6;
+	ioport32_t ddr_d7;
+	ioport32_t ddr_d8;
+	ioport32_t ddr_d9;
+	ioport32_t ddr_d10;
+	ioport32_t ddr_d11;
+	ioport32_t ddr_d12;
+	ioport32_t ddr_d13;
+	ioport32_t ddr_d14;
+	ioport32_t ddr_d15;
+	ioport32_t ddr_dqm0;
+	ioport32_t ddr_dqm1;
+	ioport32_t ddr_dqs0;
+	ioport32_t ddr_dqsn0;
+	ioport32_t ddr_dqs1;
+	ioport32_t ddr_dqsn1;
+	ioport32_t ddr_vref;
+	ioport32_t ddr_vtp;
+	ioport32_t ain7;
+	ioport32_t ain6;
+	ioport32_t ain5;
+	ioport32_t ain4;
+	ioport32_t ain3;
+	ioport32_t ain2;
+	ioport32_t ain1;
+	ioport32_t ain0;
+	ioport32_t vrefp;
+	ioport32_t vrefn;
+	ioport32_t avdd;
+	ioport32_t avss;
+	ioport32_t iforce;
+	ioport32_t vsense;
+	ioport32_t testout;
+} am335x_iomux_conf_regs_t;
+#endif /* KERN_AM335X_IOMUX_H_ */
Index: kernel/genarch/include/drivers/am335x/irc.h
===================================================================
--- kernel/genarch/include/drivers/am335x/irc.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/include/drivers/am335x/irc.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2012 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+
+/**
+ * @file
+ * @brief Texas Instruments AM335x MPU on-chip interrupt controller driver.
+ */
+
+#ifndef KERN_AM335x_IRQC_H_
+#define KERN_AM335x_IRQC_H_
+
+#define AM335x_IRC_BASE_ADDRESS 0x48200000
+#define AM335x_IRC_SIZE         4096
+
+#define AM335x_IRC_IRQ_COUNT    128
+
+#include <typedefs.h>
+
+typedef struct {
+	const ioport32_t revision;
+#define AM335x_IRC_REV_MASK 0xFF
+
+	const uint8_t padd0[12];
+
+	/* This register controls the various parameters
+	 * of the OCP interface.
+	 */
+	ioport32_t sysconfig;
+#define AM335x_IRC_SYSCONFIG_AUTOIDLE_FLAG   (1 << 0)
+#define AM335x_IRC_SYSCONFIG_SOFTRESET_FLAG  (1 << 1)
+
+	/* This register provides status information about the module */
+	const ioport32_t sysstatus;
+#define AM335x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0)
+
+	const uint8_t padd1[40];
+
+	/* This register supplies the currently active IRQ interrupt number */
+	ioport32_t sir_irq;
+#define AM335x_IRC_SIR_IRQ_ACTIVEIRQ_MASK       0x7F
+#define AM335x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8
+
+	/* This register supplies the currently active FIQ interrupt number */
+	const ioport32_t sir_fiq;
+#define AM335x_IRC_FIQ_IRQ_ACTIVEFIQ_MASK       0x7F
+#define AM335x_IRC_FIQ_IRQ_SPURIOUSFIQFLAG_MASK 0xFFFFFFF8
+
+	/* This register contains the new interrupt agreement bits */
+	ioport32_t control;
+#define AM335x_IRC_CONTROL_NEWIRQAGR_FLAG       (1 << 0)
+#define AM335x_IRC_CONTROL_NEWFIQAGR_FLAG       (1 << 1)
+
+	/* This register controls protection of the other registers.
+	 * This register can only be accessed in priviledged mode, regardless
+	 * of the current value of the protection bit.
+	 */
+	ioport32_t protection;
+#define AM335x_IRC_PROTECTION_FLAG              (1 << 0)
+
+	/* This register controls the clock auto-idle for the functional
+	 * clock and the input synchronizers.
+	 */
+	ioport32_t idle;
+#define AM335x_IRC_IDLE_FUNCIDLE_FLAG           (1 << 0)
+#define AM335x_IRC_IDLE_TURBO_FLAG              (1 << 1)
+
+	const uint8_t padd2[12];
+
+	/* This register supplies the currently active IRQ priority level */
+	const ioport32_t irq_priority;
+#define AM335x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK     0x7F
+#define AM335x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8
+
+	/* This register supplies the currently active FIQ priority level */
+	const ioport32_t fiq_priority;
+#define AM335x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK     0x7F
+#define AM335x_IRC_FIQ_PRIORITY_SPURIOUSIRQFLAG_MASK 0xFFFFFFF8
+
+	/* This register sets the priority threshold */
+	ioport32_t threshold;
+#define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK     0xFF
+#define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED  0x00
+#define AM335x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED 0xFF
+
+	const uint8_t padd[20];
+
+	struct {
+		/* Raw interrupt input status before masking */
+		const ioport32_t itr;
+
+		/* Interrupt mask */
+		ioport32_t mir;
+
+		/* This register is used to clear the interrupt mask bits,
+		 * Write 1 clears the mask bit to 0.
+		 */
+		ioport32_t mir_clear;
+
+		/* This register is used to set the interrupt mask bits,
+		 * Write 1 sets the mask bit to 1.
+		 */
+		ioport32_t mir_set;
+
+		/* This register is used to set the software interrupt bits,
+		 * it is also used to read the current active software
+		 * interrupts.
+		 * Write 1 sets the software interrups bits to 1.
+		 */
+		ioport32_t isr_set;
+
+		/* This register is used to clear the software interrups bits.
+		 * Write 1 clears the software interrupt bits to 0.
+		 */
+		ioport32_t isr_clear;
+
+		/* This register contains the IRQ status after masking. */
+		const ioport32_t pending_irq;
+
+		/* This register contains the FIQ status after masking. */
+		const ioport32_t pending_fiq;
+	} interrupts[4];
+
+	/* These registers contain the priority for the interrups and
+	 * the FIQ/IRQ steering.
+	 */
+	ioport32_t ilr[AM335x_IRC_IRQ_COUNT];
+/* 0 = Interrupt routed to IRQ, 1 = interrupt routed to FIQ */
+#define AM335x_IRC_ILR_FIQNIRQ_FLAG    (1 << 0)
+#define AM335x_IRC_ILR_PRIORITY_MASK   0x3F
+#define AM335x_IRC_ILR_PRIORITY_SHIFT  2
+
+} am335x_irc_regs_t;
+
+static inline void am335x_irc_init(am335x_irc_regs_t *regs)
+{
+	int i;
+
+	/* Initialization sequence */
+
+	/* 1 - Program the SYSCONFIG register: if necessary, enable the
+	 *     autogating by setting the AUTOIDLE bit.
+	 */
+	regs->sysconfig &= ~AM335x_IRC_SYSCONFIG_AUTOIDLE_FLAG;
+
+	/* 2 - Program the IDLE register: if necessary, disable functional
+	 *     clock autogating or enable synchronizer autogating by setting
+	 *     the FUNCIDLE bit or the TURBO bit accordingly.
+	 */
+	regs->idle &= ~AM335x_IRC_IDLE_FUNCIDLE_FLAG;
+	regs->idle &= ~AM335x_IRC_IDLE_TURBO_FLAG;
+
+	/* 3 - Program ILRm register for each interrupt line: Assign a
+	 *     priority level and set the FIQNIRQ bit for an FIQ interrupt
+	 *     (by default, interrupts are mapped to IRQ and
+	 *     priority is 0 (highest).
+	 */
+
+	for (i = 0; i < AM335x_IRC_IRQ_COUNT; ++i)
+		regs->ilr[i] = 0;
+
+	/* 4 - Program the MIRn register: Enable interrupts (by default,
+	 *     all interrupt lines are masked).
+	 */
+	for (i = 0; i < 4; ++i)
+		regs->interrupts[i].mir_set = 0xFFFFFFFF;
+}
+
+/** Get the currently active IRQ interrupt number
+ *
+ * @param regs     Pointer to the irc memory mapped registers
+ *
+ * @return         The active IRQ interrupt number
+ */
+static inline unsigned am335x_irc_inum_get(am335x_irc_regs_t *regs)
+{
+	return regs->sir_irq & AM335x_IRC_SIR_IRQ_ACTIVEIRQ_MASK;
+}
+
+/** Reset IRQ output and enable new IRQ generation
+ *
+ * @param regs    Pointer to the irc memory mapped registers
+ */
+static inline void am335x_irc_irq_ack(am335x_irc_regs_t *regs)
+{
+	regs->control = AM335x_IRC_CONTROL_NEWIRQAGR_FLAG;
+}
+
+/** Reset FIQ output and enable new FIQ generation
+ *
+ * @param regs    Pointer to the irc memory mapped registers
+ */
+static inline void am335x_irc_fiq_ack(am335x_irc_regs_t *regs)
+{
+	regs->control = AM335x_IRC_CONTROL_NEWFIQAGR_FLAG;
+}
+
+/** Clear an interrupt mask bit
+ *
+ * @param regs    Pointer to the irc memory mapped registers
+ * @param inum    The interrupt to be enabled
+ */
+static inline void am335x_irc_enable(am335x_irc_regs_t *regs, unsigned inum)
+{
+	ASSERT(inum < AM335x_IRC_IRQ_COUNT);
+	const unsigned set = inum / 32;
+	const unsigned pos = inum % 32;
+	regs->interrupts[set].mir_clear = (1 << pos);
+}
+
+/** Set an interrupt mask bit
+ *
+ * @param regs    Pointer to the irc memory mapped registers
+ * @param inum    The interrupt to be disabled
+ */
+static inline void am335x_irc_disable(am335x_irc_regs_t *regs, unsigned inum)
+{
+	ASSERT(inum < AM335x_IRC_IRQ_COUNT);
+	const unsigned set = inum / 32;
+	const unsigned pos = inum % 32;
+	regs->interrupts[set].mir_set = (1 << pos);
+}
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/am335x/timer.h
===================================================================
--- kernel/genarch/include/drivers/am335x/timer.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/include/drivers/am335x/timer.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2012 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x timer driver.
+ */
+
+#ifndef _KERN_AM335X_TIMER_H_
+#define _KERN_AM335X_TIMER_H_
+
+#include "timer_regs.h"
+
+#define AM335x_DMTIMER0_BASE_ADDRESS    0x44E05000
+#define AM335x_DMTIMER0_SIZE            4096
+#define AM335x_DMTIMER0_IRQ             66
+
+#define AM335x_DMTIMER2_BASE_ADDRESS    0x48040000
+#define AM335x_DMTIMER2_SIZE            4096
+#define AM335x_DMTIMER2_IRQ             68
+
+#define AM335x_DMTIMER3_BASE_ADDRESS    0x48042000
+#define AM335x_DMTIMER3_SIZE            4096
+#define AM335x_DMTIMER3_IRQ             69
+
+#define AM335x_DMTIMER4_BASE_ADDRESS    0x48044000
+#define AM335x_DMTIMER4_SIZE            4096
+#define AM335x_DMTIMER4_IRQ             92
+
+#define AM335x_DMTIMER5_BASE_ADDRESS    0x48046000
+#define AM335x_DMTIMER5_SIZE            4096
+#define AM335x_DMTIMER5_IRQ             93
+
+#define AM335x_DMTIMER6_BASE_ADDRESS    0x48048000
+#define AM335x_DMTIMER6_SIZE            4096
+#define AM335x_DMTIMER6_IRQ             94
+
+#define AM335x_DMTIMER7_BASE_ADDRESS    0x4804A000
+#define AM335x_DMTIMER7_SIZE            4096
+#define AM335x_DMTIMER7_IRQ             95
+
+typedef enum {
+	DMTIMER0 = 0,
+	DMTIMER1_1MS,
+	DMTIMER2,
+	DMTIMER3,
+	DMTIMER4,
+	DMTIMER5,
+	DMTIMER6,
+	DMTIMER7,
+
+	TIMERS_MAX
+} am335x_timer_id_t;
+
+typedef struct am335x_timer {
+	am335x_timer_regs_t *regs;
+	am335x_timer_id_t id;
+} am335x_timer_t;
+
+extern void am335x_timer_init(am335x_timer_t *timer, am335x_timer_id_t id,
+    unsigned hz);
+extern void am335x_timer_intr_ack(am335x_timer_t *timer);
+extern void am335x_timer_reset(am335x_timer_t *timer);
+extern void am335x_timer_start(am335x_timer_t *timer);
+extern void am335x_timer_stop(am335x_timer_t *timer);
+
+
+#endif
+
+/**
+ * @}
+ */
+
Index: kernel/genarch/include/drivers/am335x/timer_regs.h
===================================================================
--- kernel/genarch/include/drivers/am335x/timer_regs.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/include/drivers/am335x/timer_regs.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2012 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x DMTIMER memory mapped registers.
+ */
+
+#ifndef _KERN_AM335X_TIMER_REGS_H_
+#define _KERN_AM335X_TIMER_REGS_H_
+
+#include <typedefs.h>
+
+typedef struct am335x_timer_regs {
+
+	/* This read only register contains the
+	 * revision number of the module
+	 */
+	ioport32_t const tidr;
+#define AM335x_TIMER_TIDR_MINOR_MASK     0x3F
+#define AM335x_TIMER_TIDR_MINOR_SHIFT    0
+#define AM335x_TIMER_TIDR_CUSTOM_MASK    0x03
+#define AM335x_TIMER_TIDR_CUSTOM_SHIFT   6
+#define AM335x_TIMER_TIDR_MAJOR_MASK     0x07
+#define AM335x_TIMER_TIDR_MAJOR_SHIFT    8
+#define AM335x_TIMER_TIDR_RTL_MASK       0x1F
+#define AM335x_TIMER_TIDR_RTL_SHIFT      11
+#define AM335x_TIMER_TIDR_FUNC_MASK      0xFFF
+#define AM335x_TIMER_TIDR_FUNC_SHIFT     16
+#define AM335x_TIMER_TIDR_SCHEME_MASK    0x03
+#define AM335x_TIMER_TIDR_SCHEME_SHIFT   30
+
+	ioport32_t const pad1[3];
+
+	/* This register allows controlling various
+	 * parameters of the OCP interface.
+	 */
+	ioport32_t tiocp_cfg;
+#define AM335x_TIMER_TIOCPCFG_SOFTRESET_FLAG    (1 << 0)
+#define AM335x_TIMER_TIOCPCFG_EMUFREE_FLAG      (1 << 1)
+
+#define AM335x_TIMER_TIOCPCFG_IDLEMODE_MASK            0x02
+#define AM335x_TIMER_TIOCPCFG_IDLEMODE_SHIFT           2
+#  define AM335x_TIMER_TIOCCPCFG_IDLEMODE_FORCE        0x00
+#  define AM335x_TIMER_TIOCCPCFG_IDLEMODE_DISABLED     0x01
+#  define AM335x_TIMER_TIOCCPCFG_IDLEMODE_SMART        0x02
+#  define AM335x_TIMER_TIOCCPCFG_IDLEMODE_SMART_WAKEUP 0x03
+
+	ioport32_t const pad2[4];
+
+	ioport32_t irqstatus_raw;
+#define AM335x_TIMER_IRQSTATUS_RAW_MAT_FLAG     (1 << 0)
+#define AM335x_TIMER_IRQSTATUS_RAW_OVF_FLAG     (1 << 1)
+#define AM335x_TIMER_IRQSTATUS_RAW_TCAR_FLAG    (1 << 2)
+
+	ioport32_t irqstatus;
+#define AM335x_TIMER_IRQSTATUS_MAT_FLAG     (1 << 0)
+#define AM335x_TIMER_IRQSTATUS_OVF_FLAG     (1 << 1)
+#define AM335x_TIMER_IRQSTATUS_TCAR_FLAG    (1 << 2)
+
+	ioport32_t irqenable_set;
+#define AM335x_TIMER_IRQENABLE_SET_MAT_FLAG (1 << 0)
+#define AM335x_TIMER_IRQENABLE_SET_OVF_FLAG (1 << 1)
+#define AM335x_TIMER_IRQENABLE_SET_TCAR_FLAG (1 << 2)
+
+	ioport32_t irqenable_clr;
+#define AM335x_TIMER_IRQENABLE_CLR_MAT_FLAG (1 << 0)
+#define AM335x_TIMER_IRQENABLE_CLR_OVF_FLAG (1 << 1)
+#define AM335x_TIMER_IRQENABLE_CLR_TCAR_FLAG (1 << 2)
+
+	/* Timer IRQ wakeup enable register */
+	ioport32_t irqwakeen;
+#define AM335x_TIMER_IRQWAKEEN_MAT_FLAG     (1 << 0)
+#define AM335x_TIMER_IRQWAKEEN_PVF_FLAG     (1 << 1)
+#define AM335x_TIMER_IRQWAKEEN_TCAR_FLAG    (1 << 2)
+
+	/* Timer control register */
+	ioport32_t tclr;
+#define AM335x_TIMER_TCLR_ST_FLAG           (1 << 0)
+#define AM335x_TIMER_TCLR_AR_FLAG           (1 << 1)
+#define AM335x_TIMER_TCLR_PTV_MASK          0x07
+#define AM335x_TIMER_TCLR_PTV_SHIFT         2
+#define AM335x_TIMER_TCLR_PRE_FLAG          (1 << 5)
+#define AM335x_TIMER_TCLR_CE_FLAG           (1 << 6)
+#define AM335x_TIMER_TCLR_SCPWM_FLAG        (1 << 7)
+#define AM335x_TIMER_TCLR_TCM_MASK          0x03
+#define AM335x_TIMER_TCLR_TCM_SHIFT         8
+#define AM335x_TIMER_TCLR_TGR_MASK          0x03
+#define AM335x_TIMER_TCLR_TGR_SHIFT         10
+#define AM335x_TIMER_TCLR_PT_FLAG           (1 << 12)
+#define AM335x_TIMER_TCLR_CAPT_MODE_FLAG    (1 << 13)
+#define AM335x_TIMER_TCLR_GPO_CFG_FLAG      (1 << 14)
+
+	/* Timer counter register */
+	ioport32_t tcrr;
+
+	/* Timer load register */
+	ioport32_t tldr;
+
+	/* Timer trigger register */
+	ioport32_t const ttgr;
+
+	/* Timer write posted status register */
+	ioport32_t twps;
+#define AM335x_TIMER_TWPS_PEND_TCLR         (1 << 0)
+#define AM335x_TIMER_TWPS_PEND_TCRR         (1 << 1)
+#define AM335x_TIMER_TWPS_PEND_TLDR         (1 << 2)
+#define AM335x_TIMER_TWPS_PEND_TTGR         (1 << 3)
+#define AM335x_TIMER_TWPS_PEND_TMAR         (1 << 4)
+
+	/* Timer match register */
+	ioport32_t tmar;
+
+	/* Timer capture register */
+	ioport32_t tcar1;
+
+	/* Timer synchronous interface control register */
+	ioport32_t tsicr;
+#define AM335x_TIMER_TSICR_SFT_FLAG         (1 << 1)
+#define AM335x_TIMER_TSICR_POSTED_FLAG      (1 << 2)
+
+	/* Timer capture register */
+	ioport32_t tcar2;
+
+} am335x_timer_regs_t;
+
+#endif
+
+/**
+ * @}
+ */
+
Index: kernel/genarch/include/drivers/am335x/uart.h
===================================================================
--- kernel/genarch/include/drivers/am335x/uart.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/include/drivers/am335x/uart.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x UART driver.
+ */
+
+#ifndef _KERN_AM335X_UART_H_
+#define _KERN_AM335X_UART_H_
+
+#include "uart_regs.h"
+
+#define AM335x_UART0_BASE_ADDRESS    0x44E09000
+#define AM335x_UART0_SIZE            4096
+#define AM335x_UART0_IRQ             72
+
+#define AM335x_UART1_BASE_ADDRESS    0x48022000
+#define AM335x_UART1_SIZE            4096
+#define AM335x_UART1_IRQ             73
+
+#define AM335x_UART2_BASE_ADDRESS    0x48024000
+#define AM335x_UART2_SIZE            4096
+#define AM335x_UART2_IRQ             74
+
+#define AM335x_UART3_BASE_ADDRESS    0x481A6000
+#define AM335x_UART3_SIZE            4096
+#define AM335x_UART3_IRQ             44
+
+#define AM335x_UART4_BASE_ADDRESS    0x481A8000
+#define AM335x_UART4_SIZE            4096
+#define AM335x_UART4_IRQ             45
+
+#define AM335x_UART5_BASE_ADDRESS    0x481AA000
+#define AM335x_UART5_SIZE            4096
+#define AM335x_UART5_IRQ             46
+
+typedef struct {
+	am335x_uart_regs_t *regs;
+	indev_t *indev;
+	outdev_t outdev;
+	irq_t irq;
+} am335x_uart_t;
+
+
+bool am335x_uart_init(am335x_uart_t *, inr_t, uintptr_t, size_t);
+void am335x_uart_input_wire(am335x_uart_t *, indev_t *);
+
+#endif
+
+/**
+ * @}
+ */
+
Index: kernel/genarch/include/drivers/am335x/uart_regs.h
===================================================================
--- kernel/genarch/include/drivers/am335x/uart_regs.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/include/drivers/am335x/uart_regs.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,431 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * Copyright (c) 2012 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x UART memory mapped registers.
+ */
+
+#ifndef _KERN_AM335X_UART_REGS_H_
+#define _KERN_AM335X_UART_REGS_H_
+
+#include <typedefs.h>
+#include <console/chardev.h>
+#include <ddi/irq.h>
+
+typedef struct {
+	union {
+		/** Stores lower part of the 14-bit baud divisor */
+		ioport32_t dll;
+#define AM335x_UART_DLL_MASK   (0xff)
+
+		/** Receive holding register */
+		const ioport32_t rhr;
+#define AM335x_UART_RHR_MASK   (0xff)
+
+		/** Transmit holding register */
+		ioport32_t thr;
+#define AM335x_UART_THR_MASK   (0xff)
+	};
+
+	union {
+		/** Stores higher part of the 14-bit baud divisor */
+		ioport32_t dlh;
+#define AM335x_UART_DLH_MASK   (0x1f)
+
+		/** Interrupt enable registers */
+		ioport32_t ier;
+#define AM335x_UART_IER_RHR_IRQ_FLAG   (1 << 0)
+#define AM335x_UART_IER_THR_IRQ_FLAG   (1 << 1)
+#define AM335x_UART_IER_LINE_STS_IRQ_FLAG   (1 << 2)
+#define AM335x_UART_IER_MODEM_STS_IRQ_FLAG   (1 << 3)
+#define AM335x_UART_IER_SLEEP_MODE_FLAG   (1 << 4)
+#define AM335x_UART_IER_XOFF_IRQ_FLAG   (1 << 5)
+#define AM335x_UART_IER_RTS_IRQ_FLAG   (1 << 6)
+#define AM335x_UART_IER_CTS_IRQ_FLAG   (1 << 7)
+
+#define AM335x_CIR_IER_RHR_IRQ_FLAG   (1 << 0)
+#define AM335x_CIR_IER_THR_IRQ_FLAG   (1 << 1)
+#define AM335x_CIR_IER_RX_STOP_IRQ_FLAG   (1 << 2)
+#define AM335x_CIR_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
+#define AM335x_CIR_IER_TX_STS_IRQ_FLAG   (1 << 5)
+
+#define AM335x_IRDA_IER_RHR_IRQ_FLAG   (1 << 0)
+#define AM335x_IRDA_IER_THR_IRQ_FLAG   (1 << 1)
+#define AM335x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG   (1 << 2)
+#define AM335x_IRDA_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
+#define AM335x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG   (1 << 4)
+#define AM335x_IRDA_IER_TX_STS_IRQ_FLAG   (1 << 5)
+#define AM335x_IRDA_IER_LINE_STS_IRQ_FLAG   (1 << 6)
+#define AM335x_IRDA_IER_EOF_IRQ_FLAG   (1 << 7)
+	};
+
+	union {
+		/** Interrupt identification register */
+		const ioport32_t iir;
+#define AM335x_UART_IIR_IRQ_PENDING_FLAG   (1 << 0)
+#define AM335x_UART_IIR_TYPE_MASK   (0x1f)
+#define AM335x_UART_IIR_TYPE_SHIFT   (1)
+#define AM335x_UART_IIR_FCR_MASK   (0x3)
+#define AM335x_UART_IIR_FCR_SHIFT   (6)
+
+#define AM335x_CIR_IIR_RHR_IRQ_FLAG   (1 << 0)
+#define AM335x_CIR_IIR_THR_IRQ_FLAG   (1 << 1)
+#define AM335x_CIR_IIR_RX_STOP_IRQ_FLAG   (1 << 2)
+#define AM335x_CIR_IIR_RX_OE_IRQ_FLAG   (1 << 3)
+#define AM335x_CIR_IIR_TX_STS_IRQ_FLAG   (1 << 5)
+
+#define AM335x_IRDA_IIR_RHR_IRQ_FLAG   (1 << 0)
+#define AM335x_IRDA_IIR_THR_IRQ_FLAG   (1 << 1)
+#define AM335x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG   (1 << 2)
+#define AM335x_IRDA_IIR_RX_OE_IRQ_FLAG   (1 << 3)
+#define AM335x_IRDA_IIR_STS_FIFO_IRQ_FLAG   (1 << 4)
+#define AM335x_IRDA_IIR_TX_STS_IRQ_FLAG   (1 << 5)
+#define AM335x_IRDA_IIR_LINE_STS_IRQ_FLAG   (1 << 6)
+#define AM335x_IRDA_IIR_EOF_IRQ_FLAG   (1 << 7)
+
+		/** FIFO control register */
+		ioport32_t fcr;
+#define AM335x_UART_FCR_FIFO_EN_FLAG   (1 << 0)
+#define AM335x_UART_FCR_RX_FIFO_CLR_FLAG   (1 << 1)
+#define AM335x_UART_FCR_TX_FIFO_CLR_FLAG   (1 << 3)
+#define AM335x_UART_FCR_DMA_MODE_FLAG   (1 << 4)
+
+#define AM335x_UART_FCR_TX_FIFO_TRIG_MASK   (0x3)
+#define AM335x_UART_FCR_TX_FIFO_TRIG_SHIFT   (4)
+
+#define AM335x_UART_FCR_RX_FIFO_TRIG_MASK   (0x3)
+#define AM335x_UART_FCR_RX_FIFO_TRIG_SHIFT   (6)
+
+		/** Enhanced feature register */
+		ioport32_t efr;
+#define AM335x_UART_EFR_SW_FLOW_CTRL_RX_MASK   (0x3)
+#define AM335x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT   (0)
+#define AM335x_UART_EFR_SW_FLOW_CTRL_TX_MASK   (0x3)
+#define AM335x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT   (2)
+
+#define AM335x_UART_EFR_SW_FLOW_CTRL_NONE   (0x0)
+#define AM335x_UART_EFR_SW_FLOW_CTRL_X2   (0x1)
+#define AM335x_UART_EFR_SW_FLOW_CTRL_X1   (0x2)
+#define AM335x_UART_EFR_SW_FLOW_CTRL_XBOTH   (0x3)
+
+#define AM335x_UART_EFR_ENH_FLAG   (1 << 4)
+#define AM335x_UART_EFR_SPEC_CHAR_FLAG   (1 << 5)
+#define AM335x_UART_EFR_AUTO_RTS_EN_FLAG   (1 << 6)
+#define AM335x_UART_EFR_AUTO_CTS_EN_FLAG   (1 << 7)
+	};
+
+	/** Line control register */
+	ioport32_t lcr;
+#define AM335x_UART_LCR_CHAR_LENGTH_MASK   (0x3)
+#define AM335x_UART_LCR_CHAR_LENGTH_SHIFT   (0)
+#define AM335x_UART_LCR_CHAR_LENGTH_5BITS   (0x0)
+#define AM335x_UART_LCR_CHAR_LENGTH_6BITS   (0x1)
+#define AM335x_UART_LCR_CHAR_LENGTH_7BITS   (0x2)
+#define AM335x_UART_LCR_CHAR_LENGTH_8BITS   (0x3)
+#define AM335x_UART_LCR_NB_STOP_FLAG   (1 << 2)
+#define AM335x_UART_LCR_PARITY_EN_FLAG   (1 << 3)
+#define AM335x_UART_LCR_PARITY_TYPE1_FLAG   (1 << 4)
+#define AM335x_UART_LCR_PARITY_TYPE2_FLAG   (1 << 5)
+#define AM335x_UART_LCR_BREAK_EN_FLAG   (1 << 6)
+#define AM335x_UART_LCR_DIV_EN_FLAG   (1 << 7)
+
+
+	union {
+		/** Modem control register */
+		ioport32_t mcr;
+#define AM335x_UART_MCR_DTR_FLAG   (1 << 0)
+#define AM335x_UART_MCR_RTS_FLAG   (1 << 1)
+#define AM335x_UART_MCR_RI_STS_CH_FLAG   (1 << 2)
+#define AM335x_UART_MCR_CD_STS_CH_FLAG   (1 << 3)
+#define AM335x_UART_MCR_LOOPBACK_EN_FLAG   (1 << 4)
+#define AM335x_UART_MCR_XON_EN_FLAG   (1 << 5)
+#define AM335x_UART_MCR_TCR_TLR_FLAG   (1 << 6)
+
+		/** UART: XON1 char, IRDA: ADDR1 address */
+		ioport32_t xon1_addr1;
+#define AM335x_UART_XON1_ADDR1_MASK   (0xff)
+	};
+
+	union {
+		/** Line status register */
+		const ioport32_t lsr;
+#define AM335x_UART_LSR_RX_FIFO_E_FLAG   (1 << 0)
+#define AM335x_UART_LSR_RX_OE_FLAG   (1 << 1)
+#define AM335x_UART_LSR_RX_PE_FLAG   (1 << 2)
+#define AM335x_UART_LSR_RX_FE_FLAG   (1 << 3)
+#define AM335x_UART_LSR_RX_BI_FLAG   (1 << 4)
+#define AM335x_UART_LSR_TX_FIFO_E_FLAG   (1 << 5)
+#define AM335x_UART_LSR_TX_SR_E_FLAG   (1 << 6)
+#define AM335x_UART_LSR_RX_FIFO_STS_FLAG   (1 << 7)
+
+#define AM335x_CIR_LSR_RX_FIFO_E_FLAG   (1 << 0)
+#define AM335x_CIR_LSR_RX_STOP_FLAG   (1 << 5)
+#define AM335x_CIR_LSR_THR_EMPTY_FLAG   (1 << 7)
+
+#define AM335x_IRDA_LSR_RX_FIFO_E_FLAG   (1 << 0)
+#define AM335x_IRDA_LSR_STS_FIFO_E_FLAG   (1 << 1)
+#define AM335x_IRDA_LSR_CRC_FLAG   (1 << 2)
+#define AM335x_IRDA_LSR_ABORT_FLAG   (1 << 3)
+#define AM335x_IRDA_LSR_FTL_FLAG   (1 << 4)
+#define AM335x_IRDA_LSR_RX_LAST_FLAG   (1 << 5)
+#define AM335x_IRDA_LSR_STS_FIFO_FULL_FLAG   (1 << 6)
+#define AM335x_IRDA_LSR_THR_EMPTY_FLAG   (1 << 7)
+
+		/** UART: XON2 char, IRDA: ADDR2 address */
+		ioport32_t xon2_addr2;
+	};
+
+	union {
+		/** Modem status register */
+		const ioport32_t msr;
+#define AM335x_UART_MSR_CTS_STS_FLAG   (1 << 0)
+#define AM335x_UART_MSR_DSR_STS_FLAG   (1 << 1)
+#define AM335x_UART_MSR_RI_STS_FLAG   (1 << 2)
+#define AM335x_UART_MSR_DCD_STS_FLAG   (1 << 3)
+#define AM335x_UART_MSR_NCTS_STS_FLAG   (1 << 4)
+#define AM335x_UART_MSR_NDSR_STS_FLAG   (1 << 5)
+#define AM335x_UART_MSR_NRI_STS_FLAG   (1 << 6)
+#define AM335x_UART_MSR_NCD_STS_FLAG   (1 << 7)
+
+		/** Transmission control register */
+		ioport32_t tcr;
+#define AM335x_UART_TCR_FIFO_TRIG_MASK   (0xf)
+#define AM335x_UART_TCR_FIFO_TRIG_HALT_SHIFT   (0)
+#define AM335x_UART_TCR_FIFO_TRIG_START_SHIFT   (4)
+
+		/** UART: XOFF1 char */
+		ioport32_t xoff1;
+#define AM335x_UART_XOFF1_MASK   (0xff)
+	};
+
+	union {
+		/* Scratchpad register, does nothing */
+		ioport32_t spr;
+#define AM335x_UART_SPR_MASK   (0xff)
+
+		/* Trigger level register */
+		ioport32_t tlr;
+#define AM335x_UART_TLR_LEVEL_MASK   (0xf)
+#define AM335x_UART_TLR_TX_FIFO_TRIG_SHIFT   (0)
+#define AM335x_UART_TLR_RX_FIFO_TRIG_SHIFT   (4)
+
+		/** UART: XOFF2 char */
+		ioport32_t xoff2;
+#define AM335x_UART_XOFF2_MASK   (0xff)
+	};
+
+	/** Mode definition register. */
+	ioport32_t mdr1;
+#define AM335x_UART_MDR_MS_MASK   (0x7)
+#define AM335x_UART_MDR_MS_SHIFT   (0)
+#define AM335x_UART_MDR_MS_UART16   (0x0)
+#define AM335x_UART_MDR_MS_SIR   (0x1)
+#define AM335x_UART_MDR_MS_UART16_AUTO   (0x2)
+#define AM335x_UART_MDR_MS_UART13   (0x3)
+#define AM335x_UART_MDR_MS_MIR   (0x4)
+#define AM335x_UART_MDR_MS_FIR   (0x5)
+#define AM335x_UART_MDR_MS_CIR   (0x6)
+#define AM335x_UART_MDR_MS_DISABLE   (0x7)
+
+#define AM335x_UART_MDR_IR_SLEEP_FLAG   (1 << 3)
+#define AM335x_UART_MDR_SET_TXIR_FLAG   (1 << 4)
+#define AM335x_UART_MDR_SCT_FLAG   (1 << 5)
+#define AM335x_UART_MDR_SIP_FLAG   (1 << 6)
+#define AM335x_UART_MDR_FRAME_END_MODE_FLAG   (1 << 7)
+
+	/** Mode definition register */
+	ioport32_t mdr2;
+#define AM335x_UART_MDR_IRTX_UNDERRUN_FLAG   (1 << 0)
+#define AM335x_UART_MDR_STS_FIFO_TRIG_MASK   (0x3)
+#define AM335x_UART_MDR_STS_FIFO_TRIG_SHIFT   (1)
+#define AM335x_UART_MDR_PULSE_SHAPING_FLAG   (1 << 3)
+#define AM335x_UART_MDR_CIR_PULSE_MODE_MASK   (0x3)
+#define AM335x_UART_MDR_CIR_PULSE_MODE_SHIFT   (4)
+#define AM335x_UART_MDR_IRRXINVERT_FLAG   (1 << 6)
+
+	union {
+		/** Status FIFO line status register (IrDA only) */
+		const ioport32_t sflsr;
+#define AM335x_IRDA_SFLSR_CRC_ERROR_FLAG   (1 << 1)
+#define AM335x_IRDA_SFLSR_ABORT_FLAG   (1 << 2)
+#define AM335x_IRDA_SFLSR_FTL_FLAG   (1 << 3)
+#define AM335x_IRDA_SFLSR_OE_FLAG   (1 << 4)
+
+		/** Transmit frame length low (IrDA only) */
+		ioport32_t txfll;
+#define AM335x_UART_TXFLL_MASK   (0xff)
+	};
+
+	union {
+		/** Dummy register to restart TX or RX (IrDA only) */
+		const ioport32_t resume;
+		/** Transmit frame length high (IrDA only) */
+		ioport32_t txflh;
+#define AM335x_UART_TXFLH_MASK   (0xff)
+	};
+
+	union {
+		/** Status FIFO register low (IrDA only) */
+		const ioport32_t sfregl;
+#define AM335x_UART_SFREGL_MASK   (0xff)
+		/** Received frame length low (IrDA only) */
+		ioport32_t rxfll;
+#define AM335x_UART_RXFLL_MASK   (0xff)
+	};
+
+	union {
+		/** Status FIFO register high (IrDA only) */
+		const ioport32_t sfregh;
+#define AM335x_UART_SFREGH_MASK   (0xf)
+		/** Received frame length high (IrDA only) */
+		ioport32_t rxflh;
+#define AM335x_UART_RXFLH_MASK   (0xf)
+	};
+
+	union {
+		/** UART autobauding status register */
+		const ioport32_t uasr;
+#define AM335x_UART_UASR_SPEED_MASK   (0x1f)
+#define AM335x_UART_UASR_SPEED_SHIFT   (0)
+#define AM335x_UART_UASR_8BIT_CHAR_FLAG   (1 << 5)
+#define AM335x_UART_UASR_PARITY_MASK   (0x3)
+#define AM335x_UART_UASR_PARITY_SHIFT   (6)
+
+		/** BOF control register (IrDA only) */
+		ioport32_t blr;
+#define AM335x_IRDA_BLR_XBOF_TYPE_FLAG   (1 << 6)
+#define AM335x_IRDA_BLR_STS_FIFO_RESET   (1 << 7)
+	};
+
+	/** Auxiliary control register (IrDA only) */
+	ioport32_t acreg;
+#define AM335x_IRDA_ACREG_EOT_EN_FLAG   (1 << 0)
+#define AM335x_IRDA_ACREG_ABORT_EN_FLAG   (1 << 1)
+#define AM335x_IRDA_ACREG_SCTX_EN_FLAG   (1 << 2)
+#define AM335x_IRDA_ACREG_SEND_SIP_FLAG   (1 << 3)
+#define AM335x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG   (1 << 4)
+#define AM335x_IRDA_ACREG_DIS_IR_RX_FLAG   (1 << 5)
+#define AM335x_IRDA_ACREG_SD_MOD_FLAG   (1 << 6)
+#define AM335x_IRDA_ACREG_PULSE_TYPE_FLAG   (1 << 7)
+
+	/** Supplementary control register */
+	ioport32_t scr;
+#define AM335x_UART_SCR_DMA_MODE_CTL_FLAG   (1 << 0)
+#define AM335x_UART_SCR_DMA_MODE_MASK   (0x3)
+#define AM335x_UART_SCR_DMA_MODE_SHIFT   (1)
+#define AM335x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG   (1 << 3)
+#define AM335x_UART_SCR_RX_CTS_WU_EN_FLAG   (1 << 4)
+#define AM335x_UART_SCR_TX_TRIG_GRANU1_FLAG   (1 << 6)
+#define AM335x_UART_SCR_RX_TRIG_GRANU1_FLAG   (1 << 7)
+
+	/** Supplementary status register */
+	const ioport32_t ssr;
+#define AM335x_UART_SSR_TX_FIFO_FULL_FLAG   (1 << 0)
+#define AM335x_UART_SSR_RX_CTS_WU_STS_FLAG   (1 << 1)
+#define AM335x_UART_SSR_DMA_COUNTER_RESET_FLAG   (1 << 2)
+
+	/** BOF Length register (IrDA only)*/
+	ioport32_t eblr;
+#define AM335x_IRDA_EBLR_DISABLED   (0x00)
+#define AM335x_IRDA_EBLR_RX_STOP_BITS(bits)   (bits & 0xff)
+
+	uint32_t padd0_;
+
+	/** Module version register */
+	const ioport32_t mvr;
+#define AM335x_UART_MVR_MINOR_MASK   (0xf)
+#define AM335x_UART_MVR_MINOR_SHIFT   (0)
+#define AM335x_UART_MVR_MAJOR_MASK   (0xf)
+#define AM335x_UART_MVR_MAJOR_SHIFT   (4)
+
+	/** System configuration register */
+	ioport32_t sysc;
+#define AM335x_UART_SYSC_AUTOIDLE_FLAG   (1 << 0)
+#define AM335x_UART_SYSC_SOFTRESET_FLAG   (1 << 1)
+#define AM335x_UART_SYSC_ENWAKEUP_FLAG   (1 << 2)
+#define AM335x_UART_SYSC_IDLE_MODE_MASK   (0x3)
+#define AM335x_UART_SYSC_IDLE_MODE_SHIFT   (3)
+#define AM335x_UART_SYSC_IDLE_MODE_FORCE   (0x0)
+#define AM335x_UART_SYSC_IDLE_MODE_NO   (0x1)
+#define AM335x_UART_SYSC_IDLE_MODE_SMART   (0x2)
+
+	/** System status register */
+	const ioport32_t syss;
+#define AM335x_UART_SYSS_RESETDONE_FLAG   (1 << 0)
+
+	/** Wake-up enable register */
+	ioport32_t wer;
+#define AM335x_UART_WER_CTS_ACTIVITY_FLAG  (1 << 0)
+#define AM335x_UART_WER_RI_ACTIVITY_FLAG  (1 << 2)
+#define AM335x_UART_WER_RX_ACTIVITY_FLAG  (1 << 4)
+#define AM335x_UART_WER_RHR_IRQ_FLAG  (1 << 5)
+#define AM335x_UART_WER_RLS_IRQ_FLAG  (1 << 6)
+#define AM335x_UART_WER_TX_WAKEUP_EN_FLAG  (1 << 7)
+
+	/** Carrier frequency prescaler */
+	ioport32_t cfps;
+#define AM335x_UART_CFPS_MASK   (0xff)
+
+	/** Number of bytes in RX fifo */
+	const ioport32_t rx_fifo_lvl;
+#define AM335x_UART_RX_FIFO_LVL_MASK   (0xff)
+
+	/** Number of bytes in TX fifo */
+	const ioport32_t tx_fifo_lvl;
+#define AM335x_UART_TX_FIFO_LVL_MASK   (0xff)
+
+	/** RX/TX empty interrupts */
+	ioport32_t ier2;
+#define AM335x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 0)
+#define AM335x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 1)
+
+	/** RX/TX empty status */
+	ioport32_t isr2;
+#define AM335x_UART_ISR2_RX_FIFO_EMPTY_FLAG  (1 << 0)
+#define AM335x_UART_ISR2_TX_FIFO_EMPTY_FLAG  (1 << 1)
+
+	/** Set the sample per bit if non default frequency is used */
+	ioport32_t freq_sel;
+#define AM335x_UART_FREQ_SEL_MASK  (0x000000FF)
+
+	uint32_t padd2_[2];
+
+	/** Mode definition register 3 */
+	ioport32_t mdr3;
+#define AM335x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG   (1 << 0)
+} am335x_uart_regs_t;
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/amdm37x/dispc.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x/dispc.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/include/drivers/amdm37x/dispc.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,394 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM/DM37x SDRAM Memory Scheduler.
+ */
+
+#ifndef KERN_AMDM37x_DISPC_H_
+#define KERN_AMDM37x_DISPC_H_
+
+/* AMDM37x TRM p. 1813 */
+#define AMDM37x_DISPC_BASE_ADDRESS 0x48050400
+#define AMDM37x_DISPC_SIZE 1024
+
+#define __paddname(line) PADD32_ ## line
+#define _paddname(line) __paddname(line)
+#define PADD32(count) uint32_t _paddname(__LINE__)[count]
+
+#include <typedefs.h>
+
+typedef struct {
+	const ioport32_t revision;
+#define AMDM37X_DISPC_REVISION_MASK  0xff
+
+	PADD32(3);
+	ioport32_t sysconfig;
+#define AMDM37X_DISPC_SYSCONFIG_AUTOIDLE_FLAG  (1 << 0)
+#define AMDM37X_DISPC_SYSCONFIG_SOFTRESET_FLAG  (1 << 1)
+#define AMDM37X_DISPC_SYSCONFIG_ENWAKEUP_FLAG  (1 << 2)
+#define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_MASK  0x3
+#define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_SHIFT  3
+#define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_MASK  0x3
+#define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_SHIFT  8
+#define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_MASK  0x3
+#define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_SHIFT  12
+
+	const ioport32_t sysstatus;
+#define AMDM37X_DISPC_SYSSTATUS_RESETDONE_FLAG  (1 << 0)
+
+	ioport32_t irqstatus;
+	ioport32_t irqenable;
+#define AMDM37X_DISPC_IRQ_FRAMEDONE_FLAG  (1 << 0)
+#define AMDM37X_DISPC_IRQ_VSYNC_FLAG  (1 << 1)
+#define AMDM37X_DISPC_IRQ_EVSYNCEVEN_FLAG  (1 << 2)
+#define AMDM37X_DISPC_IRQ_EVSYNCODD_FLAG  (1 << 3)
+#define AMDM37X_DISPC_IRQ_ACBIASCOUNTSTATUS_FLAG  (1 << 4)
+#define AMDM37X_DISPC_IRQ_PROGRAMMEDLINENUMBER_FLAG  (1 << 5)
+#define AMDM37X_DISPC_IRQ_GFXFIFOUNDERFLOW_FLAG  (1 << 6)
+#define AMDM37X_DISPC_IRQ_GFXENDWINDOW_FLAG  (1 << 7)
+#define AMDM37X_DISPC_IRQ_PALETTEGAMMALOADING_FLAG  (1 << 8)
+#define AMDM37X_DISPC_IRQ_OPCERROR_FLAG  (1 << 9)
+#define AMDM37X_DISPC_IRQ_VID1FIFOUNDERFLOW_FLAG  (1 << 10)
+#define AMDM37X_DISPC_IRQ_VID1ENDWINDOW_FLAG  (1 << 11)
+#define AMDM37X_DISPC_IRQ_VID2FIFOUNDERFLOW_FLAG  (1 << 12)
+#define AMDM37X_DISPC_IRQ_VID2ENDWINDOW_FLAG  (1 << 13)
+#define AMDM37X_DISPC_IRQ_SYNCLOST_FLAG  (1 << 14)
+#define AMDM37X_DISPC_IRQ_SYNCLOSTDIGITAL_FLAG  (1 << 15)
+#define AMDM37X_DISPC_IRQ_WAKEUP_FLAG  (1 << 16)
+
+	PADD32(8);
+	ioport32_t control;
+#define AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG  (1 << 0)
+#define AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG  (1 << 1)
+#define AMDM37X_DISPC_CONTROL_MONOCOLOR_FLAG  (1 << 2)
+#define AMDM37X_DISPC_CONTROL_STNTFT_FLAG  (1 << 3)
+#define AMDM37X_DISPC_CONTROL_M8B_FLAG  (1 << 4)
+#define AMDM37X_DISPC_CONTROL_GOLCD_FLAG  (1 << 5)
+#define AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG  (1 << 6)
+#define AMDM37X_DISPC_CONTROL_STDITHERENABLE_FLAG  (1 << 7)
+#define AMDM37X_DISPC_CONTROL_TFTDATALINES_MASK  0x3
+#define AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT  8
+#define AMDM37X_DISPC_CONTROL_TFTDATALINES_12B  0
+#define AMDM37X_DISPC_CONTROL_TFTDATALINES_16B  1
+#define AMDM37X_DISPC_CONTROL_TFTDATALINES_18B  2
+#define AMDM37X_DISPC_CONTROL_TFTDATALINES_24B  3
+#define AMDM37X_DISPC_CONTROL_STALLMODE_FLAG  (1 << 11)
+#define AMDM37X_DISPC_CONTROL_OVERLAYOPTIMIZATION_FLAG  (1 << 12)
+#define AMDM37X_DISPC_CONTROL_GPIN0_FLAG  (1 << 13)
+#define AMDM37X_DISPC_CONTROL_GPIN1_FLAG  (1 << 14)
+#define AMDM37X_DISPC_CONTROL_GPOUT0_FLAG  (1 << 15)
+#define AMDM37X_DISPC_CONTROL_GPOUT1_FLAG  (1 << 16)
+#define AMDM37X_DISPC_CONTROL_HT_MASK  0x7
+#define AMDM37X_DISPC_CONTROL_HT_SHIFT  17
+#define AMDM37X_DISPC_CONTROL_TDMENABLE_FLAG  (1 << 20)
+#define AMDM37X_DISPC_CONTROL_TDMPARALLELMODE_MASK  0x3
+#define AMDM37X_DISPC_CONTROL_TDMPARELLELMODE_SHIFT  21
+#define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_MASK  0x3
+#define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_SHIFT  23
+#define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_MASK  0x3
+#define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_SHIFT  25
+#define AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG  (1 << 27)
+#define AMDM37X_DISPC_CONTROL_LCDENABLESIGNAL_FLAG  (1 << 28)
+#define AMDM37X_DISPC_CONTROL_KCDENABLEPOL_FLAG  (1 << 29)
+#define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK  0x3
+#define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT  30
+
+	ioport32_t config;
+#define AMDM37X_DISPC_CONFIG_PIXELGATED_FLAG  (1 << 0)
+#define AMDM37X_DISPC_CONFIG_LOADMODE_MASK  0x3
+#define AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT  1
+#define AMDM37X_DISPC_CONFIG_LOADMODE_PGDATAEVERYFRAME  0x0
+#define AMDM37X_DISPC_CONFIG_LOADMODE_PGUSER  0x1
+#define AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME  0x2
+#define AMDM37X_DISPC_CONFIG_LOADMODE_PGDFIRSTFRAME  0x3
+#define AMDM37X_DISPC_CONFIG_PALETTEGAMMATABLE_FLAG  (1 << 3)
+#define AMDM37X_DISPC_CONFIG_PIXELDATAGATED_FLAG  (1 << 4)
+#define AMDM37X_DISPC_CONFIG_PIXELCLOCKGATED_FLAG  (1 << 5)
+#define AMDM37X_DISPC_CONFIG_HSYNCGATED_FLAG  (1 << 6)
+#define AMDM37X_DISPC_CONFIG_VSYNCGATED_FLAG  (1 << 7)
+#define AMDM37X_DISPC_CONFIG_ACBIASGATED_FLAG  (1 << 8)
+#define AMDM37X_DISPC_CONFIG_FUNCGATED_FLAG  (1 << 9)
+#define AMDM37X_DISPC_CONFIG_TCKLCDENABLE_FLAG  (1 << 10)
+#define AMDM37X_DISPC_CONFIG_TCKLCDSELECTION_FLAG  (1 << 11)
+#define AMDM37X_DISPC_CONFIG_TCKDIGENABLE_FLAG  (1 << 12)
+#define AMDM37X_DISPC_CONFIG_TCKDIGSELECTION_FLAG  (1 << 13)
+#define AMDM37X_DISPC_CONFIG_FIFOMERGE_FLAG  (1 << 14)
+#define AMDM37X_DISPC_CONFIG_CPR_FLAG  (1 << 15)
+#define AMDM37X_DISPC_CONFIG_FIFOHANDCHECK_FLAG  (1 << 16)
+#define AMDM37X_DISPC_CONFIG_FIFOFILLING_FLAG  (1 << 17)
+#define AMDM37X_DISPC_CONFIG_LCDPALPHABLENDERENABLDE_FLAG  (1 << 18)
+#define AMDM37X_DISPC_CONFIG_TVALPHABLENDERENABLE_FLAG  (1 << 19)
+
+	PADD32(1);
+	ioport32_t default_color[2];
+	ioport32_t trans_color[2];
+#define AMDM37X_DISPC_COLOR_MASK 0xffffff
+
+	const ioport32_t line_status;
+	ioport32_t line_number;
+#define AMDM37X_DISPC_LINE_NUMBER_MASK 0x3ff
+
+	ioport32_t timing_h;
+#define AMDM37X_DISPC_TIMING_H_HSW_MASK 0xff
+#define AMDM37X_DISPC_TIMING_H_HSW_SHIFT 0
+#define AMDM37X_DISPC_TIMING_H_HFP_MASK 0xfff
+#define AMDM37X_DISPC_TIMING_H_HFP_SHIFT 8
+#define AMDM37X_DISPC_TIMING_H_HBP_MASK 0xfff
+#define AMDM37X_DISPC_TIMING_H_HBP_SHIFT 20
+
+	ioport32_t timing_v;
+#define AMDM37X_DISPC_TIMING_V_VSW_MASK 0xff
+#define AMDM37X_DISPC_TIMING_V_VSW_SHIFT 0
+#define AMDM37X_DISPC_TIMING_V_VFP_MASK 0xfff
+#define AMDM37X_DISPC_TIMING_V_VFP_SHIFT 8
+#define AMDM37X_DISPC_TIMING_V_VBP_MASK 0xfff
+#define AMDM37X_DISPC_TIMING_V_VBP_SHIFT 20
+
+	ioport32_t pol_freq;
+#define AMDM37X_DISPC_POL_FREQ_ACB_MASK  0xff
+#define AMDM37X_DISPC_POL_FREQ_ACB_SHIFT 0
+#define AMDM37X_DISPC_POL_FREQ_ACBI_MASK  0xf
+#define AMDM37X_DISPC_POL_FREQ_ACBI_SHIFT 8
+#define AMDM37X_DISPC_POL_FREQ_IVS_FLAG  (1 << 12)
+#define AMDM37X_DISPC_POL_FREQ_IHS_FLAG  (1 << 13)
+#define AMDM37X_DISPC_POL_FREQ_IPC_FLAG  (1 << 14)
+#define AMDM37X_DISPC_POL_FREQ_IEO_FLAG  (1 << 15)
+#define AMDM37X_DISPC_POL_FREQ_RF_FLAG  (1 << 16)
+#define AMDM37X_DISPC_POL_FREQ_ONOFF_FLAG  (1 << 17)
+
+	ioport32_t divisor;
+#define AMDM37X_DISPC_DIVISOR_PCD_MASK  0xff
+#define AMDM37X_DISPC_DIVISOR_PCD_SHIFT  0
+#define AMDM37X_DISPC_DIVISOR_LCD_MASK  0xff
+#define AMDM37X_DISPC_DIVISOR_LCD_SHIFT  16
+
+	ioport32_t global_alpha;
+#define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_MASK  0xff
+#define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_SHIFT  0
+#define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_MASK  0xff
+#define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_SHIFT  16
+
+	ioport32_t size_dig;
+	ioport32_t size_lcd;
+
+	struct {
+		ioport32_t ba[2];
+		ioport32_t position;
+#define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_MASK  0x7ff
+#define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_SHIFT  0
+#define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_MASK  0x7ff
+#define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_SHIFT  16
+
+		ioport32_t size;
+#define AMDM37X_DISPC_SIZE_WIDTH_MASK  0x7ff
+#define AMDM37X_DISPC_SIZE_WIDTH_SHIFT  0
+#define AMDM37X_DISPC_SIZE_HEIGHT_MASK  0x7ff
+#define AMDM37X_DISPC_SIZE_HEIGHT_SHIFT  16
+
+		PADD32(4);
+		ioport32_t attributes;
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG  (1 << 0)
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_MASK  0xf
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT  1
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB16  0x5
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16  0x6
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24_32  0x8
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24  0x9
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB  0xc
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBA  0xd
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX  0xe
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_REPLICATIONENABLE_FLAG  (1 << 5)
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_MASK  0x3
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_SHIFT  6
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT_FLAG  (1 << 8)
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE_FLAG  (1 << 9)
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXENDIANNES_FLAG  (1 << 10)
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXFIFOPRELOAD_FLAG  (1 << 11)
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_MASK  0x3
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_SHIFT  12
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXARBITRATION_FLAG  (1 << 14)
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXSELFREFRESH_FLAG  (1 << 15)
+#define AMDM37X_DISPC_GFX_ATTRIBUTES_PREMULTIALPHA_FLAG  (1 << 28)
+
+
+		ioport32_t fifo_threshold;
+		const ioport32_t fifo_size_status;
+		ioport32_t row_inc;
+		ioport32_t pixel_inc;
+		ioport32_t window_skip;
+		ioport32_t table_ba;
+	} gfx;
+
+	struct {
+		ioport32_t ba[2];
+		ioport32_t position;
+		ioport32_t size;
+		ioport32_t attributes;
+		ioport32_t fifo_threshold;
+		const ioport32_t fifo_size_status;
+		ioport32_t row_inc;
+		ioport32_t pixel_inc;
+		ioport32_t fir;
+		ioport32_t picture_size;
+		ioport32_t accui[2];
+		struct {
+			ioport32_t hi;
+			ioport32_t hvi;
+		} fir_coef[8];
+		ioport32_t conv_coef[5];
+		PADD32(2);
+	} vid[2];
+	/* 0x1d4 */
+	ioport32_t data_cycle[3];
+	/* 0x1e0 */
+	ioport32_t vid_fir_coef_v[8];
+	/* 0x200 */
+	PADD32(8);
+	/* 0x220 */
+	ioport32_t cpr_coef_r;
+	ioport32_t cpr_coef_g;
+	ioport32_t cpr_coef_b;
+	ioport32_t gfx_preload;
+
+	/* 0x230 */
+	ioport32_t vid_preload[2];
+
+} __attribute__((packed)) amdm37x_dispc_regs_t;
+
+
+static inline void amdm37x_dispc_setup_fb(amdm37x_dispc_regs_t *regs,
+    unsigned x, unsigned y, unsigned bpp, uintptr_t pa)
+{
+	ASSERT(regs);
+	/* Init sequence for dispc is in chapter 7.6.5.1.4 p. 1810,
+	 * no idea what parts of that work. */
+
+	/* Disable all interrupts */
+	regs->irqenable = 0;
+
+	/* Pixel format specifics*/
+	uint32_t attrib_pixel_format = 0;
+	uint32_t control_data_lanes = 0;
+	switch (bpp)
+	{
+	case 32:
+		attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX;
+		control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
+		break;
+	case 24:
+		attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24;
+		control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
+		break;
+	case 16:
+		attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16;
+		control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_16B;
+		break;
+	default:
+		ASSERT(false);
+	}
+
+	/* Prepare sizes */
+	const uint32_t size_reg =
+	    (((x - 1) & AMDM37X_DISPC_SIZE_WIDTH_MASK)
+	        << AMDM37X_DISPC_SIZE_WIDTH_SHIFT) |
+	    (((y - 1) & AMDM37X_DISPC_SIZE_HEIGHT_MASK)
+	        << AMDM37X_DISPC_SIZE_HEIGHT_SHIFT);
+
+	/* modes taken from u-boot, for 1024x768 */
+	// TODO replace magic values with actual correct values
+//	regs->timing_h = 0x1a4024c9;
+//	regs->timing_v = 0x02c00509;
+//	regs->pol_freq = 0x00007028;
+//	regs->divisor  = 0x00010001;
+
+	/* setup output */
+	regs->size_lcd = size_reg;
+	regs->size_dig = size_reg;
+
+	/* Nice blue default color */
+	regs->default_color[0] = 0x0000ff;
+	regs->default_color[1] = 0x0000ff;
+
+	/* Setup control register */
+	uint32_t control = 0 |
+		AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG |
+		(control_data_lanes << AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT) |
+		AMDM37X_DISPC_CONTROL_GPOUT0_FLAG |
+		AMDM37X_DISPC_CONTROL_GPOUT1_FLAG;
+	regs->control = control;
+
+	/* No gamma stuff only data */
+	uint32_t config = (AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME
+	            << AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT);
+	regs->config = config;
+
+
+	/* Set framebuffer base address */
+	regs->gfx.ba[0] = pa;
+	regs->gfx.ba[1] = pa;
+	regs->gfx.position = 0;
+
+	/* Setup fb size */
+	regs->gfx.size = size_reg;
+
+	/* Set pixel format */
+	uint32_t attribs = 0 |
+	    (attrib_pixel_format << AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT);
+	regs->gfx.attributes = attribs;
+
+	/* 0x03ff03c0 is the default */
+	regs->gfx.fifo_threshold = 0x03ff03c0;
+	/* This value should be stride - width, 1 means next pixel i.e.
+	 * stride == width */
+	regs->gfx.row_inc = 1;
+	/* number of bytes to next pixel in BPP multiples */
+	regs->gfx.pixel_inc = 1;
+	/* only used if video is played over fb */
+	regs->gfx.window_skip = 0;
+	/* Gamma and palette table */
+	regs->gfx.table_ba = 0;
+
+	/* enable frame buffer graphics */
+	regs->gfx.attributes |= AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG;
+	/* Update register values */
+	regs->control |= AMDM37X_DISPC_CONTROL_GOLCD_FLAG;
+	regs->control |= AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG;
+	/* Enable output */
+	regs->control |= AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG;
+	regs->control |= AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG;
+}
+
+
+#endif
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/amdm37x/gpt.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x/gpt.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/include/drivers/amdm37x/gpt.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM/DM37x MPU general purpose timer driver.
+ */
+
+#ifndef KERN_AMDM37x_GPT_H_
+#define KERN_AMDM37x_GPT_H_
+
+#include <typedefs.h>
+#include <mm/km.h>
+
+/* AMDM37x TRM p. 2740 */
+#define AMDM37x_GPT1_BASE_ADDRESS  0x48318000
+#define AMDM37x_GPT1_SIZE  4096
+#define AMDM37x_GPT1_IRQ  37
+#define AMDM37x_GPT2_BASE_ADDRESS  0x49032000
+#define AMDM37x_GPT2_SIZE  4096
+#define AMDM37x_GPT2_IRQ  38
+#define AMDM37x_GPT3_BASE_ADDRESS  0x49034000
+#define AMDM37x_GPT3_SIZE  4096
+#define AMDM37x_GPT3_IRQ  39
+#define AMDM37x_GPT4_BASE_ADDRESS  0x49036000
+#define AMDM37x_GPT4_SIZE  4096
+#define AMDM37x_GPT4_IRQ  40
+#define AMDM37x_GPT5_BASE_ADDRESS  0x49038000
+#define AMDM37x_GPT5_SIZE  4096
+#define AMDM37x_GPT5_IRQ  41
+#define AMDM37x_GPT6_BASE_ADDRESS  0x4903a000
+#define AMDM37x_GPT6_SIZE  4096
+#define AMDM37x_GPT6_IRQ  42
+#define AMDM37x_GPT7_BASE_ADDRESS  0x4903c000
+#define AMDM37x_GPT7_SIZE  4096
+#define AMDM37x_GPT7_IRQ  43
+#define AMDM37x_GPT8_BASE_ADDRESS  0x4903e000
+#define AMDM37x_GPT8_SIZE  4096
+#define AMDM37x_GPT8_IRQ  44
+#define AMDM37x_GPT9_BASE_ADDRESS  0x49040000
+#define AMDM37x_GPT9_SIZE  4096
+#define AMDM37x_GPT9_IRQ  45
+#define AMDM37x_GPT10_BASE_ADDRESS  0x48086000
+#define AMDM37x_GPT10_SIZE  4096
+#define AMDM37x_GPT10_IRQ  46
+#define AMDM37x_GPT11_BASE_ADDRESS  0x48088000
+#define AMDM37x_GPT11_SIZE  4096
+#define AMDM37x_GPT11_IRQ  47
+
+
+/** GPT register map AMDM37x TRM p. 2740 */
+typedef struct {
+	/** IP revision */
+	const ioport32_t tidr;
+#define AMDM37x_GPT_TIDR_MINOR_MASK  (0xf)
+#define AMDM37x_GPT_TIDR_MINOR_SHIFT  (0)
+#define AMDM37x_GPT_TIDR_MAJOR_MASK  (0xf)
+#define AMDM37x_GPT_TIDR_MAJOR_SHIFT  (4)
+	uint32_t padd0_[3];
+
+	/** L4 Interface parameters */
+	ioport32_t tiocp_cfg;
+#define AMDM37x_GPT_TIOCP_CFG_AUTOIDLE_FLAG  (1 << 0)
+#define AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG  (1 << 1)
+#define AMDM37x_GPT_TIOCP_CFG_ENWAKEUP_FLAG  (1 << 2)
+#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_MASK  (0x3)
+#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_SHIFT  (3)
+#define AMDM37x_GPT_TIOCP_CFG_EMUFREE_FlAG  (1 << 5)
+#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_MASK  (0x3)
+#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_SHIFT (8)
+
+	/** Module status information, excluding irq */
+	const ioport32_t tistat;
+#define AMDM37x_GPT_TISTAT_RESET_DONE_FLAG  (1 << 0)
+
+	/** Interrupt status register */
+	ioport32_t tisr;
+#define AMDM37x_GPT_TISR_MAT_IRQ_FLAG  (1 << 0)
+#define AMDM37x_GPT_TISR_OVF_IRQ_FLAG  (1 << 1)
+#define AMDM37x_GPT_TISR_TCAR_IRQ_FLAG  (1 << 2)
+
+	/* Interrupt enable register */
+	ioport32_t tier;
+#define AMDM37x_GPT_TIER_MAT_IRQ_FLAG  (1 << 0)
+#define AMDM37x_GPT_TIER_OVF_IRQ_FLAG  (1 << 1)
+#define AMDM37x_GPT_TIER_TCAR_IRQ_FLAG  (1 << 2)
+
+	/** Wakeup enable register */
+	ioport32_t twer;
+#define AMDM37x_GPT_TWER_MAT_IRQ_FLAG  (1 << 0)
+#define AMDM37x_GPT_TWER_OVF_IRQ_FLAG  (1 << 1)
+#define AMDM37x_GPT_TWER_TCAR_IRQ_FLAG  (1 << 2)
+
+	/** Optional features control register */
+	ioport32_t tclr;
+#define AMDM37x_GPT_TCLR_ST_FLAG  (1 << 0)
+#define AMDM37x_GPT_TCLR_AR_FLAG  (1 << 1)
+#define AMDM37x_GPT_TCLR_PTV_MASK  (0x7)
+#define AMDM37x_GPT_TCLR_PTV_SHIFT  (2)
+#define AMDM37x_GPT_TCLR_PRE_FLAG  (1 << 5)
+#define AMDM37x_GPT_TCLR_CE_FLAG  (1 << 6)
+#define AMDM37x_GPT_TCLR_SCPWM  (1 << 7)
+#define AMDM37x_GPT_TCLR_TCM_MASK  (0x3)
+#define AMDM37x_GPT_TCLR_TCM_SHIFT  (8)
+#define AMDM37x_GPT_TCLR_TRG_MASK  (0x3)
+#define AMDM37x_GPT_TCLR_TRG_SHIFT (10)
+#define AMDM37x_GPT_TCLR_PT_FLAG  (1 << 12)
+#define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG  (1 << 13)
+#define AMDM37x_GPT_TCLR_GPO_CFG_FLAG  (1 << 14)
+
+	/** Value of timer counter */
+	ioport32_t tccr;
+
+	/** Timer load register */
+	ioport32_t tldr;
+
+	/** Timer trigger register */
+	ioport32_t ttgr;
+
+	/** Write-posted pending register */
+	const ioport32_t twps;
+#define AMDM37x_GPT_TWPS_TCLR_FLAG  (1 << 0)
+#define AMDM37x_GPT_TWPS_TCRR_FLAG  (1 << 1)
+#define AMDM37x_GPT_TWPS_TLDR_FLAG  (1 << 2)
+#define AMDM37x_GPT_TWPS_TTGR_FLAG  (1 << 3)
+#define AMDM37x_GPT_TWPS_TMAR_FLAG  (1 << 4)
+#define AMDM37x_GPT_TWPS_TPIR_FLAG  (1 << 5)
+#define AMDM37x_GPT_TWPS_TNIR_FLAG  (1 << 6)
+#define AMDM37x_GPT_TWPS_TCVR_FLAG  (1 << 7)
+#define AMDM37x_GPT_TWPS_TOCR_FLAG  (1 << 8)
+#define AMDM37x_GPT_TWPS_TOWR_FLAG  (1 << 9)
+
+	/** Timer match register */
+	ioport32_t tmar;
+
+	/** Capture value 1 register */
+	const ioport32_t tcar1;
+
+	/** Software interface control register */
+	ioport32_t tsicr;
+#define AMDM37x_GPT_TSICR_SFT_FLAG  (1 << 1)
+#define AMDM37x_GPT_TSICR_POSTED_FLAG  (1 << 2)
+
+	/** Capture value 2 register */
+	const ioport32_t tcar2;
+
+	/* GPT1,2,10 only (used for 1ms time period generation)*/
+
+	/** Positive increment register */
+	ioport32_t tpir;
+
+	/** Negative increment register */
+	ioport32_t tnir;
+
+	/** Counter value register */
+	ioport32_t tcvr;
+
+	/** Mask the tick interrupt for selected number of ticks */
+	ioport32_t tocr;
+
+	/** Number of masked overflow interrupts */
+	ioport32_t towr;
+} amdm37x_gpt_regs_t;
+
+typedef struct {
+	amdm37x_gpt_regs_t *regs;
+	bool special_available;
+} amdm37x_gpt_t;
+
+static inline void amdm37x_gpt_timer_ticks_init(
+    amdm37x_gpt_t* timer, uintptr_t ioregs, size_t iosize, unsigned hz)
+{
+	/* Set 32768 Hz clock as source */
+	// TODO find a nicer way to setup 32kHz clock source for timer1
+	// reg 0x48004C40 is CM_CLKSEL_WKUP see page 485 of the manual
+	ioport32_t *clksel = (void*) km_map(0x48004C40, 4, PAGE_NOT_CACHEABLE);
+	*clksel &= ~1;
+	km_unmap((uintptr_t)clksel, 4);
+
+	ASSERT(timer);
+	/* Map control register */
+	timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
+
+	/* Set autoreload */
+	timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG;
+
+	timer->special_available = (
+	    (ioregs == AMDM37x_GPT1_BASE_ADDRESS) ||
+	    (ioregs == AMDM37x_GPT2_BASE_ADDRESS) ||
+	    (ioregs == AMDM37x_GPT10_BASE_ADDRESS));
+	timer->regs->tldr = 0xffffffff - (32768 / hz) + 1;
+	timer->regs->tccr = 0xffffffff - (32768 / hz) + 1;
+	if (timer->special_available) {
+		/* Set values for according to formula (manual p. 2733) */
+		/* Use temporary variables for easier debugging */
+		const uint32_t tpir =
+		    ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz));
+		const uint32_t tnir =
+		    ((32768 / hz) * 1000000) - (32768000 * (1000 / hz));
+		timer->regs->tpir = tpir;
+		timer->regs->tnir = tnir;
+	}
+
+}
+
+static inline void amdm37x_gpt_timer_ticks_start(amdm37x_gpt_t* timer)
+{
+	ASSERT(timer);
+	ASSERT(timer->regs);
+	/* Enable overflow interrupt */
+	timer->regs->tier |= AMDM37x_GPT_TIER_OVF_IRQ_FLAG;
+	/* Start timer */
+	timer->regs->tclr |= AMDM37x_GPT_TCLR_ST_FLAG;
+}
+
+static inline void amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
+{
+	ASSERT(timer);
+	ASSERT(timer->regs);
+	/* Clear all pending interrupts */
+	timer->regs->tisr = timer->regs->tisr;
+}
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/amdm37x/irc.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x/irc.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/include/drivers/amdm37x/irc.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM/DM37x MPU on-chip interrupt controller driver.
+ */
+
+#ifndef KERN_AMDM37x_IRQC_H_
+#define KERN_AMDM37x_IRQC_H_
+
+/* AMDM37x TRM p. 1079 */
+#define AMDM37x_IRC_BASE_ADDRESS 0x48200000
+#define AMDM37x_IRC_SIZE 4096
+
+#define AMDM37x_IRC_IRQ_COUNT 96
+
+#include <typedefs.h>
+
+typedef struct {
+	const ioport32_t revision; /**< Revision */
+#define AMDM37x_IRC_REV_MASK (0xff)
+
+	uint8_t padd0_[12];
+
+	ioport32_t sysconfig; /**< SYS config */
+#define AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0)
+#define AMDM37x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1)
+
+	const ioport32_t sysstatus; /**< SYS status */
+#define AMDM37x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0)
+
+	uint8_t padd1_[40];
+
+	const ioport32_t sir_irq;   /**< Currently active irq number */
+#define AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK (0x7f)
+#define AMDM37x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK (0xfffffff8)
+
+	const ioport32_t sir_fiq;
+#define AMDM37x_IRC_SIR_FIQ_ACTIVEIRQ_MASK (0x7f)
+#define AMDM37x_IRC_SIR_FIQ_SPURIOUSIRQFLAG_MASK (0xfffffff8)
+
+	ioport32_t control;   /**< New interrupt agreement. */
+#define AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0)
+#define AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1)
+
+	ioport32_t protection;  /**< Protect other registers. */
+#define AMDM37x_IRC_PROTECTION_PROETCTION_FLAG (1 << 0)
+
+	ioport32_t idle;   /**< Idle and autogating */
+#define AMDM37x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0)
+#define AMDM37x_IRC_IDLE_TURBO_FLAG (1 << 1)
+
+	uint8_t padd2_[12];
+
+	ioport32_t irq_priority; /**< Active IRQ priority */
+#define AMDM37x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK (0x7f)
+#define AMDM37x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK (0xfffffff8)
+
+	ioport32_t fiq_priority; /**< Active FIQ priority */
+#define AMDM37x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK (0x7f)
+#define AMDM37x_IRC_FIQ_PRIORITY_SPURIOUSFIQFLAG_MASK (0xfffffff8)
+
+	ioport32_t threshold; /**< Priority threshold */
+#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK (0xff)
+#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED (0x00)
+#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED (0xff)
+
+	uint8_t padd3__[20];
+
+	struct {
+		const ioport32_t itr;   /**< Interrupt input status before masking */
+		ioport32_t mir;   /**< Interrupt mask */
+		ioport32_t mir_clear; /**< Clear mir mask bits */
+		ioport32_t mir_set;   /**< Set mir mask bits */
+		ioport32_t isr_set;   /**< Set software interrupt bits */
+		ioport32_t isr_clear; /**< Clear software interrupt bits */
+		const ioport32_t pending_irq; /**< IRQ status after masking */
+		const ioport32_t pending_fiq; /**< FIQ status after masking */
+	} interrupts[3];
+
+	uint8_t padd4_[32];
+
+	ioport32_t ilr[96];   /**< FIQ/IRQ steering */
+#define AMDM37x_IRC_ILR_FIQNIRQ (1 << 0)
+#define AMDM37x_IRC_ILR_PRIORITY_MASK (0x3f)
+#define AMDM37x_IRC_ILR_PRIORITY_SHIFT (2)
+
+} amdm37x_irc_regs_t;
+
+static inline void amdm37x_irc_dump(amdm37x_irc_regs_t *regs)
+{
+#define DUMP_REG(name) \
+	printf("%s %p(%x).\n", #name, &regs->name, regs->name);
+
+	DUMP_REG(revision);
+	DUMP_REG(sysconfig);
+	DUMP_REG(sysstatus);
+	DUMP_REG(sir_irq);
+	DUMP_REG(sir_fiq);
+	DUMP_REG(control);
+	DUMP_REG(protection);
+	DUMP_REG(idle);
+	DUMP_REG(irq_priority);
+	DUMP_REG(fiq_priority);
+	DUMP_REG(threshold);
+
+	for (int i = 0; i < 3; ++i) {
+		DUMP_REG(interrupts[i].itr);
+		DUMP_REG(interrupts[i].mir);
+		DUMP_REG(interrupts[i].isr_set);
+		DUMP_REG(interrupts[i].pending_irq);
+		DUMP_REG(interrupts[i].pending_fiq);
+	}
+	for (int i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) {
+		DUMP_REG(ilr[i]);
+	}
+
+#undef DUMP_REG
+}
+
+static inline void amdm37x_irc_init(amdm37x_irc_regs_t *regs)
+{
+	/* AMDM37x TRM sec 12.5.1 p. 2425 */
+	/* Program system config register */
+	//TODO enable this when you know the meaning
+	//regs->sysconfig |= AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG;
+
+	/* Program idle register */
+	//TODO enable this when you know the meaning
+	//regs->sysconfig |= AMDM37x_IRC_IDLE_TURBO_FLAG;
+
+	/* Program ilr[m] assign priority, decide fiq */
+	for (unsigned i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) {
+		regs->ilr[i] = 0; /* highest prio(default) route to irq */
+	}
+
+	/* Disable all interrupts */
+	regs->interrupts[0].mir_set = 0xffffffff;
+	regs->interrupts[1].mir_set = 0xffffffff;
+	regs->interrupts[2].mir_set = 0xffffffff;
+}
+
+static inline unsigned amdm37x_irc_inum_get(amdm37x_irc_regs_t *regs)
+{
+	return regs->sir_irq & AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK;
+}
+
+static inline void amdm37x_irc_irq_ack(amdm37x_irc_regs_t *regs)
+{
+	regs->control = AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG;
+}
+
+static inline void amdm37x_irc_fiq_ack(amdm37x_irc_regs_t *regs)
+{
+	regs->control = AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG;
+}
+
+static inline void amdm37x_irc_enable(amdm37x_irc_regs_t *regs, unsigned inum)
+{
+	ASSERT(inum < AMDM37x_IRC_IRQ_COUNT);
+	const unsigned set = inum / 32;
+	const unsigned pos = inum % 32;
+	regs->interrupts[set].mir_clear = (1 << pos);
+}
+
+static inline void amdm37x_irc_disable(amdm37x_irc_regs_t *regs, unsigned inum)
+{
+	ASSERT(inum < AMDM37x_IRC_IRQ_COUNT);
+	const unsigned set = inum / 32;
+	const unsigned pos = inum % 32;
+	regs->interrupts[set].mir_set = (1 << pos);
+}
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/amdm37x/uart.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x/uart.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/include/drivers/amdm37x/uart.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * Copyright (c) 2012 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AMDM37x UART driver
+ */
+
+#ifndef _AMDM37x_UART_H_
+#define _AMDM37x_UART_H_
+
+#include "uart_regs.h"
+
+/* AMDM37x TRM p. 2950 */
+#define AMDM37x_UART1_BASE_ADDRESS   0x4806a000
+#define AMDM37x_UART1_SIZE   1024
+#define AMDM37x_UART1_IRQ   72 /* AMDM37x TRM p. 2418 */
+
+#define AMDM37x_UART2_BASE_ADDRESS   0x4806b000
+#define AMDM37x_UART2_SIZE   1024
+#define AMDM37x_UART2_IRQ   73 /* AMDM37x TRM p. 2418 */
+
+#define AMDM37x_UART3_BASE_ADDRESS   0x49020000
+#define AMDM37x_UART3_SIZE   1024
+#define AMDM37x_UART3_IRQ   74 /* AMDM37x TRM p. 2418 */
+
+#define AMDM37x_UART4_BASE_ADDRESS   0x49042000
+#define AMDM37x_UART4_SIZE   1024
+#define AMDM37x_UART4_IRQ   80 /* AMDM37x TRM p. 2418 */
+
+typedef struct {
+	amdm37x_uart_regs_t *regs;
+	indev_t *indev;
+	outdev_t outdev;
+	irq_t irq;
+} amdm37x_uart_t;
+
+
+bool amdm37x_uart_init(amdm37x_uart_t *, inr_t, uintptr_t, size_t);
+void amdm37x_uart_input_wire(amdm37x_uart_t *, indev_t *);
+
+#endif
+
+/**
+ * @}
+ */
Index: kernel/genarch/include/drivers/amdm37x/uart_regs.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x/uart_regs.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/include/drivers/amdm37x/uart_regs.h	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,431 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AMDM37x UART memory mapped registers.
+ */
+
+#ifndef KERN_AMDM37x_UART_H_
+#define KERN_AMDM37x_UART_H_
+
+#include <typedefs.h>
+#include <console/chardev.h>
+#include <ddi/irq.h>
+
+typedef struct {
+	union {
+		/** Stores lower part of the 14-bit baud divisor */
+		ioport32_t dll;
+#define AMDM37x_UART_DLL_MASK   (0xff)
+
+		/** Receive holding register */
+		const ioport32_t rhr;
+#define AMDM37x_UART_RHR_MASK   (0xff)
+
+		/** Transmit holding register */
+		ioport32_t thr;
+#define AMDM37x_UART_THR_MASK   (0xff)
+	};
+
+	union {
+		/** Stores higher part of the 14-bit baud divisor */
+		ioport32_t dlh;
+#define AMDM37x_UART_DLH_MASK   (0x1f)
+
+		/** Interrupt enable registers */
+		ioport32_t ier;
+#define AMDM37x_UART_IER_RHR_IRQ_FLAG   (1 << 0)
+#define AMDM37x_UART_IER_THR_IRQ_FLAG   (1 << 1)
+#define AMDM37x_UART_IER_LINE_STS_IRQ_FLAG   (1 << 2)
+#define AMDM37x_UART_IER_MODEM_STS_IRQ_FLAG   (1 << 3)
+#define AMDM37x_UART_IER_SLEEP_MODE_FLAG   (1 << 4)
+#define AMDM37x_UART_IER_XOFF_IRQ_FLAG   (1 << 5)
+#define AMDM37x_UART_IER_RTS_IRQ_FLAG   (1 << 6)
+#define AMDM37x_UART_IER_CTS_IRQ_FLAG   (1 << 7)
+
+#define AMDM37x_CIR_IER_RHR_IRQ_FLAG   (1 << 0)
+#define AMDM37x_CIR_IER_THR_IRQ_FLAG   (1 << 1)
+#define AMDM37x_CIR_IER_RX_STOP_IRQ_FLAG   (1 << 2)
+#define AMDM37x_CIR_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
+#define AMDM37x_CIR_IER_TX_STS_IRQ_FLAG   (1 << 5)
+
+#define AMDM37x_IRDA_IER_RHR_IRQ_FLAG   (1 << 0)
+#define AMDM37x_IRDA_IER_THR_IRQ_FLAG   (1 << 1)
+#define AMDM37x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG   (1 << 2)
+#define AMDM37x_IRDA_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
+#define AMDM37x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG   (1 << 4)
+#define AMDM37x_IRDA_IER_TX_STS_IRQ_FLAG   (1 << 5)
+#define AMDM37x_IRDA_IER_LINE_STS_IRQ_FLAG   (1 << 6)
+#define AMDM37x_IRDA_IER_EOF_IRQ_FLAG   (1 << 7)
+	};
+
+	union {
+		/** Interrupt identification register */
+		const ioport32_t iir;
+#define AMDM37x_UART_IIR_IRQ_PENDING_FLAG   (1 << 0)
+#define AMDM37x_UART_IIR_TYPE_MASK   (0x1f)
+#define AMDM37x_UART_IIR_TYPE_SHIFT   (1)
+#define AMDM37x_UART_IIR_FCR_MASK   (0x3)
+#define AMDM37x_UART_IIR_FCR_SHIFT   (6)
+
+#define AMDM37x_CIR_IIR_RHR_IRQ_FLAG   (1 << 0)
+#define AMDM37x_CIR_IIR_THR_IRQ_FLAG   (1 << 1)
+#define AMDM37x_CIR_IIR_RX_STOP_IRQ_FLAG   (1 << 2)
+#define AMDM37x_CIR_IIR_RX_OE_IRQ_FLAG   (1 << 3)
+#define AMDM37x_CIR_IIR_TX_STS_IRQ_FLAG   (1 << 5)
+
+#define AMDM37x_IRDA_IIR_RHR_IRQ_FLAG   (1 << 0)
+#define AMDM37x_IRDA_IIR_THR_IRQ_FLAG   (1 << 1)
+#define AMDM37x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG   (1 << 2)
+#define AMDM37x_IRDA_IIR_RX_OE_IRQ_FLAG   (1 << 3)
+#define AMDM37x_IRDA_IIR_STS_FIFO_IRQ_FLAG   (1 << 4)
+#define AMDM37x_IRDA_IIR_TX_STS_IRQ_FLAG   (1 << 5)
+#define AMDM37x_IRDA_IIR_LINE_STS_IRQ_FLAG   (1 << 6)
+#define AMDM37x_IRDA_IIR_EOF_IRQ_FLAG   (1 << 7)
+
+		/** FIFO control register */
+		ioport32_t fcr;
+#define AMDM37x_UART_FCR_FIFO_EN_FLAG   (1 << 0)
+#define AMDM37x_UART_FCR_RX_FIFO_CLR_FLAG   (1 << 1)
+#define AMDM37x_UART_FCR_TX_FIFO_CLR_FLAG   (1 << 3)
+#define AMDM37x_UART_FCR_DMA_MODE_FLAG   (1 << 4)
+
+#define AMDM37x_UART_FCR_TX_FIFO_TRIG_MASK   (0x3)
+#define AMDM37x_UART_FCR_TX_FIFO_TRIG_SHIFT   (4)
+
+#define AMDM37x_UART_FCR_RX_FIFO_TRIG_MASK   (0x3)
+#define AMDM37x_UART_FCR_RX_FIFO_TRIG_SHIFT   (6)
+
+		/** Enhanced feature register */
+		ioport32_t efr;
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_MASK   (0x3)
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT   (0)
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_MASK   (0x3)
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT   (2)
+
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_NONE   (0x0)
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X2   (0x1)
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X1   (0x2)
+#define AMDM37x_UART_EFR_SW_FLOW_CTRL_XBOTH   (0x3)
+
+#define AMDM37x_UART_EFR_ENH_FLAG   (1 << 4)
+#define AMDM37x_UART_EFR_SPEC_CHAR_FLAG   (1 << 5)
+#define AMDM37x_UART_EFR_AUTO_RTS_EN_FLAG   (1 << 6)
+#define AMDM37x_UART_EFR_AUTO_CTS_EN_FLAG   (1 << 7)
+	};
+
+	/** Line control register */
+	ioport32_t lcr;
+#define AMDM37x_UART_LCR_CHAR_LENGTH_MASK   (0x3)
+#define AMDM37x_UART_LCR_CHAR_LENGTH_SHIFT   (0)
+#define AMDM37x_UART_LCR_CHAR_LENGTH_5BITS   (0x0)
+#define AMDM37x_UART_LCR_CHAR_LENGTH_6BITS   (0x1)
+#define AMDM37x_UART_LCR_CHAR_LENGTH_7BITS   (0x2)
+#define AMDM37x_UART_LCR_CHAR_LENGTH_8BITS   (0x3)
+#define AMDM37x_UART_LCR_NB_STOP_FLAG   (1 << 2)
+#define AMDM37x_UART_LCR_PARITY_EN_FLAG   (1 << 3)
+#define AMDM37x_UART_LCR_PARITY_TYPE1_FLAG   (1 << 4)
+#define AMDM37x_UART_LCR_PARITY_TYPE2_FLAG   (1 << 5)
+#define AMDM37x_UART_LCR_BREAK_EN_FLAG   (1 << 6)
+#define AMDM37x_UART_LCR_DIV_EN_FLAG   (1 << 7)
+
+
+	union {
+		/** Modem control register */
+		ioport32_t mcr;
+#define AMDM37x_UART_MCR_DTR_FLAG   (1 << 0)
+#define AMDM37x_UART_MCR_RTS_FLAG   (1 << 1)
+#define AMDM37x_UART_MCR_RI_STS_CH_FLAG   (1 << 2)
+#define AMDM37x_UART_MCR_CD_STS_CH_FLAG   (1 << 3)
+#define AMDM37x_UART_MCR_LOOPBACK_EN_FLAG   (1 << 4)
+#define AMDM37x_UART_MCR_XON_EN_FLAG   (1 << 5)
+#define AMDM37x_UART_MCR_TCR_TLR_FLAG   (1 << 6)
+
+		/** UART: XON1 char, IRDA: ADDR1 address */
+		ioport32_t xon1_addr1;
+#define AMDM37x_UART_XON1_ADDR1_MASK   (0xff)
+	};
+
+	union {
+		/** Line status register */
+		const ioport32_t lsr;
+#define AMDM37x_UART_LSR_RX_FIFO_E_FLAG   (1 << 0)
+#define AMDM37x_UART_LSR_RX_OE_FLAG   (1 << 1)
+#define AMDM37x_UART_LSR_RX_PE_FLAG   (1 << 2)
+#define AMDM37x_UART_LSR_RX_FE_FLAG   (1 << 3)
+#define AMDM37x_UART_LSR_RX_BI_FLAG   (1 << 4)
+#define AMDM37x_UART_LSR_TX_FIFO_E_FLAG   (1 << 5)
+#define AMDM37x_UART_LSR_TX_SR_E_FLAG   (1 << 6)
+#define AMDM37x_UART_LSR_RX_FIFO_STS_FLAG   (1 << 7)
+
+#define AMDM37x_CIR_LSR_RX_FIFO_E_FLAG   (1 << 0)
+#define AMDM37x_CIR_LSR_RX_STOP_FLAG   (1 << 5)
+#define AMDM37x_CIR_LSR_THR_EMPTY_FLAG   (1 << 7)
+
+#define AMDM37x_IRDA_LSR_RX_FIFO_E_FLAG   (1 << 0)
+#define AMDM37x_IRDA_LSR_STS_FIFO_E_FLAG   (1 << 1)
+#define AMDM37x_IRDA_LSR_CRC_FLAG   (1 << 2)
+#define AMDM37x_IRDA_LSR_ABORT_FLAG   (1 << 3)
+#define AMDM37x_IRDA_LSR_FTL_FLAG   (1 << 4)
+#define AMDM37x_IRDA_LSR_RX_LAST_FLAG   (1 << 5)
+#define AMDM37x_IRDA_LSR_STS_FIFO_FULL_FLAG   (1 << 6)
+#define AMDM37x_IRDA_LSR_THR_EMPTY_FLAG   (1 << 7)
+
+		/** UART: XON2 char, IRDA: ADDR2 address */
+		ioport32_t xon2_addr2;
+	};
+
+	union {
+		/** Modem status register */
+		const ioport32_t msr;
+#define AMDM37x_UART_MSR_CTS_STS_FLAG   (1 << 0)
+#define AMDM37x_UART_MSR_DSR_STS_FLAG   (1 << 1)
+#define AMDM37x_UART_MSR_RI_STS_FLAG   (1 << 2)
+#define AMDM37x_UART_MSR_DCD_STS_FLAG   (1 << 3)
+#define AMDM37x_UART_MSR_NCTS_STS_FLAG   (1 << 4)
+#define AMDM37x_UART_MSR_NDSR_STS_FLAG   (1 << 5)
+#define AMDM37x_UART_MSR_NRI_STS_FLAG   (1 << 6)
+#define AMDM37x_UART_MSR_NCD_STS_FLAG   (1 << 7)
+
+		/** Transmission control register */
+		ioport32_t tcr;
+#define AMDM37x_UART_TCR_FIFO_TRIG_MASK   (0xf)
+#define AMDM37x_UART_TCR_FIFO_TRIG_HALT_SHIFT   (0)
+#define AMDM37x_UART_TCR_FIFO_TRIG_START_SHIFT   (4)
+
+		/** UART: XOFF1 char */
+		ioport32_t xoff1;
+#define AMDM37x_UART_XOFF1_MASK   (0xff)
+	};
+
+	union {
+		/* Scratchpad register, does nothing */
+		ioport32_t spr;
+#define AMDM37x_UART_SPR_MASK   (0xff)
+
+		/* Trigger level register */
+		ioport32_t tlr;
+#define AMDM37x_UART_TLR_LEVEL_MASK   (0xf)
+#define AMDM37x_UART_TLR_TX_FIFO_TRIG_SHIFT   (0)
+#define AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT   (4)
+
+		/** UART: XOFF2 char */
+		ioport32_t xoff2;
+#define AMDM37x_UART_XOFF2_MASK   (0xff)
+	};
+
+	/** Mode definition register. */
+	ioport32_t mdr1;
+#define AMDM37x_UART_MDR_MS_MASK   (0x7)
+#define AMDM37x_UART_MDR_MS_SHIFT   (0)
+#define AMDM37x_UART_MDR_MS_UART16   (0x0)
+#define AMDM37x_UART_MDR_MS_SIR   (0x1)
+#define AMDM37x_UART_MDR_MS_UART16_AUTO   (0x2)
+#define AMDM37x_UART_MDR_MS_UART13   (0x3)
+#define AMDM37x_UART_MDR_MS_MIR   (0x4)
+#define AMDM37x_UART_MDR_MS_FIR   (0x5)
+#define AMDM37x_UART_MDR_MS_CIR   (0x6)
+#define AMDM37x_UART_MDR_MS_DISABLE   (0x7)
+
+#define AMDM37x_UART_MDR_IR_SLEEP_FLAG   (1 << 3)
+#define AMDM37x_UART_MDR_SET_TXIR_FLAG   (1 << 4)
+#define AMDM37x_UART_MDR_SCT_FLAG   (1 << 5)
+#define AMDM37x_UART_MDR_SIP_FLAG   (1 << 6)
+#define AMDM37x_UART_MDR_FRAME_END_MODE_FLAG   (1 << 7)
+
+	/** Mode definition register */
+	ioport32_t mdr2;
+#define AMDM37x_UART_MDR_IRTX_UNDERRUN_FLAG   (1 << 0)
+#define AMDM37x_UART_MDR_STS_FIFO_TRIG_MASK   (0x3)
+#define AMDM37x_UART_MDR_STS_FIFO_TRIG_SHIFT   (1)
+#define AMDM37x_UART_MDR_PULSE_SHAPING_FLAG   (1 << 3)
+#define AMDM37x_UART_MDR_CIR_PULSE_MODE_MASK   (0x3)
+#define AMDM37x_UART_MDR_CIR_PULSE_MODE_SHIFT   (4)
+#define AMDM37x_UART_MDR_IRRXINVERT_FLAG   (1 << 6)
+
+
+	/* UART3 specific */
+	union {
+		/** Status FIFO line status register (IrDA only) */
+		const ioport32_t sflsr;
+#define AMDM37x_IRDA_SFLSR_CRC_ERROR_FLAG   (1 << 1)
+#define AMDM37x_IRDA_SFLSR_ABORT_FLAG   (1 << 2)
+#define AMDM37x_IRDA_SFLSR_FTL_FLAG   (1 << 3)
+#define AMDM37x_IRDA_SFLSR_OE_FLAG   (1 << 4)
+
+		/** Transmit frame length low (IrDA only) */
+		ioport32_t txfll;
+#define AMDM37x_UART_TXFLL_MASK   (0xff)
+	};
+
+	/* UART3 specific */
+	union {
+		/** Dummy register to restart TX or RX (IrDA only) */
+		const ioport32_t resume;
+		/** Transmit frame length high (IrDA only) */
+		ioport32_t txflh;
+#define AMDM37x_UART_TXFLH_MASK   (0xff)
+	};
+
+	/* UART3 specific */
+	union {
+		/** Status FIFO register low (IrDA only) */
+		const ioport32_t sfregl;
+#define AMDM37x_UART_SFREGL_MASK   (0xff)
+		/** Received frame length low (IrDA only) */
+		ioport32_t rxfll;
+#define AMDM37x_UART_RXFLL_MASK   (0xff)
+	};
+
+	/* UART3 specific */
+	union {
+		/** Status FIFO register high (IrDA only) */
+		const ioport32_t sfregh;
+#define AMDM37x_UART_SFREGH_MASK   (0xf)
+		/** Received frame length high (IrDA only) */
+		ioport32_t rxflh;
+#define AMDM37x_UART_RXFLH_MASK   (0xf)
+	};
+
+	union {
+		/** UART autobauding status register */
+		const ioport32_t uasr;
+#define AMDM37x_UART_UASR_SPEED_MASK   (0x1f)
+#define AMDM37x_UART_UASR_SPEED_SHIFT   (0)
+#define AMDM37x_UART_UASR_8BIT_CHAR_FLAG   (1 << 5)
+#define AMDM37x_UART_UASR_PARITY_MASK   (0x3)
+#define AMDM37x_UART_UASR_PARITY_SHIFT   (6)
+
+		/** BOF control register (IrDA only) */
+		ioport32_t blr; /* UART3 specific */
+#define AMDM37x_IRDA_BLR_XBOF_TYPE_FLAG   (1 << 6)
+#define AMDM37x_IRDA_BLR_STS_FIFO_RESET   (1 << 7)
+	};
+
+	/** Auxiliary control register (IrDA only) */
+	ioport32_t acreg; /* UART3 specific */
+#define AMDM37x_IRDA_ACREG_EOT_EN_FLAG   (1 << 0)
+#define AMDM37x_IRDA_ACREG_ABORT_EN_FLAG   (1 << 1)
+#define AMDM37x_IRDA_ACREG_SCTX_EN_FLAG   (1 << 2)
+#define AMDM37x_IRDA_ACREG_SEND_SIP_FLAG   (1 << 3)
+#define AMDM37x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG   (1 << 4)
+#define AMDM37x_IRDA_ACREG_DIS_IR_RX_FLAG   (1 << 5)
+#define AMDM37x_IRDA_ACREG_SD_MOD_FLAG   (1 << 6)
+#define AMDM37x_IRDA_ACREG_PULSE_TYPE_FLAG   (1 << 7)
+
+	/** Supplementary control register */
+	ioport32_t scr;
+#define AMDM37x_UART_SCR_DMA_MODE_CTL_FLAG   (1 << 0)
+#define AMDM37x_UART_SCR_DMA_MODE_MASK   (0x3)
+#define AMDM37x_UART_SCR_DMA_MODE_SHIFT   (1)
+#define AMDM37x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG   (1 << 3)
+#define AMDM37x_UART_SCR_RX_CTS_WU_EN_FLAG   (1 << 4)
+#define AMDM37x_UART_SCR_TX_TRIG_GRANU1_FLAG   (1 << 6)
+#define AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG   (1 << 7)
+
+	/** Supplementary status register */
+	const ioport32_t ssr;
+#define AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG   (1 << 0)
+#define AMDM37x_UART_SSR_RX_CTS_WU_STS_FLAG   (1 << 1)
+#define AMDM37x_UART_SSR_DMA_COUNTER_RESET_FLAG   (1 << 2)
+
+	/** BOF Length register (IrDA only)*/
+	ioport32_t eblr; /* UART3 specific */
+#define AMDM37x_IRDA_EBLR_DISABLED   (0x00)
+#define AMDM37x_IRDA_EBLR_RX_STOP_BITS(bits)   (bits & 0xff)
+
+	uint32_t padd0_;
+
+	/** Module version register */
+	const ioport32_t mvr;
+#define AMDM37x_UART_MVR_MINOR_MASK   (0xf)
+#define AMDM37x_UART_MVR_MINOR_SHIFT   (0)
+#define AMDM37x_UART_MVR_MAJOR_MASK   (0xf)
+#define AMDM37x_UART_MVR_MAJOR_SHIFT   (4)
+
+	/** System configuration register */
+	ioport32_t sysc;
+#define AMDM37x_UART_SYSC_AUTOIDLE_FLAG   (1 << 0)
+#define AMDM37x_UART_SYSC_SOFTRESET_FLAG   (1 << 1)
+#define AMDM37x_UART_SYSC_ENWAKEUP_FLAG   (1 << 2)
+#define AMDM37x_UART_SYSC_IDLE_MODE_MASK   (0x3)
+#define AMDM37x_UART_SYSC_IDLE_MODE_SHIFT   (3)
+#define AMDM37x_UART_SYSC_IDLE_MODE_FORCE   (0x0)
+#define AMDM37x_UART_SYSC_IDLE_MODE_NO   (0x1)
+#define AMDM37x_UART_SYSC_IDLE_MODE_SMART   (0x2)
+
+	/** System status register */
+	const ioport32_t syss;
+#define AMDM37x_UART_SYSS_RESETDONE_FLAG   (1 << 0)
+
+	/** Wake-up enable register */
+	ioport32_t wer;
+#define AMDM37x_UART_WER_CTS_ACTIVITY_FLAG  (1 << 0)
+#define AMDM37x_UART_WER_RI_ACTIVITY_FLAG  (1 << 2)
+#define AMDM37x_UART_WER_RX_ACTIVITY_FLAG  (1 << 4)
+#define AMDM37x_UART_WER_RHR_IRQ_FLAG  (1 << 5)
+#define AMDM37x_UART_WER_RLS_IRQ_FLAG  (1 << 6)
+#define AMDM37x_UART_WER_TX_WAKEUP_EN_FLAG  (1 << 7)
+
+	/** Carrier frequency prescaler */
+	ioport32_t cfps;	/* UART3 specific */
+#define AMDM37x_UART_CFPS_MASK   (0xff)
+
+	/** Number of bytes in RX fifo */
+	const ioport32_t rx_fifo_lvl;
+#define AMDM37x_UART_RX_FIFO_LVL_MASK   (0xff)
+
+	/** Number of bytes in TX fifo */
+	const ioport32_t tx_fifo_lvl;
+#define AMDM37x_UART_TX_FIFO_LVL_MASK   (0xff)
+
+	/** RX/TX empty interrupts */
+	ioport32_t ier2;
+#define AMDM37x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 0)
+#define AMDM37x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 1)
+
+	/** RX/TX empty status */
+	ioport32_t isr2;
+#define AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG  (1 << 0)
+#define AMDM37x_UART_ISR2_TX_FIFO_EMPTY_FLAG  (1 << 1)
+
+	uint32_t padd2_[3];
+
+	/** Mode definition register 3 */
+	ioport32_t mdr3;
+#define AMDM37x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG   (1 << 0)
+} amdm37x_uart_regs_t;
+
+#endif
+
+/**
+ * @}
+ */
Index: rnel/genarch/include/drivers/amdm37x_dispc/amdm37x_dispc.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x_dispc/amdm37x_dispc.h	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ 	(revision )
@@ -1,394 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AM/DM37x SDRAM Memory Scheduler.
- */
-
-#ifndef KERN_AMDM37x_DISPC_H_
-#define KERN_AMDM37x_DISPC_H_
-
-/* AMDM37x TRM p. 1813 */
-#define AMDM37x_DISPC_BASE_ADDRESS 0x48050400
-#define AMDM37x_DISPC_SIZE 1024
-
-#define __paddname(line) PADD32_ ## line
-#define _paddname(line) __paddname(line)
-#define PADD32(count) uint32_t _paddname(__LINE__)[count]
-
-#include <typedefs.h>
-
-typedef struct {
-	const ioport32_t revision;
-#define AMDM37X_DISPC_REVISION_MASK  0xff
-
-	PADD32(3);
-	ioport32_t sysconfig;
-#define AMDM37X_DISPC_SYSCONFIG_AUTOIDLE_FLAG  (1 << 0)
-#define AMDM37X_DISPC_SYSCONFIG_SOFTRESET_FLAG  (1 << 1)
-#define AMDM37X_DISPC_SYSCONFIG_ENWAKEUP_FLAG  (1 << 2)
-#define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_MASK  0x3
-#define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_SHIFT  3
-#define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_MASK  0x3
-#define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_SHIFT  8
-#define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_MASK  0x3
-#define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_SHIFT  12
-
-	const ioport32_t sysstatus;
-#define AMDM37X_DISPC_SYSSTATUS_RESETDONE_FLAG  (1 << 0)
-
-	ioport32_t irqstatus;
-	ioport32_t irqenable;
-#define AMDM37X_DISPC_IRQ_FRAMEDONE_FLAG  (1 << 0)
-#define AMDM37X_DISPC_IRQ_VSYNC_FLAG  (1 << 1)
-#define AMDM37X_DISPC_IRQ_EVSYNCEVEN_FLAG  (1 << 2)
-#define AMDM37X_DISPC_IRQ_EVSYNCODD_FLAG  (1 << 3)
-#define AMDM37X_DISPC_IRQ_ACBIASCOUNTSTATUS_FLAG  (1 << 4)
-#define AMDM37X_DISPC_IRQ_PROGRAMMEDLINENUMBER_FLAG  (1 << 5)
-#define AMDM37X_DISPC_IRQ_GFXFIFOUNDERFLOW_FLAG  (1 << 6)
-#define AMDM37X_DISPC_IRQ_GFXENDWINDOW_FLAG  (1 << 7)
-#define AMDM37X_DISPC_IRQ_PALETTEGAMMALOADING_FLAG  (1 << 8)
-#define AMDM37X_DISPC_IRQ_OPCERROR_FLAG  (1 << 9)
-#define AMDM37X_DISPC_IRQ_VID1FIFOUNDERFLOW_FLAG  (1 << 10)
-#define AMDM37X_DISPC_IRQ_VID1ENDWINDOW_FLAG  (1 << 11)
-#define AMDM37X_DISPC_IRQ_VID2FIFOUNDERFLOW_FLAG  (1 << 12)
-#define AMDM37X_DISPC_IRQ_VID2ENDWINDOW_FLAG  (1 << 13)
-#define AMDM37X_DISPC_IRQ_SYNCLOST_FLAG  (1 << 14)
-#define AMDM37X_DISPC_IRQ_SYNCLOSTDIGITAL_FLAG  (1 << 15)
-#define AMDM37X_DISPC_IRQ_WAKEUP_FLAG  (1 << 16)
-
-	PADD32(8);
-	ioport32_t control;
-#define AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG  (1 << 0)
-#define AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG  (1 << 1)
-#define AMDM37X_DISPC_CONTROL_MONOCOLOR_FLAG  (1 << 2)
-#define AMDM37X_DISPC_CONTROL_STNTFT_FLAG  (1 << 3)
-#define AMDM37X_DISPC_CONTROL_M8B_FLAG  (1 << 4)
-#define AMDM37X_DISPC_CONTROL_GOLCD_FLAG  (1 << 5)
-#define AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG  (1 << 6)
-#define AMDM37X_DISPC_CONTROL_STDITHERENABLE_FLAG  (1 << 7)
-#define AMDM37X_DISPC_CONTROL_TFTDATALINES_MASK  0x3
-#define AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT  8
-#define AMDM37X_DISPC_CONTROL_TFTDATALINES_12B  0
-#define AMDM37X_DISPC_CONTROL_TFTDATALINES_16B  1
-#define AMDM37X_DISPC_CONTROL_TFTDATALINES_18B  2
-#define AMDM37X_DISPC_CONTROL_TFTDATALINES_24B  3
-#define AMDM37X_DISPC_CONTROL_STALLMODE_FLAG  (1 << 11)
-#define AMDM37X_DISPC_CONTROL_OVERLAYOPTIMIZATION_FLAG  (1 << 12)
-#define AMDM37X_DISPC_CONTROL_GPIN0_FLAG  (1 << 13)
-#define AMDM37X_DISPC_CONTROL_GPIN1_FLAG  (1 << 14)
-#define AMDM37X_DISPC_CONTROL_GPOUT0_FLAG  (1 << 15)
-#define AMDM37X_DISPC_CONTROL_GPOUT1_FLAG  (1 << 16)
-#define AMDM37X_DISPC_CONTROL_HT_MASK  0x7
-#define AMDM37X_DISPC_CONTROL_HT_SHIFT  17
-#define AMDM37X_DISPC_CONTROL_TDMENABLE_FLAG  (1 << 20)
-#define AMDM37X_DISPC_CONTROL_TDMPARALLELMODE_MASK  0x3
-#define AMDM37X_DISPC_CONTROL_TDMPARELLELMODE_SHIFT  21
-#define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_MASK  0x3
-#define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_SHIFT  23
-#define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_MASK  0x3
-#define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_SHIFT  25
-#define AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG  (1 << 27)
-#define AMDM37X_DISPC_CONTROL_LCDENABLESIGNAL_FLAG  (1 << 28)
-#define AMDM37X_DISPC_CONTROL_KCDENABLEPOL_FLAG  (1 << 29)
-#define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK  0x3
-#define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT  30
-
-	ioport32_t config;
-#define AMDM37X_DISPC_CONFIG_PIXELGATED_FLAG  (1 << 0)
-#define AMDM37X_DISPC_CONFIG_LOADMODE_MASK  0x3
-#define AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT  1
-#define AMDM37X_DISPC_CONFIG_LOADMODE_PGDATAEVERYFRAME  0x0
-#define AMDM37X_DISPC_CONFIG_LOADMODE_PGUSER  0x1
-#define AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME  0x2
-#define AMDM37X_DISPC_CONFIG_LOADMODE_PGDFIRSTFRAME  0x3
-#define AMDM37X_DISPC_CONFIG_PALETTEGAMMATABLE_FLAG  (1 << 3)
-#define AMDM37X_DISPC_CONFIG_PIXELDATAGATED_FLAG  (1 << 4)
-#define AMDM37X_DISPC_CONFIG_PIXELCLOCKGATED_FLAG  (1 << 5)
-#define AMDM37X_DISPC_CONFIG_HSYNCGATED_FLAG  (1 << 6)
-#define AMDM37X_DISPC_CONFIG_VSYNCGATED_FLAG  (1 << 7)
-#define AMDM37X_DISPC_CONFIG_ACBIASGATED_FLAG  (1 << 8)
-#define AMDM37X_DISPC_CONFIG_FUNCGATED_FLAG  (1 << 9)
-#define AMDM37X_DISPC_CONFIG_TCKLCDENABLE_FLAG  (1 << 10)
-#define AMDM37X_DISPC_CONFIG_TCKLCDSELECTION_FLAG  (1 << 11)
-#define AMDM37X_DISPC_CONFIG_TCKDIGENABLE_FLAG  (1 << 12)
-#define AMDM37X_DISPC_CONFIG_TCKDIGSELECTION_FLAG  (1 << 13)
-#define AMDM37X_DISPC_CONFIG_FIFOMERGE_FLAG  (1 << 14)
-#define AMDM37X_DISPC_CONFIG_CPR_FLAG  (1 << 15)
-#define AMDM37X_DISPC_CONFIG_FIFOHANDCHECK_FLAG  (1 << 16)
-#define AMDM37X_DISPC_CONFIG_FIFOFILLING_FLAG  (1 << 17)
-#define AMDM37X_DISPC_CONFIG_LCDPALPHABLENDERENABLDE_FLAG  (1 << 18)
-#define AMDM37X_DISPC_CONFIG_TVALPHABLENDERENABLE_FLAG  (1 << 19)
-
-	PADD32(1);
-	ioport32_t default_color[2];
-	ioport32_t trans_color[2];
-#define AMDM37X_DISPC_COLOR_MASK 0xffffff
-
-	const ioport32_t line_status;
-	ioport32_t line_number;
-#define AMDM37X_DISPC_LINE_NUMBER_MASK 0x3ff
-
-	ioport32_t timing_h;
-#define AMDM37X_DISPC_TIMING_H_HSW_MASK 0xff
-#define AMDM37X_DISPC_TIMING_H_HSW_SHIFT 0
-#define AMDM37X_DISPC_TIMING_H_HFP_MASK 0xfff
-#define AMDM37X_DISPC_TIMING_H_HFP_SHIFT 8
-#define AMDM37X_DISPC_TIMING_H_HBP_MASK 0xfff
-#define AMDM37X_DISPC_TIMING_H_HBP_SHIFT 20
-
-	ioport32_t timing_v;
-#define AMDM37X_DISPC_TIMING_V_VSW_MASK 0xff
-#define AMDM37X_DISPC_TIMING_V_VSW_SHIFT 0
-#define AMDM37X_DISPC_TIMING_V_VFP_MASK 0xfff
-#define AMDM37X_DISPC_TIMING_V_VFP_SHIFT 8
-#define AMDM37X_DISPC_TIMING_V_VBP_MASK 0xfff
-#define AMDM37X_DISPC_TIMING_V_VBP_SHIFT 20
-
-	ioport32_t pol_freq;
-#define AMDM37X_DISPC_POL_FREQ_ACB_MASK  0xff
-#define AMDM37X_DISPC_POL_FREQ_ACB_SHIFT 0
-#define AMDM37X_DISPC_POL_FREQ_ACBI_MASK  0xf
-#define AMDM37X_DISPC_POL_FREQ_ACBI_SHIFT 8
-#define AMDM37X_DISPC_POL_FREQ_IVS_FLAG  (1 << 12)
-#define AMDM37X_DISPC_POL_FREQ_IHS_FLAG  (1 << 13)
-#define AMDM37X_DISPC_POL_FREQ_IPC_FLAG  (1 << 14)
-#define AMDM37X_DISPC_POL_FREQ_IEO_FLAG  (1 << 15)
-#define AMDM37X_DISPC_POL_FREQ_RF_FLAG  (1 << 16)
-#define AMDM37X_DISPC_POL_FREQ_ONOFF_FLAG  (1 << 17)
-
-	ioport32_t divisor;
-#define AMDM37X_DISPC_DIVISOR_PCD_MASK  0xff
-#define AMDM37X_DISPC_DIVISOR_PCD_SHIFT  0
-#define AMDM37X_DISPC_DIVISOR_LCD_MASK  0xff
-#define AMDM37X_DISPC_DIVISOR_LCD_SHIFT  16
-
-	ioport32_t global_alpha;
-#define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_MASK  0xff
-#define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_SHIFT  0
-#define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_MASK  0xff
-#define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_SHIFT  16
-
-	ioport32_t size_dig;
-	ioport32_t size_lcd;
-
-	struct {
-		ioport32_t ba[2];
-		ioport32_t position;
-#define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_MASK  0x7ff
-#define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_SHIFT  0
-#define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_MASK  0x7ff
-#define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_SHIFT  16
-
-		ioport32_t size;
-#define AMDM37X_DISPC_SIZE_WIDTH_MASK  0x7ff
-#define AMDM37X_DISPC_SIZE_WIDTH_SHIFT  0
-#define AMDM37X_DISPC_SIZE_HEIGHT_MASK  0x7ff
-#define AMDM37X_DISPC_SIZE_HEIGHT_SHIFT  16
-
-		PADD32(4);
-		ioport32_t attributes;
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG  (1 << 0)
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_MASK  0xf
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT  1
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB16  0x5
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16  0x6
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24_32  0x8
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24  0x9
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB  0xc
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBA  0xd
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX  0xe
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_REPLICATIONENABLE_FLAG  (1 << 5)
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_MASK  0x3
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_SHIFT  6
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT_FLAG  (1 << 8)
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE_FLAG  (1 << 9)
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXENDIANNES_FLAG  (1 << 10)
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXFIFOPRELOAD_FLAG  (1 << 11)
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_MASK  0x3
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_SHIFT  12
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXARBITRATION_FLAG  (1 << 14)
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXSELFREFRESH_FLAG  (1 << 15)
-#define AMDM37X_DISPC_GFX_ATTRIBUTES_PREMULTIALPHA_FLAG  (1 << 28)
-
-
-		ioport32_t fifo_threshold;
-		const ioport32_t fifo_size_status;
-		ioport32_t row_inc;
-		ioport32_t pixel_inc;
-		ioport32_t window_skip;
-		ioport32_t table_ba;
-	} gfx;
-
-	struct {
-		ioport32_t ba[2];
-		ioport32_t position;
-		ioport32_t size;
-		ioport32_t attributes;
-		ioport32_t fifo_threshold;
-		const ioport32_t fifo_size_status;
-		ioport32_t row_inc;
-		ioport32_t pixel_inc;
-		ioport32_t fir;
-		ioport32_t picture_size;
-		ioport32_t accui[2];
-		struct {
-			ioport32_t hi;
-			ioport32_t hvi;
-		} fir_coef[8];
-		ioport32_t conv_coef[5];
-		PADD32(2);
-	} vid[2];
-	/* 0x1d4 */
-	ioport32_t data_cycle[3];
-	/* 0x1e0 */
-	ioport32_t vid_fir_coef_v[8];
-	/* 0x200 */
-	PADD32(8);
-	/* 0x220 */
-	ioport32_t cpr_coef_r;
-	ioport32_t cpr_coef_g;
-	ioport32_t cpr_coef_b;
-	ioport32_t gfx_preload;
-
-	/* 0x230 */
-	ioport32_t vid_preload[2];
-
-} __attribute__((packed)) amdm37x_dispc_regs_t;
-
-
-static inline void amdm37x_dispc_setup_fb(amdm37x_dispc_regs_t *regs,
-    unsigned x, unsigned y, unsigned bpp, uintptr_t pa)
-{
-	ASSERT(regs);
-	/* Init sequence for dispc is in chapter 7.6.5.1.4 p. 1810,
-	 * no idea what parts of that work. */
-
-	/* Disable all interrupts */
-	regs->irqenable = 0;
-
-	/* Pixel format specifics*/
-	uint32_t attrib_pixel_format = 0;
-	uint32_t control_data_lanes = 0;
-	switch (bpp)
-	{
-	case 32:
-		attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX;
-		control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
-		break;
-	case 24:
-		attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24;
-		control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
-		break;
-	case 16:
-		attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16;
-		control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_16B;
-		break;
-	default:
-		ASSERT(false);
-	}
-
-	/* Prepare sizes */
-	const uint32_t size_reg =
-	    (((x - 1) & AMDM37X_DISPC_SIZE_WIDTH_MASK)
-	        << AMDM37X_DISPC_SIZE_WIDTH_SHIFT) |
-	    (((y - 1) & AMDM37X_DISPC_SIZE_HEIGHT_MASK)
-	        << AMDM37X_DISPC_SIZE_HEIGHT_SHIFT);
-
-	/* modes taken from u-boot, for 1024x768 */
-	// TODO replace magic values with actual correct values
-//	regs->timing_h = 0x1a4024c9;
-//	regs->timing_v = 0x02c00509;
-//	regs->pol_freq = 0x00007028;
-//	regs->divisor  = 0x00010001;
-
-	/* setup output */
-	regs->size_lcd = size_reg;
-	regs->size_dig = size_reg;
-
-	/* Nice blue default color */
-	regs->default_color[0] = 0x0000ff;
-	regs->default_color[1] = 0x0000ff;
-
-	/* Setup control register */
-	uint32_t control = 0 |
-		AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG |
-		(control_data_lanes << AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT) |
-		AMDM37X_DISPC_CONTROL_GPOUT0_FLAG |
-		AMDM37X_DISPC_CONTROL_GPOUT1_FLAG;
-	regs->control = control;
-
-	/* No gamma stuff only data */
-	uint32_t config = (AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME
-	            << AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT);
-	regs->config = config;
-
-
-	/* Set framebuffer base address */
-	regs->gfx.ba[0] = pa;
-	regs->gfx.ba[1] = pa;
-	regs->gfx.position = 0;
-
-	/* Setup fb size */
-	regs->gfx.size = size_reg;
-
-	/* Set pixel format */
-	uint32_t attribs = 0 |
-	    (attrib_pixel_format << AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT);
-	regs->gfx.attributes = attribs;
-
-	/* 0x03ff03c0 is the default */
-	regs->gfx.fifo_threshold = 0x03ff03c0;
-	/* This value should be stride - width, 1 means next pixel i.e.
-	 * stride == width */
-	regs->gfx.row_inc = 1;
-	/* number of bytes to next pixel in BPP multiples */
-	regs->gfx.pixel_inc = 1;
-	/* only used if video is played over fb */
-	regs->gfx.window_skip = 0;
-	/* Gamma and palette table */
-	regs->gfx.table_ba = 0;
-
-	/* enable frame buffer graphics */
-	regs->gfx.attributes |= AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG;
-	/* Update register values */
-	regs->control |= AMDM37X_DISPC_CONTROL_GOLCD_FLAG;
-	regs->control |= AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG;
-	/* Enable output */
-	regs->control |= AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG;
-	regs->control |= AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG;
-}
-
-
-#endif
-/**
- * @}
- */
Index: rnel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x_gpt/amdm37x_gpt.h	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ 	(revision )
@@ -1,255 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AM/DM37x MPU general purpose timer driver.
- */
-
-#ifndef KERN_AMDM37x_GPT_H_
-#define KERN_AMDM37x_GPT_H_
-
-#include <typedefs.h>
-#include <mm/km.h>
-
-/* AMDM37x TRM p. 2740 */
-#define AMDM37x_GPT1_BASE_ADDRESS  0x48318000
-#define AMDM37x_GPT1_SIZE  4096
-#define AMDM37x_GPT1_IRQ  37
-#define AMDM37x_GPT2_BASE_ADDRESS  0x49032000
-#define AMDM37x_GPT2_SIZE  4096
-#define AMDM37x_GPT2_IRQ  38
-#define AMDM37x_GPT3_BASE_ADDRESS  0x49034000
-#define AMDM37x_GPT3_SIZE  4096
-#define AMDM37x_GPT3_IRQ  39
-#define AMDM37x_GPT4_BASE_ADDRESS  0x49036000
-#define AMDM37x_GPT4_SIZE  4096
-#define AMDM37x_GPT4_IRQ  40
-#define AMDM37x_GPT5_BASE_ADDRESS  0x49038000
-#define AMDM37x_GPT5_SIZE  4096
-#define AMDM37x_GPT5_IRQ  41
-#define AMDM37x_GPT6_BASE_ADDRESS  0x4903a000
-#define AMDM37x_GPT6_SIZE  4096
-#define AMDM37x_GPT6_IRQ  42
-#define AMDM37x_GPT7_BASE_ADDRESS  0x4903c000
-#define AMDM37x_GPT7_SIZE  4096
-#define AMDM37x_GPT7_IRQ  43
-#define AMDM37x_GPT8_BASE_ADDRESS  0x4903e000
-#define AMDM37x_GPT8_SIZE  4096
-#define AMDM37x_GPT8_IRQ  44
-#define AMDM37x_GPT9_BASE_ADDRESS  0x49040000
-#define AMDM37x_GPT9_SIZE  4096
-#define AMDM37x_GPT9_IRQ  45
-#define AMDM37x_GPT10_BASE_ADDRESS  0x48086000
-#define AMDM37x_GPT10_SIZE  4096
-#define AMDM37x_GPT10_IRQ  46
-#define AMDM37x_GPT11_BASE_ADDRESS  0x48088000
-#define AMDM37x_GPT11_SIZE  4096
-#define AMDM37x_GPT11_IRQ  47
-
-
-/** GPT register map AMDM37x TRM p. 2740 */
-typedef struct {
-	/** IP revision */
-	const ioport32_t tidr;
-#define AMDM37x_GPT_TIDR_MINOR_MASK  (0xf)
-#define AMDM37x_GPT_TIDR_MINOR_SHIFT  (0)
-#define AMDM37x_GPT_TIDR_MAJOR_MASK  (0xf)
-#define AMDM37x_GPT_TIDR_MAJOR_SHIFT  (4)
-	uint32_t padd0_[3];
-
-	/** L4 Interface parameters */
-	ioport32_t tiocp_cfg;
-#define AMDM37x_GPT_TIOCP_CFG_AUTOIDLE_FLAG  (1 << 0)
-#define AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG  (1 << 1)
-#define AMDM37x_GPT_TIOCP_CFG_ENWAKEUP_FLAG  (1 << 2)
-#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_MASK  (0x3)
-#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_SHIFT  (3)
-#define AMDM37x_GPT_TIOCP_CFG_EMUFREE_FlAG  (1 << 5)
-#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_MASK  (0x3)
-#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_SHIFT (8)
-
-	/** Module status information, excluding irq */
-	const ioport32_t tistat;
-#define AMDM37x_GPT_TISTAT_RESET_DONE_FLAG  (1 << 0)
-
-	/** Interrupt status register */
-	ioport32_t tisr;
-#define AMDM37x_GPT_TISR_MAT_IRQ_FLAG  (1 << 0)
-#define AMDM37x_GPT_TISR_OVF_IRQ_FLAG  (1 << 1)
-#define AMDM37x_GPT_TISR_TCAR_IRQ_FLAG  (1 << 2)
-
-	/* Interrupt enable register */
-	ioport32_t tier;
-#define AMDM37x_GPT_TIER_MAT_IRQ_FLAG  (1 << 0)
-#define AMDM37x_GPT_TIER_OVF_IRQ_FLAG  (1 << 1)
-#define AMDM37x_GPT_TIER_TCAR_IRQ_FLAG  (1 << 2)
-
-	/** Wakeup enable register */
-	ioport32_t twer;
-#define AMDM37x_GPT_TWER_MAT_IRQ_FLAG  (1 << 0)
-#define AMDM37x_GPT_TWER_OVF_IRQ_FLAG  (1 << 1)
-#define AMDM37x_GPT_TWER_TCAR_IRQ_FLAG  (1 << 2)
-
-	/** Optional features control register */
-	ioport32_t tclr;
-#define AMDM37x_GPT_TCLR_ST_FLAG  (1 << 0)
-#define AMDM37x_GPT_TCLR_AR_FLAG  (1 << 1)
-#define AMDM37x_GPT_TCLR_PTV_MASK  (0x7)
-#define AMDM37x_GPT_TCLR_PTV_SHIFT  (2)
-#define AMDM37x_GPT_TCLR_PRE_FLAG  (1 << 5)
-#define AMDM37x_GPT_TCLR_CE_FLAG  (1 << 6)
-#define AMDM37x_GPT_TCLR_SCPWM  (1 << 7)
-#define AMDM37x_GPT_TCLR_TCM_MASK  (0x3)
-#define AMDM37x_GPT_TCLR_TCM_SHIFT  (8)
-#define AMDM37x_GPT_TCLR_TRG_MASK  (0x3)
-#define AMDM37x_GPT_TCLR_TRG_SHIFT (10)
-#define AMDM37x_GPT_TCLR_PT_FLAG  (1 << 12)
-#define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG  (1 << 13)
-#define AMDM37x_GPT_TCLR_GPO_CFG_FLAG  (1 << 14)
-
-	/** Value of timer counter */
-	ioport32_t tccr;
-
-	/** Timer load register */
-	ioport32_t tldr;
-
-	/** Timer trigger register */
-	ioport32_t ttgr;
-
-	/** Write-posted pending register */
-	const ioport32_t twps;
-#define AMDM37x_GPT_TWPS_TCLR_FLAG  (1 << 0)
-#define AMDM37x_GPT_TWPS_TCRR_FLAG  (1 << 1)
-#define AMDM37x_GPT_TWPS_TLDR_FLAG  (1 << 2)
-#define AMDM37x_GPT_TWPS_TTGR_FLAG  (1 << 3)
-#define AMDM37x_GPT_TWPS_TMAR_FLAG  (1 << 4)
-#define AMDM37x_GPT_TWPS_TPIR_FLAG  (1 << 5)
-#define AMDM37x_GPT_TWPS_TNIR_FLAG  (1 << 6)
-#define AMDM37x_GPT_TWPS_TCVR_FLAG  (1 << 7)
-#define AMDM37x_GPT_TWPS_TOCR_FLAG  (1 << 8)
-#define AMDM37x_GPT_TWPS_TOWR_FLAG  (1 << 9)
-
-	/** Timer match register */
-	ioport32_t tmar;
-
-	/** Capture value 1 register */
-	const ioport32_t tcar1;
-
-	/** Software interface control register */
-	ioport32_t tsicr;
-#define AMDM37x_GPT_TSICR_SFT_FLAG  (1 << 1)
-#define AMDM37x_GPT_TSICR_POSTED_FLAG  (1 << 2)
-
-	/** Capture value 2 register */
-	const ioport32_t tcar2;
-
-	/* GPT1,2,10 only (used for 1ms time period generation)*/
-
-	/** Positive increment register */
-	ioport32_t tpir;
-
-	/** Negative increment register */
-	ioport32_t tnir;
-
-	/** Counter value register */
-	ioport32_t tcvr;
-
-	/** Mask the tick interrupt for selected number of ticks */
-	ioport32_t tocr;
-
-	/** Number of masked overflow interrupts */
-	ioport32_t towr;
-} amdm37x_gpt_regs_t;
-
-typedef struct {
-	amdm37x_gpt_regs_t *regs;
-	bool special_available;
-} amdm37x_gpt_t;
-
-static inline void amdm37x_gpt_timer_ticks_init(
-    amdm37x_gpt_t* timer, uintptr_t ioregs, size_t iosize, unsigned hz)
-{
-	/* Set 32768 Hz clock as source */
-	// TODO find a nicer way to setup 32kHz clock source for timer1
-	// reg 0x48004C40 is CM_CLKSEL_WKUP see page 485 of the manual
-	ioport32_t *clksel = (void*) km_map(0x48004C40, 4, PAGE_NOT_CACHEABLE);
-	*clksel &= ~1;
-	km_unmap((uintptr_t)clksel, 4);
-
-	ASSERT(timer);
-	/* Map control register */
-	timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
-
-	/* Set autoreload */
-	timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG;
-
-	timer->special_available = (
-	    (ioregs == AMDM37x_GPT1_BASE_ADDRESS) ||
-	    (ioregs == AMDM37x_GPT2_BASE_ADDRESS) ||
-	    (ioregs == AMDM37x_GPT10_BASE_ADDRESS));
-	timer->regs->tldr = 0xffffffff - (32768 / hz) + 1;
-	timer->regs->tccr = 0xffffffff - (32768 / hz) + 1;
-	if (timer->special_available) {
-		/* Set values for according to formula (manual p. 2733) */
-		/* Use temporary variables for easier debugging */
-		const uint32_t tpir =
-		    ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz));
-		const uint32_t tnir =
-		    ((32768 / hz) * 1000000) - (32768000 * (1000 / hz));
-		timer->regs->tpir = tpir;
-		timer->regs->tnir = tnir;
-	}
-
-}
-
-static inline void amdm37x_gpt_timer_ticks_start(amdm37x_gpt_t* timer)
-{
-	ASSERT(timer);
-	ASSERT(timer->regs);
-	/* Enable overflow interrupt */
-	timer->regs->tier |= AMDM37x_GPT_TIER_OVF_IRQ_FLAG;
-	/* Start timer */
-	timer->regs->tclr |= AMDM37x_GPT_TCLR_ST_FLAG;
-}
-
-static inline void amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
-{
-	ASSERT(timer);
-	ASSERT(timer->regs);
-	/* Clear all pending interrupts */
-	timer->regs->tisr = timer->regs->tisr;
-}
-
-#endif
-
-/**
- * @}
- */
Index: rnel/genarch/include/drivers/amdm37x_irc/amdm37x_irc.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x_irc/amdm37x_irc.h	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ 	(revision )
@@ -1,206 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AM/DM37x MPU on-chip interrupt controller driver.
- */
-
-#ifndef KERN_AMDM37x_IRQC_H_
-#define KERN_AMDM37x_IRQC_H_
-
-/* AMDM37x TRM p. 1079 */
-#define AMDM37x_IRC_BASE_ADDRESS 0x48200000
-#define AMDM37x_IRC_SIZE 4096
-
-#define AMDM37x_IRC_IRQ_COUNT 96
-
-#include <typedefs.h>
-
-typedef struct {
-	const ioport32_t revision; /**< Revision */
-#define AMDM37x_IRC_REV_MASK (0xff)
-
-	uint8_t padd0_[12];
-
-	ioport32_t sysconfig; /**< SYS config */
-#define AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0)
-#define AMDM37x_IRC_SYSCONFIG_SOFTRESET_FLAG (1 << 1)
-
-	const ioport32_t sysstatus; /**< SYS status */
-#define AMDM37x_IRC_SYSSTATUS_RESET_DONE_FLAG (1 << 0)
-
-	uint8_t padd1_[40];
-
-	const ioport32_t sir_irq;   /**< Currently active irq number */
-#define AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK (0x7f)
-#define AMDM37x_IRC_SIR_IRQ_SPURIOUSIRQFLAG_MASK (0xfffffff8)
-
-	const ioport32_t sir_fiq;
-#define AMDM37x_IRC_SIR_FIQ_ACTIVEIRQ_MASK (0x7f)
-#define AMDM37x_IRC_SIR_FIQ_SPURIOUSIRQFLAG_MASK (0xfffffff8)
-
-	ioport32_t control;   /**< New interrupt agreement. */
-#define AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG (1 << 0)
-#define AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG (1 << 1)
-
-	ioport32_t protection;  /**< Protect other registers. */
-#define AMDM37x_IRC_PROTECTION_PROETCTION_FLAG (1 << 0)
-
-	ioport32_t idle;   /**< Idle and autogating */
-#define AMDM37x_IRC_IDLE_FUNCIDLE_FLAG (1 << 0)
-#define AMDM37x_IRC_IDLE_TURBO_FLAG (1 << 1)
-
-	uint8_t padd2_[12];
-
-	ioport32_t irq_priority; /**< Active IRQ priority */
-#define AMDM37x_IRC_IRQ_PRIORITY_IRQPRIORITY_MASK (0x7f)
-#define AMDM37x_IRC_IRQ_PRIORITY_SPURIOUSIRQFLAG_MASK (0xfffffff8)
-
-	ioport32_t fiq_priority; /**< Active FIQ priority */
-#define AMDM37x_IRC_FIQ_PRIORITY_FIQPRIORITY_MASK (0x7f)
-#define AMDM37x_IRC_FIQ_PRIORITY_SPURIOUSFIQFLAG_MASK (0xfffffff8)
-
-	ioport32_t threshold; /**< Priority threshold */
-#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_MASK (0xff)
-#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_ENABLED (0x00)
-#define AMDM37x_IRC_THRESHOLD_PRIORITYTHRESHOLD_DISABLED (0xff)
-
-	uint8_t padd3__[20];
-
-	struct {
-		const ioport32_t itr;   /**< Interrupt input status before masking */
-		ioport32_t mir;   /**< Interrupt mask */
-		ioport32_t mir_clear; /**< Clear mir mask bits */
-		ioport32_t mir_set;   /**< Set mir mask bits */
-		ioport32_t isr_set;   /**< Set software interrupt bits */
-		ioport32_t isr_clear; /**< Clear software interrupt bits */
-		const ioport32_t pending_irq; /**< IRQ status after masking */
-		const ioport32_t pending_fiq; /**< FIQ status after masking */
-	} interrupts[3];
-
-	uint8_t padd4_[32];
-
-	ioport32_t ilr[96];   /**< FIQ/IRQ steering */
-#define AMDM37x_IRC_ILR_FIQNIRQ (1 << 0)
-#define AMDM37x_IRC_ILR_PRIORITY_MASK (0x3f)
-#define AMDM37x_IRC_ILR_PRIORITY_SHIFT (2)
-
-} amdm37x_irc_regs_t;
-
-static inline void amdm37x_irc_dump(amdm37x_irc_regs_t *regs)
-{
-#define DUMP_REG(name) \
-	printf("%s %p(%x).\n", #name, &regs->name, regs->name);
-
-	DUMP_REG(revision);
-	DUMP_REG(sysconfig);
-	DUMP_REG(sysstatus);
-	DUMP_REG(sir_irq);
-	DUMP_REG(sir_fiq);
-	DUMP_REG(control);
-	DUMP_REG(protection);
-	DUMP_REG(idle);
-	DUMP_REG(irq_priority);
-	DUMP_REG(fiq_priority);
-	DUMP_REG(threshold);
-
-	for (int i = 0; i < 3; ++i) {
-		DUMP_REG(interrupts[i].itr);
-		DUMP_REG(interrupts[i].mir);
-		DUMP_REG(interrupts[i].isr_set);
-		DUMP_REG(interrupts[i].pending_irq);
-		DUMP_REG(interrupts[i].pending_fiq);
-	}
-	for (int i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) {
-		DUMP_REG(ilr[i]);
-	}
-
-#undef DUMP_REG
-}
-
-static inline void amdm37x_irc_init(amdm37x_irc_regs_t *regs)
-{
-	/* AMDM37x TRM sec 12.5.1 p. 2425 */
-	/* Program system config register */
-	//TODO enable this when you know the meaning
-	//regs->sysconfig |= AMDM37x_IRC_SYSCONFIG_AUTOIDLE_FLAG;
-
-	/* Program idle register */
-	//TODO enable this when you know the meaning
-	//regs->sysconfig |= AMDM37x_IRC_IDLE_TURBO_FLAG;
-
-	/* Program ilr[m] assign priority, decide fiq */
-	for (unsigned i = 0; i < AMDM37x_IRC_IRQ_COUNT; ++i) {
-		regs->ilr[i] = 0; /* highest prio(default) route to irq */
-	}
-
-	/* Disable all interrupts */
-	regs->interrupts[0].mir_set = 0xffffffff;
-	regs->interrupts[1].mir_set = 0xffffffff;
-	regs->interrupts[2].mir_set = 0xffffffff;
-}
-
-static inline unsigned amdm37x_irc_inum_get(amdm37x_irc_regs_t *regs)
-{
-	return regs->sir_irq & AMDM37x_IRC_SIR_IRQ_ACTIVEIRQ_MASK;
-}
-
-static inline void amdm37x_irc_irq_ack(amdm37x_irc_regs_t *regs)
-{
-	regs->control = AMDM37x_IRC_CONTROL_NEWIRQAGR_FLAG;
-}
-
-static inline void amdm37x_irc_fiq_ack(amdm37x_irc_regs_t *regs)
-{
-	regs->control = AMDM37x_IRC_CONTROL_NEWFIQAGR_FLAG;
-}
-
-static inline void amdm37x_irc_enable(amdm37x_irc_regs_t *regs, unsigned inum)
-{
-	ASSERT(inum < AMDM37x_IRC_IRQ_COUNT);
-	const unsigned set = inum / 32;
-	const unsigned pos = inum % 32;
-	regs->interrupts[set].mir_clear = (1 << pos);
-}
-
-static inline void amdm37x_irc_disable(amdm37x_irc_regs_t *regs, unsigned inum)
-{
-	ASSERT(inum < AMDM37x_IRC_IRQ_COUNT);
-	const unsigned set = inum / 32;
-	const unsigned pos = inum % 32;
-	regs->interrupts[set].mir_set = (1 << pos);
-}
-
-#endif
-
-/**
- * @}
- */
Index: rnel/genarch/include/drivers/amdm37x_uart/amdm37x_uart.h
===================================================================
--- kernel/genarch/include/drivers/amdm37x_uart/amdm37x_uart.h	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ 	(revision )
@@ -1,459 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AMDM37x on-chip interrupt controller driver.
- */
-
-#ifndef KERN_AMDM37x_UART_H_
-#define KERN_AMDM37x_UART_H_
-
-#include <typedefs.h>
-#include <console/chardev.h>
-#include <ddi/irq.h>
-
-/* AMDM37x TRM p. 2950 */
-#define AMDM37x_UART1_BASE_ADDRESS   0x4806a000
-#define AMDM37x_UART1_SIZE   1024
-#define AMDM37x_UART1_IRQ   72 /* AMDM37x TRM p. 2418 */
-
-#define AMDM37x_UART2_BASE_ADDRESS   0x4806b000
-#define AMDM37x_UART2_SIZE   1024
-#define AMDM37x_UART2_IRQ   73 /* AMDM37x TRM p. 2418 */
-
-#define AMDM37x_UART3_BASE_ADDRESS   0x49020000
-#define AMDM37x_UART3_SIZE   1024
-#define AMDM37x_UART3_IRQ   74 /* AMDM37x TRM p. 2418 */
-
-#define AMDM37x_UART4_BASE_ADDRESS   0x49042000
-#define AMDM37x_UART4_SIZE   1024
-#define AMDM37x_UART4_IRQ   80 /* AMDM37x TRM p. 2418 */
-
-typedef struct {
-	union {
-		/** Stores lower part of the 14-bit baud divisor */
-		ioport32_t dll;
-#define AMDM37x_UART_DLL_MASK   (0xff)
-
-		/** Receive holding register */
-		const ioport32_t rhr;
-#define AMDM37x_UART_RHR_MASK   (0xff)
-
-		/** Transmit holding register */
-		ioport32_t thr;
-#define AMDM37x_UART_THR_MASK   (0xff)
-	};
-
-	union {
-		/** Stores higher part of the 14-bit baud divisor */
-		ioport32_t dlh;
-#define AMDM37x_UART_DLH_MASK   (0x1f)
-
-		/** Interrupt enable registers */
-		ioport32_t ier;
-#define AMDM37x_UART_IER_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_UART_IER_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_UART_IER_LINE_STS_IRQ_FLAG   (1 << 2)
-#define AMDM37x_UART_IER_MODEM_STS_IRQ_FLAG   (1 << 3)
-#define AMDM37x_UART_IER_SLEEP_MODE_FLAG   (1 << 4)
-#define AMDM37x_UART_IER_XOFF_IRQ_FLAG   (1 << 5)
-#define AMDM37x_UART_IER_RTS_IRQ_FLAG   (1 << 6)
-#define AMDM37x_UART_IER_CTS_IRQ_FLAG   (1 << 7)
-
-#define AMDM37x_CIR_IER_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_CIR_IER_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_CIR_IER_RX_STOP_IRQ_FLAG   (1 << 2)
-#define AMDM37x_CIR_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
-#define AMDM37x_CIR_IER_TX_STS_IRQ_FLAG   (1 << 5)
-
-#define AMDM37x_IRDA_IER_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_IRDA_IER_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG   (1 << 2)
-#define AMDM37x_IRDA_IER_RX_OVERRUN_IRQ_FLAG   (1 << 3)
-#define AMDM37x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG   (1 << 4)
-#define AMDM37x_IRDA_IER_TX_STS_IRQ_FLAG   (1 << 5)
-#define AMDM37x_IRDA_IER_LINE_STS_IRQ_FLAG   (1 << 6)
-#define AMDM37x_IRDA_IER_EOF_IRQ_FLAG   (1 << 7)
-	};
-
-	union {
-		/** Interrupt identification register */
-		const ioport32_t iir;
-#define AMDM37x_UART_IIR_IRQ_PENDING_FLAG   (1 << 0)
-#define AMDM37x_UART_IIR_TYPE_MASK   (0x1f)
-#define AMDM37x_UART_IIR_TYPE_SHIFT   (1)
-#define AMDM37x_UART_IIR_FCR_MASK   (0x3)
-#define AMDM37x_UART_IIR_FCR_SHIFT   (6)
-
-#define AMDM37x_CIR_IIR_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_CIR_IIR_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_CIR_IIR_RX_STOP_IRQ_FLAG   (1 << 2)
-#define AMDM37x_CIR_IIR_RX_OE_IRQ_FLAG   (1 << 3)
-#define AMDM37x_CIR_IIR_TX_STS_IRQ_FLAG   (1 << 5)
-
-#define AMDM37x_IRDA_IIR_RHR_IRQ_FLAG   (1 << 0)
-#define AMDM37x_IRDA_IIR_THR_IRQ_FLAG   (1 << 1)
-#define AMDM37x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG   (1 << 2)
-#define AMDM37x_IRDA_IIR_RX_OE_IRQ_FLAG   (1 << 3)
-#define AMDM37x_IRDA_IIR_STS_FIFO_IRQ_FLAG   (1 << 4)
-#define AMDM37x_IRDA_IIR_TX_STS_IRQ_FLAG   (1 << 5)
-#define AMDM37x_IRDA_IIR_LINE_STS_IRQ_FLAG   (1 << 6)
-#define AMDM37x_IRDA_IIR_EOF_IRQ_FLAG   (1 << 7)
-
-		/** FIFO control register */
-		ioport32_t fcr;
-#define AMDM37x_UART_FCR_FIFO_EN_FLAG   (1 << 0)
-#define AMDM37x_UART_FCR_RX_FIFO_CLR_FLAG   (1 << 1)
-#define AMDM37x_UART_FCR_TX_FIFO_CLR_FLAG   (1 << 3)
-#define AMDM37x_UART_FCR_DMA_MODE_FLAG   (1 << 4)
-
-#define AMDM37x_UART_FCR_TX_FIFO_TRIG_MASK   (0x3)
-#define AMDM37x_UART_FCR_TX_FIFO_TRIG_SHIFT   (4)
-
-#define AMDM37x_UART_FCR_RX_FIFO_TRIG_MASK   (0x3)
-#define AMDM37x_UART_FCR_RX_FIFO_TRIG_SHIFT   (6)
-
-		/** Enhanced feature register */
-		ioport32_t efr;
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_MASK   (0x3)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT   (0)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_MASK   (0x3)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT   (2)
-
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_NONE   (0x0)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X2   (0x1)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_X1   (0x2)
-#define AMDM37x_UART_EFR_SW_FLOW_CTRL_XBOTH   (0x3)
-
-#define AMDM37x_UART_EFR_ENH_FLAG   (1 << 4)
-#define AMDM37x_UART_EFR_SPEC_CHAR_FLAG   (1 << 5)
-#define AMDM37x_UART_EFR_AUTO_RTS_EN_FLAG   (1 << 6)
-#define AMDM37x_UART_EFR_AUTO_CTS_EN_FLAG   (1 << 7)
-	};
-
-	/** Line control register */
-	ioport32_t lcr;
-#define AMDM37x_UART_LCR_CHAR_LENGTH_MASK   (0x3)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_SHIFT   (0)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_5BITS   (0x0)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_6BITS   (0x1)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_7BITS   (0x2)
-#define AMDM37x_UART_LCR_CHAR_LENGTH_8BITS   (0x3)
-#define AMDM37x_UART_LCR_NB_STOP_FLAG   (1 << 2)
-#define AMDM37x_UART_LCR_PARITY_EN_FLAG   (1 << 3)
-#define AMDM37x_UART_LCR_PARITY_TYPE1_FLAG   (1 << 4)
-#define AMDM37x_UART_LCR_PARITY_TYPE2_FLAG   (1 << 5)
-#define AMDM37x_UART_LCR_BREAK_EN_FLAG   (1 << 6)
-#define AMDM37x_UART_LCR_DIV_EN_FLAG   (1 << 7)
-
-
-	union {
-		/** Modem control register */
-		ioport32_t mcr;
-#define AMDM37x_UART_MCR_DTR_FLAG   (1 << 0)
-#define AMDM37x_UART_MCR_RTS_FLAG   (1 << 1)
-#define AMDM37x_UART_MCR_RI_STS_CH_FLAG   (1 << 2)
-#define AMDM37x_UART_MCR_CD_STS_CH_FLAG   (1 << 3)
-#define AMDM37x_UART_MCR_LOOPBACK_EN_FLAG   (1 << 4)
-#define AMDM37x_UART_MCR_XON_EN_FLAG   (1 << 5)
-#define AMDM37x_UART_MCR_TCR_TLR_FLAG   (1 << 6)
-
-		/** UART: XON1 char, IRDA: ADDR1 address */
-		ioport32_t xon1_addr1;
-#define AMDM37x_UART_XON1_ADDR1_MASK   (0xff)
-	};
-
-	union {
-		/** Line status register */
-		const ioport32_t lsr;
-#define AMDM37x_UART_LSR_RX_FIFO_E_FLAG   (1 << 0)
-#define AMDM37x_UART_LSR_RX_OE_FLAG   (1 << 1)
-#define AMDM37x_UART_LSR_RX_PE_FLAG   (1 << 2)
-#define AMDM37x_UART_LSR_RX_FE_FLAG   (1 << 3)
-#define AMDM37x_UART_LSR_RX_BI_FLAG   (1 << 4)
-#define AMDM37x_UART_LSR_TX_FIFO_E_FLAG   (1 << 5)
-#define AMDM37x_UART_LSR_TX_SR_E_FLAG   (1 << 6)
-#define AMDM37x_UART_LSR_RX_FIFO_STS_FLAG   (1 << 7)
-
-#define AMDM37x_CIR_LSR_RX_FIFO_E_FLAG   (1 << 0)
-#define AMDM37x_CIR_LSR_RX_STOP_FLAG   (1 << 5)
-#define AMDM37x_CIR_LSR_THR_EMPTY_FLAG   (1 << 7)
-
-#define AMDM37x_IRDA_LSR_RX_FIFO_E_FLAG   (1 << 0)
-#define AMDM37x_IRDA_LSR_STS_FIFO_E_FLAG   (1 << 1)
-#define AMDM37x_IRDA_LSR_CRC_FLAG   (1 << 2)
-#define AMDM37x_IRDA_LSR_ABORT_FLAG   (1 << 3)
-#define AMDM37x_IRDA_LSR_FTL_FLAG   (1 << 4)
-#define AMDM37x_IRDA_LSR_RX_LAST_FLAG   (1 << 5)
-#define AMDM37x_IRDA_LSR_STS_FIFO_FULL_FLAG   (1 << 6)
-#define AMDM37x_IRDA_LSR_THR_EMPTY_FLAG   (1 << 7)
-
-		/** UART: XON2 char, IRDA: ADDR2 address */
-		ioport32_t xon2_addr2;
-	};
-
-	union {
-		/** Modem status register */
-		const ioport32_t msr;
-#define AMDM37x_UART_MSR_CTS_STS_FLAG   (1 << 0)
-#define AMDM37x_UART_MSR_DSR_STS_FLAG   (1 << 1)
-#define AMDM37x_UART_MSR_RI_STS_FLAG   (1 << 2)
-#define AMDM37x_UART_MSR_DCD_STS_FLAG   (1 << 3)
-#define AMDM37x_UART_MSR_NCTS_STS_FLAG   (1 << 4)
-#define AMDM37x_UART_MSR_NDSR_STS_FLAG   (1 << 5)
-#define AMDM37x_UART_MSR_NRI_STS_FLAG   (1 << 6)
-#define AMDM37x_UART_MSR_NCD_STS_FLAG   (1 << 7)
-
-		/** Transmission control register */
-		ioport32_t tcr;
-#define AMDM37x_UART_TCR_FIFO_TRIG_MASK   (0xf)
-#define AMDM37x_UART_TCR_FIFO_TRIG_HALT_SHIFT   (0)
-#define AMDM37x_UART_TCR_FIFO_TRIG_START_SHIFT   (4)
-
-		/** UART: XOFF1 char */
-		ioport32_t xoff1;
-#define AMDM37x_UART_XOFF1_MASK   (0xff)
-	};
-
-	union {
-		/* Scratchpad register, does nothing */
-		ioport32_t spr;
-#define AMDM37x_UART_SPR_MASK   (0xff)
-
-		/* Trigger level register */
-		ioport32_t tlr;
-#define AMDM37x_UART_TLR_LEVEL_MASK   (0xf)
-#define AMDM37x_UART_TLR_TX_FIFO_TRIG_SHIFT   (0)
-#define AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT   (4)
-
-		/** UART: XOFF2 char */
-		ioport32_t xoff2;
-#define AMDM37x_UART_XOFF2_MASK   (0xff)
-	};
-
-	/** Mode definition register. */
-	ioport32_t mdr1;
-#define AMDM37x_UART_MDR_MS_MASK   (0x7)
-#define AMDM37x_UART_MDR_MS_SHIFT   (0)
-#define AMDM37x_UART_MDR_MS_UART16   (0x0)
-#define AMDM37x_UART_MDR_MS_SIR   (0x1)
-#define AMDM37x_UART_MDR_MS_UART16_AUTO   (0x2)
-#define AMDM37x_UART_MDR_MS_UART13   (0x3)
-#define AMDM37x_UART_MDR_MS_MIR   (0x4)
-#define AMDM37x_UART_MDR_MS_FIR   (0x5)
-#define AMDM37x_UART_MDR_MS_CIR   (0x6)
-#define AMDM37x_UART_MDR_MS_DISABLE   (0x7)
-
-#define AMDM37x_UART_MDR_IR_SLEEP_FLAG   (1 << 3)
-#define AMDM37x_UART_MDR_SET_TXIR_FLAG   (1 << 4)
-#define AMDM37x_UART_MDR_SCT_FLAG   (1 << 5)
-#define AMDM37x_UART_MDR_SIP_FLAG   (1 << 6)
-#define AMDM37x_UART_MDR_FRAME_END_MODE_FLAG   (1 << 7)
-
-	/** Mode definition register */
-	ioport32_t mdr2;
-#define AMDM37x_UART_MDR_IRTX_UNDERRUN_FLAG   (1 << 0)
-#define AMDM37x_UART_MDR_STS_FIFO_TRIG_MASK   (0x3)
-#define AMDM37x_UART_MDR_STS_FIFO_TRIG_SHIFT   (1)
-#define AMDM37x_UART_MDR_PULSE_SHAPING_FLAG   (1 << 3)
-#define AMDM37x_UART_MDR_CIR_PULSE_MODE_MASK   (0x3)
-#define AMDM37x_UART_MDR_CIR_PULSE_MODE_SHIFT   (4)
-#define AMDM37x_UART_MDR_IRRXINVERT_FLAG   (1 << 6)
-
-
-	/* UART3 specific */
-	union {
-		/** Status FIFO line status register (IrDA only) */
-		const ioport32_t sflsr;
-#define AMDM37x_IRDA_SFLSR_CRC_ERROR_FLAG   (1 << 1)
-#define AMDM37x_IRDA_SFLSR_ABORT_FLAG   (1 << 2)
-#define AMDM37x_IRDA_SFLSR_FTL_FLAG   (1 << 3)
-#define AMDM37x_IRDA_SFLSR_OE_FLAG   (1 << 4)
-
-		/** Transmit frame length low (IrDA only) */
-		ioport32_t txfll;
-#define AMDM37x_UART_TXFLL_MASK   (0xff)
-	};
-
-	/* UART3 specific */
-	union {
-		/** Dummy register to restart TX or RX (IrDA only) */
-		const ioport32_t resume;
-		/** Transmit frame length high (IrDA only) */
-		ioport32_t txflh;
-#define AMDM37x_UART_TXFLH_MASK   (0xff)
-	};
-
-	/* UART3 specific */
-	union {
-		/** Status FIFO register low (IrDA only) */
-		const ioport32_t sfregl;
-#define AMDM37x_UART_SFREGL_MASK   (0xff)
-		/** Received frame length low (IrDA only) */
-		ioport32_t rxfll;
-#define AMDM37x_UART_RXFLL_MASK   (0xff)
-	};
-
-	/* UART3 specific */
-	union {
-		/** Status FIFO register high (IrDA only) */
-		const ioport32_t sfregh;
-#define AMDM37x_UART_SFREGH_MASK   (0xf)
-		/** Received frame length high (IrDA only) */
-		ioport32_t rxflh;
-#define AMDM37x_UART_RXFLH_MASK   (0xf)
-	};
-
-	union {
-		/** UART autobauding status register */
-		const ioport32_t uasr;
-#define AMDM37x_UART_UASR_SPEED_MASK   (0x1f)
-#define AMDM37x_UART_UASR_SPEED_SHIFT   (0)
-#define AMDM37x_UART_UASR_8BIT_CHAR_FLAG   (1 << 5)
-#define AMDM37x_UART_UASR_PARITY_MASK   (0x3)
-#define AMDM37x_UART_UASR_PARITY_SHIFT   (6)
-
-		/** BOF control register (IrDA only) */
-		ioport32_t blr; /* UART3 sepcific */
-#define AMDM37x_IRDA_BLR_XBOF_TYPE_FLAG   (1 << 6)
-#define AMDM37x_IRDA_BLR_STS_FIFO_RESET   (1 << 7)
-	};
-
-	/** Auxiliary control register (IrDA only) */
-	ioport32_t acreg; /* UART3 specific */
-#define AMDM37x_IRDA_ACREG_EOT_EN_FLAG   (1 << 0)
-#define AMDM37x_IRDA_ACREG_ABORT_EN_FLAG   (1 << 1)
-#define AMDM37x_IRDA_ACREG_SCTX_EN_FLAG   (1 << 2)
-#define AMDM37x_IRDA_ACREG_SEND_SIP_FLAG   (1 << 3)
-#define AMDM37x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG   (1 << 4)
-#define AMDM37x_IRDA_ACREG_DIS_IR_RX_FLAG   (1 << 5)
-#define AMDM37x_IRDA_ACREG_SD_MOD_FLAG   (1 << 6)
-#define AMDM37x_IRDA_ACREG_PULSE_TYPE_FLAG   (1 << 7)
-
-	/** Supplementary control register */
-	ioport32_t scr;
-#define AMDM37x_UART_SCR_DMA_MODE_CTL_FLAG   (1 << 0)
-#define AMDM37x_UART_SCR_DMA_MODE_MASK   (0x3)
-#define AMDM37x_UART_SCR_DMA_MODE_SHIFT   (1)
-#define AMDM37x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG   (1 << 3)
-#define AMDM37x_UART_SCR_RX_CTS_WU_EN_FLAG   (1 << 4)
-#define AMDM37x_UART_SCR_TX_TRIG_GRANU1_FLAG   (1 << 6)
-#define AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG   (1 << 7)
-
-	/** Supplementary status register */
-	const ioport32_t ssr;
-#define AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG   (1 << 0)
-#define AMDM37x_UART_SSR_RX_CTS_WU_STS_FLAG   (1 << 1)
-#define AMDM37x_UART_SSR_DMA_COUNTER_RESET_FLAG   (1 << 2)
-
-	/** BOF Length register (IrDA only)*/
-	ioport32_t eblr; /* UART3 specific */
-#define AMDM37x_IRDA_EBLR_DISABLED   (0x00)
-#define AMDM37x_IRDA_EBLR_RX_STOP_BITS(bits)   (bits & 0xff)
-
-	uint32_t padd0_;
-
-	/** Module version register */
-	const ioport32_t mvr;
-#define AMDM37x_UART_MVR_MINOR_MASK   (0xf)
-#define AMDM37x_UART_MVR_MINOR_SHIFT   (0)
-#define AMDM37x_UART_MVR_MAJOR_MASK   (0xf)
-#define AMDM37x_UART_MVR_MAJOR_SHIFT   (4)
-
-	/** System configuration register */
-	ioport32_t sysc;
-#define AMDM37x_UART_SYSC_AUTOIDLE_FLAG   (1 << 0)
-#define AMDM37x_UART_SYSC_SOFTRESET_FLAG   (1 << 1)
-#define AMDM37x_UART_SYSC_ENWAKEUP_FLAG   (1 << 2)
-#define AMDM37x_UART_SYSC_IDLE_MODE_MASK   (0x3)
-#define AMDM37x_UART_SYSC_IDLE_MODE_SHIFT   (3)
-#define AMDM37x_UART_SYSC_IDLE_MODE_FORCE   (0x0)
-#define AMDM37x_UART_SYSC_IDLE_MODE_NO   (0x1)
-#define AMDM37x_UART_SYSC_IDLE_MODE_SMART   (0x2)
-
-	/** System status register */
-	const ioport32_t syss;
-#define AMDM37x_UART_SYSS_RESETDONE_FLAG   (1 << 0)
-
-	/** Wake-up enable register */
-	ioport32_t wer;
-#define AMDM37x_UART_WER_CTS_ACTIVITY_FLAG  (1 << 0)
-#define AMDM37x_UART_WER_RI_ACTIVITY_FLAG  (1 << 2)
-#define AMDM37x_UART_WER_RX_ACTIVITY_FLAG  (1 << 4)
-#define AMDM37x_UART_WER_RHR_IRQ_FLAG  (1 << 5)
-#define AMDM37x_UART_WER_RLS_IRQ_FLAG  (1 << 6)
-#define AMDM37x_UART_WER_TX_WAKEUP_EN_FLAG  (1 << 7)
-
-	/** Carrier frequency prescaler */
-	ioport32_t cfps;	/* UART3 specific */
-#define AMDM37x_UART_CFPS_MASK   (0xff)
-
-	/** Number of bytes in RX fifo */
-	const ioport32_t rx_fifo_lvl;
-#define AMDM37x_UART_RX_FIFO_LVL_MASK   (0xff)
-
-	/** Number of bytes in TX fifo */
-	const ioport32_t tx_fifo_lvl;
-#define AMDM37x_UART_TX_FIFO_LVL_MASK   (0xff)
-
-	/** RX/TX empty interrupts */
-	ioport32_t ier2;
-#define AMDM37x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 0)
-#define AMDM37x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG  (1 << 1)
-
-	/** RX/TX empty status */
-	ioport32_t isr2;
-#define AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG  (1 << 0)
-#define AMDM37x_UART_ISR2_TX_FIFO_EMPTY_FLAG  (1 << 1)
-
-	uint32_t padd2_[3];
-
-	/** Mode definition register 3 */
-	ioport32_t mdr3;
-#define AMDM37x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG   (1 << 0)
-} amdm37x_uart_regs_t;
-
-typedef struct {
-	amdm37x_uart_regs_t *regs;
-	indev_t *indev;
-	outdev_t outdev;
-	irq_t irq;
-} amdm37x_uart_t;
-
-
-bool amdm37x_uart_init(amdm37x_uart_t *, inr_t, uintptr_t, size_t);
-void amdm37x_uart_input_wire(amdm37x_uart_t *, indev_t *);
-
-#endif
-
-/**
- * @}
- */
Index: kernel/genarch/src/drivers/am335x/timer.c
===================================================================
--- kernel/genarch/src/drivers/am335x/timer.c	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/src/drivers/am335x/timer.c	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2012 Maurizio Lombardi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x timer driver.
+ */
+
+#include <genarch/drivers/am335x/timer.h>
+#include <mm/km.h>
+#include <errno.h>
+
+
+typedef struct timer_regs_mmap {
+        uintptr_t base;
+        size_t size;
+} timer_regs_mmap_t;
+
+static const timer_regs_mmap_t regs_map[TIMERS_MAX] = {
+	{ .base = AM335x_DMTIMER0_BASE_ADDRESS, .size = AM335x_DMTIMER0_SIZE },
+	{0, 0},
+	{ .base = AM335x_DMTIMER2_BASE_ADDRESS, .size = AM335x_DMTIMER2_SIZE },
+	{ .base = AM335x_DMTIMER3_BASE_ADDRESS, .size = AM335x_DMTIMER3_SIZE },
+	{ .base = AM335x_DMTIMER4_BASE_ADDRESS, .size = AM335x_DMTIMER4_SIZE },
+	{ .base = AM335x_DMTIMER5_BASE_ADDRESS, .size = AM335x_DMTIMER5_SIZE },
+	{ .base = AM335x_DMTIMER6_BASE_ADDRESS, .size = AM335x_DMTIMER6_SIZE },
+	{ .base = AM335x_DMTIMER7_BASE_ADDRESS, .size = AM335x_DMTIMER7_SIZE },
+};
+
+void
+am335x_timer_init(am335x_timer_t *timer, am335x_timer_id_t id, unsigned hz)
+{
+	uintptr_t base_addr;
+	size_t size;
+
+	ASSERT(id < TIMERS_MAX);
+
+	if (id == DMTIMER1_1MS)
+		return; /* Not supported yet */
+
+	base_addr = regs_map[id].base;
+	size = regs_map[id].size;
+
+	timer->regs = (void *) km_map(base_addr, size, PAGE_NOT_CACHEABLE);
+	timer->id = id;
+
+	am335x_timer_regs_t *regs = timer->regs;
+
+	/* Stop the timer */
+	am335x_timer_stop(timer);
+
+	/* Perform a soft reset */
+	am335x_timer_reset(timer);
+
+	/* Disable the prescaler */
+	regs->tclr &= ~AM335x_TIMER_TCLR_PRE_FLAG;
+
+	/* Enable auto-reload mode */
+	regs->tclr |= AM335x_TIMER_TCLR_AR_FLAG;
+
+	/* XXX Here we assume that the timer clock source
+	 * is running at 32 Khz but this is not always the
+	 * case; DMTIMER[2 - 7] can use the internal system 24 Mhz
+	 * clock source or an external clock also.
+	 */
+	unsigned const count = 0xFFFFFFFE - 32768 / hz;
+	regs->tcrr = count;
+	regs->tldr = count;
+}
+
+void
+am335x_timer_intr_ack(am335x_timer_t *timer)
+{
+	/* Clear pending OVF event */
+	timer->regs->irqstatus |= AM335x_TIMER_IRQSTATUS_OVF_FLAG;
+}
+
+void
+am335x_timer_reset(am335x_timer_t *timer)
+{
+	/* Initiate soft reset */
+	timer->regs->tiocp_cfg |= AM335x_TIMER_TIOCPCFG_SOFTRESET_FLAG;
+	/* Wait until the reset is done */
+	while (timer->regs->tiocp_cfg & AM335x_TIMER_TIOCPCFG_SOFTRESET_FLAG);
+}
+
+void
+am335x_timer_stop(am335x_timer_t *timer)
+{
+	/* Disable the interrupt */
+	timer->regs->irqenable_clr |= AM335x_TIMER_IRQENABLE_CLR_OVF_FLAG;
+	/* Stop the timer */
+	timer->regs->tclr &= ~AM335x_TIMER_TCLR_ST_FLAG;
+}
+
+void
+am335x_timer_start(am335x_timer_t *timer)
+{
+	/* Enable the interrupt */
+	timer->regs->irqenable_set |= AM335x_TIMER_IRQENABLE_SET_OVF_FLAG;
+	/* Start the clock */
+	timer->regs->tclr |= AM335x_TIMER_TCLR_ST_FLAG;
+}
+
+/**
+ * @}
+ */
+
Index: kernel/genarch/src/drivers/am335x/uart.c
===================================================================
--- kernel/genarch/src/drivers/am335x/uart.c	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/src/drivers/am335x/uart.c	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AM335x on-chip uart serial line driver.
+ */
+
+#include <genarch/drivers/am335x/uart.h>
+#include <ddi/device.h>
+#include <str.h>
+#include <mm/km.h>
+
+static void am335x_uart_txb(am335x_uart_t *uart, uint8_t b)
+{
+	/* Wait for buffer */
+	while (uart->regs->ssr & AM335x_UART_SSR_TX_FIFO_FULL_FLAG);
+	/* Write to the outgoing fifo */
+	uart->regs->thr = b;
+}
+
+static void am335x_uart_putchar(outdev_t *dev, wchar_t ch)
+{
+	am335x_uart_t *uart = dev->data;
+	if (!ascii_check(ch)) {
+		am335x_uart_txb(uart, U_SPECIAL);
+	} else {
+		if (ch == '\n')
+			am335x_uart_txb(uart, '\r');
+		am335x_uart_txb(uart, ch);
+	}
+}
+
+static outdev_operations_t am335x_uart_ops = {
+	.redraw = NULL,
+	.write = am335x_uart_putchar,
+};
+
+static irq_ownership_t am335x_uart_claim(irq_t *irq)
+{
+	return IRQ_ACCEPT;
+}
+
+static void am335x_uart_handler(irq_t *irq)
+{
+	am335x_uart_t *uart = irq->instance;
+	while ((uart->regs->rx_fifo_lvl)) {
+		const uint8_t val = uart->regs->rhr;
+		if (uart->indev && val) {
+			indev_push_character(uart->indev, val);
+		}
+	}
+}
+
+bool am335x_uart_init(
+    am335x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size)
+{
+	ASSERT(uart);
+	uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE);
+
+	ASSERT(uart->regs);
+
+	/* Soft reset the port */
+	uart->regs->sysc = AM335x_UART_SYSC_SOFTRESET_FLAG;
+	while (!(uart->regs->syss & AM335x_UART_SYSS_RESETDONE_FLAG)) ;
+
+	/* Enable access to EFR register */
+	const uint8_t lcr = uart->regs->lcr; /* Save old value */
+	uart->regs->lcr = 0xbf;              /* Sets config mode B */
+
+	/* Enable access to TCL_TLR register */
+	const bool enhanced = uart->regs->efr & AM335x_UART_EFR_ENH_FLAG;
+	uart->regs->efr |= AM335x_UART_EFR_ENH_FLAG; /* Turn on enh. */
+	uart->regs->lcr = 0x80;              /* Config mode A */
+
+	/* Set default (val 0) triggers, disable DMA enable FIFOs */
+	const bool tcl_tlr = uart->regs->mcr & AM335x_UART_MCR_TCR_TLR_FLAG;
+	/* Enable access to tcr and tlr registers */
+	uart->regs->mcr |= AM335x_UART_MCR_TCR_TLR_FLAG;
+
+	/* Enable FIFOs */
+	uart->regs->fcr = AM335x_UART_FCR_FIFO_EN_FLAG;
+
+	/* Enable fine granularity for RX FIFO and set trigger level to 1,
+	 * TX FIFO, trigger level is irrelevant*/
+	uart->regs->lcr = 0xbf;              /* Sets config mode B */
+	uart->regs->scr = AM335x_UART_SCR_RX_TRIG_GRANU1_FLAG;
+	uart->regs->tlr = 1 << AM335x_UART_TLR_RX_FIFO_TRIG_SHIFT;
+
+	/* Restore enhanced */
+	if (!enhanced)
+		uart->regs->efr &= ~AM335x_UART_EFR_ENH_FLAG;
+
+	uart->regs->lcr = 0x80;              /* Config mode A */
+	/* Restore tcl_lcr access flag*/
+	if (!tcl_tlr)
+		uart->regs->mcr &= ~AM335x_UART_MCR_TCR_TLR_FLAG;
+
+	/* Restore lcr */
+	uart->regs->lcr = lcr;
+
+	/* Disable interrupts */
+	uart->regs->ier = 0;
+
+	/* Setup outdev */
+	outdev_initialize("am335x_uart_dev", &uart->outdev, &am335x_uart_ops);
+	uart->outdev.data = uart;
+
+	/* Initialize IRQ */
+	irq_initialize(&uart->irq);
+	uart->irq.devno = device_assign_devno();
+	uart->irq.inr = interrupt;
+	uart->irq.claim = am335x_uart_claim;
+	uart->irq.handler = am335x_uart_handler;
+	uart->irq.instance = uart;
+
+	return true;
+}
+
+void am335x_uart_input_wire(am335x_uart_t *uart, indev_t *indev)
+{
+	ASSERT(uart);
+	/* Set indev */
+	uart->indev = indev;
+	/* Register interrupt. */
+	irq_register(&uart->irq);
+	/* Enable interrupt on receive */
+	uart->regs->ier |= AM335x_UART_IER_RHR_IRQ_FLAG;
+}
+
+/**
+ * @}
+ */
+
Index: kernel/genarch/src/drivers/amdm37x/uart.c
===================================================================
--- kernel/genarch/src/drivers/amdm37x/uart.c	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
+++ kernel/genarch/src/drivers/amdm37x/uart.c	(revision 17cc8f4f7ca39b859a63ea05d5105d4300f84a27)
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** @addtogroup genarch
+ * @{
+ */
+/**
+ * @file
+ * @brief Texas Instruments AMDM37x on-chip uart serial line driver.
+ */
+
+#include <genarch/drivers/amdm37x/uart.h>
+#include <ddi/device.h>
+#include <str.h>
+#include <mm/km.h>
+
+static void amdm37x_uart_txb(amdm37x_uart_t *uart, uint8_t b)
+{
+	/* Wait for buffer */
+	while (uart->regs->ssr & AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG);
+	/* Write to the outgoing fifo */
+	uart->regs->thr = b;
+}
+
+static void amdm37x_uart_putchar(outdev_t *dev, wchar_t ch)
+{
+	amdm37x_uart_t *uart = dev->data;
+	if (!ascii_check(ch)) {
+		amdm37x_uart_txb(uart, U_SPECIAL);
+	} else {
+		if (ch == '\n')
+			amdm37x_uart_txb(uart, '\r');
+		amdm37x_uart_txb(uart, ch);
+	}
+}
+
+static outdev_operations_t amdm37x_uart_ops = {
+	.redraw = NULL,
+	.write = amdm37x_uart_putchar,
+};
+
+static irq_ownership_t amdm37x_uart_claim(irq_t *irq)
+{
+	return IRQ_ACCEPT;
+}
+
+static void amdm37x_uart_handler(irq_t *irq)
+{
+	amdm37x_uart_t *uart = irq->instance;
+	while ((uart->regs->rx_fifo_lvl)) {
+		const uint8_t val = uart->regs->rhr;
+		if (uart->indev && val) {
+			indev_push_character(uart->indev, val);
+		}
+	}
+}
+
+bool amdm37x_uart_init(
+    amdm37x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size)
+{
+	ASSERT(uart);
+	uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE);
+
+	ASSERT(uart->regs);
+
+	/* See TI OMAP35X TRM ch 17.5.1.1 p. 2732 for startup routine */
+#if 0
+	/* Soft reset the port */
+	uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG;
+	while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ;
+#endif
+
+	/* Enable access to EFR register */
+	const uint8_t lcr = uart->regs->lcr; /* Save old value */
+	uart->regs->lcr = 0xbf;              /* Sets config mode B */
+
+	/* Enable access to TCL_TLR register */
+	const bool enhanced = uart->regs->efr & AMDM37x_UART_EFR_ENH_FLAG;
+	uart->regs->efr |= AMDM37x_UART_EFR_ENH_FLAG; /* Turn on enh. */
+	uart->regs->lcr = 0x80;              /* Config mode A */
+
+	/* Set default (val 0) triggers, disable DMA enable FIFOs */
+	const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG;
+	/* Enable access to tcr and tlr registers */
+	uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG;
+
+	/* Enable FIFOs */
+	uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG;
+
+	/* Eneble fine granularity for RX FIFO and set trigger level to 1,
+	 * TX FIFO, trigger level is irelevant*/
+	uart->regs->lcr = 0xbf;              /* Sets config mode B */
+	uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG;
+	uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT;
+
+	/* Restore enhanced */
+	if (!enhanced)
+		uart->regs->efr &= ~AMDM37x_UART_EFR_ENH_FLAG;
+
+	uart->regs->lcr = 0x80;              /* Config mode A */
+	/* Restore tcl_lcr access flag*/
+	if (!tcl_tlr)
+		uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG;
+
+	/* Restore lcr */
+	uart->regs->lcr = lcr;
+
+	/* Disable interrupts */
+	uart->regs->ier = 0;
+
+	/* Setup outdev */
+	outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops);
+	uart->outdev.data = uart;
+
+	/* Initialize IRQ */
+	irq_initialize(&uart->irq);
+	uart->irq.devno = device_assign_devno();
+	uart->irq.inr = interrupt;
+	uart->irq.claim = amdm37x_uart_claim;
+	uart->irq.handler = amdm37x_uart_handler;
+	uart->irq.instance = uart;
+
+	return true;
+}
+
+void amdm37x_uart_input_wire(amdm37x_uart_t *uart, indev_t *indev)
+{
+	ASSERT(uart);
+	/* Set indev */
+	uart->indev = indev;
+	/* Register interrupt. */
+	irq_register(&uart->irq);
+	/* Enable interrupt on receive */
+	uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG;
+}
+
+/**
+ * @}
+ */
Index: rnel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c
===================================================================
--- kernel/genarch/src/drivers/amdm37x_uart/amdm37x_uart.c	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ 	(revision )
@@ -1,163 +1,0 @@
-/*
- * Copyright (c) 2012 Jan Vesely
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * - Redistributions of source code must retain the above copyright
- *   notice, this list of conditions and the following disclaimer.
- * - Redistributions in binary form must reproduce the above copyright
- *   notice, this list of conditions and the following disclaimer in the
- *   documentation and/or other materials provided with the distribution.
- * - The name of the author may not be used to endorse or promote products
- *   derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/** @addtogroup genarch
- * @{
- */
-/**
- * @file
- * @brief Texas Instruments AMDM37x on-chip uart serial line driver.
- */
-
-#include <genarch/drivers/amdm37x_uart/amdm37x_uart.h>
-#include <ddi/device.h>
-#include <str.h>
-#include <mm/km.h>
-
-static void amdm37x_uart_txb(amdm37x_uart_t *uart, uint8_t b)
-{
-	/* Wait for buffer */
-	while (uart->regs->ssr & AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG);
-	/* Write to the outgoing fifo */
-	uart->regs->thr = b;
-}
-
-static void amdm37x_uart_putchar(outdev_t *dev, wchar_t ch)
-{
-	amdm37x_uart_t *uart = dev->data;
-	if (!ascii_check(ch)) {
-		amdm37x_uart_txb(uart, U_SPECIAL);
-	} else {
-		if (ch == '\n')
-			amdm37x_uart_txb(uart, '\r');
-		amdm37x_uart_txb(uart, ch);
-	}
-}
-
-static outdev_operations_t amdm37x_uart_ops = {
-	.redraw = NULL,
-	.write = amdm37x_uart_putchar,
-};
-
-static irq_ownership_t amdm37x_uart_claim(irq_t *irq)
-{
-	return IRQ_ACCEPT;
-}
-
-static void amdm37x_uart_handler(irq_t *irq)
-{
-	amdm37x_uart_t *uart = irq->instance;
-	while ((uart->regs->rx_fifo_lvl)) {
-		const uint8_t val = uart->regs->rhr;
-		if (uart->indev && val) {
-			indev_push_character(uart->indev, val);
-		}
-	}
-}
-
-bool amdm37x_uart_init(
-    amdm37x_uart_t *uart, inr_t interrupt, uintptr_t addr, size_t size)
-{
-	ASSERT(uart);
-	uart->regs = (void *)km_map(addr, size, PAGE_NOT_CACHEABLE);
-
-	ASSERT(uart->regs);
-
-	/* See TI OMAP35X TRM ch 17.5.1.1 p. 2732 for startup routine */
-#if 0
-	/* Soft reset the port */
-	uart->regs->sysc = AMDM37x_UART_SYSC_SOFTRESET_FLAG;
-	while (!(uart->regs->syss & AMDM37x_UART_SYSS_RESETDONE_FLAG)) ;
-#endif
-
-	/* Enable access to EFR register */
-	const uint8_t lcr = uart->regs->lcr; /* Save old value */
-	uart->regs->lcr = 0xbf;              /* Sets config mode B */
-
-	/* Enable access to TCL_TLR register */
-	const bool enhanced = uart->regs->efr & AMDM37x_UART_EFR_ENH_FLAG;
-	uart->regs->efr |= AMDM37x_UART_EFR_ENH_FLAG; /* Turn on enh. */
-	uart->regs->lcr = 0x80;              /* Config mode A */
-
-	/* Set default (val 0) triggers, disable DMA enable FIFOs */
-	const bool tcl_tlr = uart->regs->mcr & AMDM37x_UART_MCR_TCR_TLR_FLAG;
-	/* Enable access to tcr and tlr registers */
-	uart->regs->mcr |= AMDM37x_UART_MCR_TCR_TLR_FLAG;
-
-	/* Enable FIFOs */
-	uart->regs->fcr = AMDM37x_UART_FCR_FIFO_EN_FLAG;
-
-	/* Eneble fine granularity for RX FIFO and set trigger level to 1,
-	 * TX FIFO, trigger level is irelevant*/
-	uart->regs->lcr = 0xbf;              /* Sets config mode B */
-	uart->regs->scr = AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG;
-	uart->regs->tlr = 1 << AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT;
-
-	/* Restore enhanced */
-	if (!enhanced)
-		uart->regs->efr &= ~AMDM37x_UART_EFR_ENH_FLAG;
-
-	uart->regs->lcr = 0x80;              /* Config mode A */
-	/* Restore tcl_lcr access flag*/
-	if (!tcl_tlr)
-		uart->regs->mcr &= ~AMDM37x_UART_MCR_TCR_TLR_FLAG;
-
-	/* Restore lcr */
-	uart->regs->lcr = lcr;
-
-	/* Disable interrupts */
-	uart->regs->ier = 0;
-
-	/* Setup outdev */
-	outdev_initialize("amdm37x_uart_dev", &uart->outdev, &amdm37x_uart_ops);
-	uart->outdev.data = uart;
-
-	/* Initialize IRQ */
-	irq_initialize(&uart->irq);
-	uart->irq.devno = device_assign_devno();
-	uart->irq.inr = interrupt;
-	uart->irq.claim = amdm37x_uart_claim;
-	uart->irq.handler = amdm37x_uart_handler;
-	uart->irq.instance = uart;
-
-	return true;
-}
-
-void amdm37x_uart_input_wire(amdm37x_uart_t *uart, indev_t *indev)
-{
-	ASSERT(uart);
-	/* Set indev */
-	uart->indev = indev;
-	/* Register interrupt. */
-	irq_register(&uart->irq);
-	/* Enable interrupt on receive */
-	uart->regs->ier |= AMDM37x_UART_IER_RHR_IRQ_FLAG;
-}
-
-/**
- * @}
- */
