Index: boot/arch/arm32/Makefile.inc
===================================================================
--- boot/arch/arm32/Makefile.inc	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ boot/arch/arm32/Makefile.inc	(revision 179f6f2bf553edec9f7da2bcd60ea5a63afb17db)
@@ -49,5 +49,5 @@
 BITS = 32
 ENDIANESS = LE
-EXTRA_CFLAGS = -march=armv4
+EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR))
 
 ifeq ($(MACHINE), gta02)
Index: boot/arch/arm32/src/mm.c
===================================================================
--- boot/arch/arm32/src/mm.c	(revision c127e1ccb10c2c7b86a2fce5e27f2378ecb9a6a9)
+++ boot/arch/arm32/src/mm.c	(revision 179f6f2bf553edec9f7da2bcd60ea5a63afb17db)
@@ -107,9 +107,5 @@
 		"mcr p15, 0, r0, c3, c0, 0\n"
 		
-#ifdef PROCESSOR_armv7
-		/* Clean L2 cache */
-		"mov r12, #0x1\n"   //set up to invalidate L2
-		"smc #0\n"  //Call SMI monitor
-		
+#ifdef PROCESSOR_armv7_a
 		/* Read Auxiliary control register */
 		"mrc p15, 0, r0, c1, c0, 1\n"
@@ -123,5 +119,5 @@
 		"mrc p15, 0, r0, c1, c0, 0\n"
 		
-#ifdef PROCESSOR_armv7
+#ifdef PROCESSOR_armv7_a
 		/* Mask to enable paging, alignment and caching */
 		"ldr r1, =0x00000007\n"