Index: boot/arch/sparc64/loader/asm.S
===================================================================
--- boot/arch/sparc64/loader/asm.S	(revision a1a83e5e5ddb366d3021bdee2baa08d1a60230fc)
+++ boot/arch/sparc64/loader/asm.S	(revision 1787e527c803ec9bf678df8b19b0de9e18985f12)
@@ -31,6 +31,6 @@
 #include <register.h>
 
-.register       %g2, #scratch
-.register       %g3, #scratch
+.register %g2, #scratch
+.register %g3, #scratch
 
 .text
@@ -43,60 +43,67 @@
 	ba %xcc, halt
 	nop
+
+memcpy:
+	mov %o0, %o3      ! save dst
+	add %o1, 7, %g1
+	and %g1, -8, %g1
+	cmp %o1, %g1
+	be,pn %xcc, 3f
+	add %o0, 7, %g1
+	mov 0, %g3
 	
-memcpy:
-	mov	%o0, %o3		! save dst
-	add	%o1, 7, %g1
-	and	%g1, -8, %g1
-	cmp	%o1, %g1
-	be,pn	%xcc, 3f
-	add	%o0, 7, %g1
-	mov	0, %g3
-0:
-	brz,pn	%o2, 2f
-	mov	0, %g2
-1:
-	ldub	[%g3 + %o1], %g1
-	add	%g2, 1, %g2
-	cmp	%o2, %g2
-	stb	%g1, [%g3 + %o0]
-	bne,pt	%xcc, 1b
-	mov	%g2, %g3
-2:
-	jmp	%o7 + 8			! exit point
-	mov	%o3, %o0
-3:
-	and	%g1, -8, %g1
-	cmp	%o0, %g1
-	bne,pt	%xcc, 0b
-	mov	0, %g3
-	srlx	%o2, 3, %g4
-	brz,pn	%g4, 5f
-	mov	0, %g5
-4:
-	sllx	%g3, 3, %g2
-	add	%g5, 1, %g3
-	ldx	[%o1 + %g2], %g1
-	mov	%g3, %g5
-	cmp	%g4, %g3
-	bne,pt	%xcc, 4b
-	stx	%g1, [%o0 + %g2]
-5:
-	and	%o2, 7, %o2
-	brz,pn	%o2, 2b
-	sllx	%g4, 3, %g1
-	mov	0, %g2
-	add	%g1, %o0, %o0
-	add	%g1, %o1, %g4
-	mov	0, %g3
-6:
-	ldub	[%g2 + %g4], %g1
-	stb	%g1, [%g2 + %o0]
-	add	%g3, 1, %g2
-	cmp	%o2, %g2
-	bne,pt	%xcc, 6b
-	mov	%g2, %g3
-
-	jmp	%o7 + 8			! exit point
-	mov	%o3, %o0
+	0:
+		brz,pn %o2, 2f
+		mov 0, %g2
+	
+	1:
+		ldub [%g3 + %o1], %g1
+		add %g2, 1, %g2
+		cmp %o2, %g2
+		stb %g1, [%g3 + %o0]
+		bne,pt %xcc, 1b
+		mov %g2, %g3
+	
+	2:
+		jmp %o7 + 8   ! exit point
+		mov %o3, %o0
+	
+	3:
+		and %g1, -8, %g1
+		cmp %o0, %g1
+		bne,pt %xcc, 0b
+		mov 0, %g3
+		srlx %o2, 3, %g4
+		brz,pn %g4, 5f
+		mov 0, %g5
+	
+	4:
+		sllx %g3, 3, %g2
+		add %g5, 1, %g3
+		ldx [%o1 + %g2], %g1
+		mov %g3, %g5
+		cmp %g4, %g3
+		bne,pt %xcc, 4b
+		stx %g1, [%o0 + %g2]
+	
+	5:
+		and %o2, 7, %o2
+		brz,pn %o2, 2b
+		sllx %g4, 3, %g1
+		mov 0, %g2
+		add %g1, %o0, %o0
+		add %g1, %o1, %g4
+		mov 0, %g3
+	
+	6:
+		ldub [%g2 + %g4], %g1
+		stb %g1, [%g2 + %o0]
+		add %g3, 1, %g2
+		cmp %o2, %g2
+		bne,pt %xcc, 6b
+		mov %g2, %g3
+	
+	jmp %o7 + 8   ! exit point
+	mov %o3, %o0
 
 jump_to_kernel:
@@ -107,51 +114,55 @@
 	 * 3. Flush instruction pipeline.
 	 */
-
+	
 	/*
 	 * US3 processors have a write-invalidate cache, so explicitly
 	 * invalidating it is not required. Whether to invalidate I-cache
-	 * or not is decided according to the value of the global
-	 * "subarchitecture" variable (set in the bootstrap).
+	 * or not is decided according to the value of the 5th argument
+	 * (subarchitecture).
 	 */
-	set subarchitecture, %g2
-	ldub [%g2], %g2
-	cmp %g2, 3
+	cmp %i4, 3
 	be %xcc, 1f
 	nop
-0:
-	call icache_flush
-	nop
-1:
-	membar #StoreStore
+	
+	0:
+		call icache_flush
+		nop
+	
+	1:
+		membar #StoreStore
 	
 	/*
 	 * Flush the instruction pipeline.
 	 */
-	flush	%i7
-
+	flush %i7
+	
 	mov %o0, %l1
 	mov %o1, %o0
 	mov %o2, %o1
 	mov %o3, %o2
-	jmp %l1				! jump to kernel
+	jmp %l1       ! jump to kernel
 	nop
 
-#define ICACHE_SIZE		8192
-#define ICACHE_LINE_SIZE	32
-#define ICACHE_SET_BIT		(1 << 13)
-#define ASI_ICACHE_TAG		0x67
+#define ICACHE_SIZE       8192
+#define ICACHE_LINE_SIZE  32
+#define ICACHE_SET_BIT    (1 << 13)
+#define ASI_ICACHE_TAG    0x67
 
 # Flush I-cache
 icache_flush:
-	set	((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1
-	stxa	%g0, [%g1] ASI_ICACHE_TAG
-0:	membar	#Sync
-	subcc	%g1, ICACHE_LINE_SIZE, %g1
-	bnz,pt	%xcc, 0b
-	stxa	%g0, [%g1] ASI_ICACHE_TAG
-	membar	#Sync
+	set ((ICACHE_SIZE - ICACHE_LINE_SIZE) | ICACHE_SET_BIT), %g1
+	stxa %g0, [%g1] ASI_ICACHE_TAG
+	
+	0:
+		membar #Sync
+		subcc %g1, ICACHE_LINE_SIZE, %g1
+		bnz,pt %xcc, 0b
+	
+	stxa %g0, [%g1] ASI_ICACHE_TAG
+	membar #Sync
 	retl
 	! SF Erratum #51
 	nop
+
 .global ofw
 ofw:
@@ -159,14 +170,14 @@
 	set ofw_cif, %l0
 	ldx [%l0], %l0
-
+	
 	rdpr  %pstate, %l1
 	and  %l1, ~PSTATE_AM_BIT, %l2
 	wrpr  %l2, 0, %pstate
-    
+	
 	jmpl %l0, %o7
 	mov %i0, %o0
-
+	
 	wrpr %l1, 0, %pstate
-
+	
 	ret
 	restore %o0, 0, %o0
