Index: uspace/drv/infrastructure/rootamdm37x/prm/clock_control.h
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/prm/clock_control.h	(revision 17be8c2d723504080ddc7761884379e5b6b72ff3)
+++ uspace/drv/infrastructure/rootamdm37x/prm/clock_control.h	(revision 167c7b390cfc394f1747a84c725053b73b99e21c)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup amdm37xdrvclockcontrolprm
+/** @addtogroup amdm37xdrvprm
  * @{
  */
Index: uspace/drv/infrastructure/rootamdm37x/prm/usbhost.h
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/prm/usbhost.h	(revision 17be8c2d723504080ddc7761884379e5b6b72ff3)
+++ uspace/drv/infrastructure/rootamdm37x/prm/usbhost.h	(revision 167c7b390cfc394f1747a84c725053b73b99e21c)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup amdm37xdrvclockcontrolprm
+/** @addtogroup amdm37xdrvprm
  * @{
  */
Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision 17be8c2d723504080ddc7761884379e5b6b72ff3)
+++ uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision 167c7b390cfc394f1747a84c725053b73b99e21c)
@@ -56,4 +56,5 @@
 
 #include "prm/clock_control.h"
+#include "prm/global_reg.h"
 
 #define NAME  "rootamdm37x"
@@ -71,4 +72,5 @@
 	struct {
 		clock_control_prm_regs_t *clocks;
+		global_reg_prm_regs_t *global;
 	} prm;
 } amdm37x_t;
@@ -112,4 +114,9 @@
 	ret = pio_enable((void*)CLOCK_CONTROL_PRM_BASE_ADDRESS,
 	    CLOCK_CONTROL_PRM_SIZE, (void**)&device->prm.clocks);
+	if (ret != EOK)
+		return ret;
+
+	ret = pio_enable((void*)GLOBAL_REG_PRM_BASE_ADDRESS,
+	    GLOBAL_REG_PRM_SIZE, (void**)&device->prm.global);
 	if (ret != EOK)
 		return ret;
@@ -134,4 +141,5 @@
 		pio_trace_enable(device->uhh, AMDM37x_UHH_SIZE, log, (void*)AMDM37x_UHH_BASE_ADDRESS);
 		pio_trace_enable(device->prm.clocks, CLOCK_CONTROL_PRM_SIZE, log, (void*)CLOCK_CONTROL_PRM_BASE_ADDRESS);
+		pio_trace_enable(device->prm.global, GLOBAL_REG_PRM_SIZE, log, (void*)GLOBAL_REG_PRM_BASE_ADDRESS);
 	}
 	return EOK;
@@ -151,8 +159,10 @@
 	/* Get SYS_CLK value, it is used as reference clock by all DPLLs,
 	 * NFI who sets this or why it is set to specific value. */
-	const unsigned base_clk = pio_read_32(&device->prm.clocks->clksel)
+	const unsigned osc_clk = pio_read_32(&device->prm.clocks->clksel)
 	    & CLOCK_CONTROL_PRM_CLKSEL_SYS_CLKIN_MASK;
-	const unsigned base_freq = sys_clk_freq_kHz(base_clk);
-	ddf_msg(LVL_DEBUG, "Base frequency: %d.%dMhz",
+	const unsigned clk_reg = pio_read_32(&device->prm.global->clksrc_ctrl);
+	const unsigned base_freq = sys_clk_freq_kHz(osc_clk)
+	    / GLOBAL_REG_PRM_CLKSRC_CTRL_SYSCLKDIV_GET(clk_reg);
+	ddf_msg(LVL_NOTE, "Base frequency: %d.%dMhz",
 	    base_freq / 1000, base_freq % 1000);