Changes in boot/arch/arm32/src/main.c [0e63d34:15fbe6a] in mainline

File:

• boot/arch/arm32/src/main.c (modified) (5 diffs)

boot/arch/arm32/src/main.c

@@ -47 +47 @@
 #include <errno.h>
 #include <inflate.h>
+#include <arch/cp15.h>
 
 #define TOP2ADDR(top)  (((void *) PA2KA(BOOT_OFFSET)) + (top))
@@ -53 +54 @@
 extern void *bdata_end;
 
-
-static inline void invalidate_icache(void)
-{
-        /* ICIALLU Invalidate entire ICache */
-        asm volatile ("mov r0, #0\n" "mcr p15, 0, r0, c7, c5, 0\n" ::: "r0" );
-}
-
-static inline void invalidate_dcache(void *address, size_t size)
-{
-        const uintptr_t addr = (uintptr_t)address;
-        /* DCIMVAC - invalidate by address to the point of coherence */
-        for (uintptr_t a = addr; a < addr + size; a += 4) {
-                asm volatile ("mcr p15, 0, %[a], c7, c6, 1\n" :: [a]"r"(a) : );
-        }
-}
-
 static inline void clean_dcache_poc(void *address, size_t size)
 {
-        const uintptr_t addr = (uintptr_t)address;
-        /* DCCMVAC - clean by address to the point of coherence */
-        for (uintptr_t a = addr; a < addr + size; a += 4) {
-                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
+        const uintptr_t addr = (uintptr_t) address;
+
+#if !defined(PROCESSOR_ARCH_armv7_a)
+        bool sep;
+        if (MIDR_read() != CTR_read()) {
+                sep = (CTR_read() & CTR_SEP_FLAG) == CTR_SEP_FLAG;
+        } else {
+                printf("Unknown cache type.\n");
+                halt();
+        }
+#endif
+
+        for (uintptr_t a = ALIGN_DOWN(addr, CP15_C7_MVA_ALIGN); a < addr + size;
+            a += CP15_C7_MVA_ALIGN) {
+#if defined(PROCESSOR_ARCH_armv7_a)
+                DCCMVAC_write(a);
+#else
+                if (sep)
+                        DCCMVA_write(a);
+                else
+                        CCMVA_write(a);
+#endif
         }
 }
@@ -82 +85 @@
 void bootstrap(void)
 {
-        /* Make sure  we run in memory code when caches are enabled,
-         * make sure we read memory data too. This part is ARMv7 specific as
-         * ARMv7 no longer invalidates caches on restart.
-         * See chapter B2.2.2 of ARM Architecture Reference Manual p. B2-1263*/
-        invalidate_icache();
-        invalidate_dcache(&bdata_start, &bdata_end - &bdata_start);
-
         /* Enable MMU and caches */
         mmu_start();
@@ -105 +101 @@
                     components[i].start, components[i].name, components[i].inflated,
                     components[i].size);
-                invalidate_dcache(components[i].start, components[i].size);
         }
         
@@ -148 +143 @@
                         halt();
                 }
+                /* Make sure data are in the memory, ICache will need them */
                 clean_dcache_poc(dest[i - 1], components[i - 1].inflated);
         }
         
         printf(".\n");
+
+        /* Flush PT too. We need this if we disable caches later */
+        clean_dcache_poc(boot_pt, PTL0_ENTRIES * PTL0_ENTRY_SIZE);
         
         printf("Booting the kernel...\n");