Changeset 15fbe6a in mainline for boot/arch/arm32/src/main.c

Timestamp:

2015-10-06T20:23:44Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

803f581

Parents:

afe5e09

Message:

Fix clean_dcache_poc() wrt. ARMv6-

Clean D$ according to the actual architecture and processor.
Make sure the MVA is always CP15_C7_MVA_ALIGN-aligned.

File:

• boot/arch/arm32/src/main.c (modified) (2 diffs)

boot/arch/arm32/src/main.c

@@ -47 +47 @@
 #include <errno.h>
 #include <inflate.h>
+#include <arch/cp15.h>
 
 #define TOP2ADDR(top)  (((void *) PA2KA(BOOT_OFFSET)) + (top))
@@ -55 +56 @@
 static inline void clean_dcache_poc(void *address, size_t size)
 {
-        const uintptr_t addr = (uintptr_t)address;
-        for (uintptr_t a = addr; a < addr + size; a += 4) {
-                /* DCCMVAC - clean by address to the point of coherence */
-                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
+        const uintptr_t addr = (uintptr_t) address;
+
+#if !defined(PROCESSOR_ARCH_armv7_a)
+        bool sep;
+        if (MIDR_read() != CTR_read()) {
+                sep = (CTR_read() & CTR_SEP_FLAG) == CTR_SEP_FLAG;
+        } else {
+                printf("Unknown cache type.\n");
+                halt();
+        }
+#endif
+
+        for (uintptr_t a = ALIGN_DOWN(addr, CP15_C7_MVA_ALIGN); a < addr + size;
+            a += CP15_C7_MVA_ALIGN) {
+#if defined(PROCESSOR_ARCH_armv7_a)
+                DCCMVAC_write(a);
+#else
+                if (sep)
+                        DCCMVA_write(a);
+                else
+                        CCMVA_write(a);
+#endif
         }
 }