Index: boot/arch/arm32/src/main.c
===================================================================
--- boot/arch/arm32/src/main.c	(revision afe5e09834ae57e9f9d6b7ccdce21b34a8690041)
+++ boot/arch/arm32/src/main.c	(revision 15fbe6acd40fcb3e688db865b931ed04c43f0548)
@@ -47,4 +47,5 @@
 #include <errno.h>
 #include <inflate.h>
+#include <arch/cp15.h>
 
 #define TOP2ADDR(top)  (((void *) PA2KA(BOOT_OFFSET)) + (top))
@@ -55,8 +56,26 @@
 static inline void clean_dcache_poc(void *address, size_t size)
 {
-	const uintptr_t addr = (uintptr_t)address;
-	for (uintptr_t a = addr; a < addr + size; a += 4) {
-		/* DCCMVAC - clean by address to the point of coherence */
-		asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
+	const uintptr_t addr = (uintptr_t) address;
+
+#if !defined(PROCESSOR_ARCH_armv7_a)
+	bool sep;
+	if (MIDR_read() != CTR_read()) {
+		sep = (CTR_read() & CTR_SEP_FLAG) == CTR_SEP_FLAG;
+	} else {
+		printf("Unknown cache type.\n");
+		halt();
+	}
+#endif
+
+	for (uintptr_t a = ALIGN_DOWN(addr, CP15_C7_MVA_ALIGN); a < addr + size;
+	    a += CP15_C7_MVA_ALIGN) {
+#if defined(PROCESSOR_ARCH_armv7_a)
+		DCCMVAC_write(a);
+#else
+		if (sep)
+			DCCMVA_write(a);
+		else
+			CCMVA_write(a);
+#endif
 	}
 }