Index: uspace/drv/infrastructure/rootamdm37x/clock_control_cm.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/clock_control_cm.h (revision f5ffc9a1bd3617efdb275ac8185b46800cc10b07) +++ (revision ) @@ -1,155 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvclockcontrolcm - * @{ - */ -/** @file - * @brief Clock Control Clock Management IO register structure. - */ -#ifndef AMDM37x_CLOCK_CONTROL_CM_H -#define AMDM37x_CLOCK_CONTROL_CM_H -#include -#include - -/* AM/DM37x TRM p.485 */ -#define CLOCK_CONTROL_CM_BASE_ADDRESS 0x48004d00 -#define CLOCK_CONTROL_CM_SIZE 8192 - -/** Clock control register map - * - * Periph DPLL == DPLL4 - * Core DPLL == DPLL3 - */ -typedef struct { - ioport32_t clken_pll; -#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_PERIPH_FLAG (1 << 31) -#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_CAM_FLAG (1 << 30) -#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_DSS1_FLAG (1 << 29) -#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_TV_FLAG (1 << 28) -#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_96M_FLAG (1 << 27) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_DRIFTGUARD_FLAG (1 << 19) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_MASK (0x7 << 16) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LP_STOP (0x1 << 16) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LOCK (0x7 << 16) -#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_CORE_FLAG (1 << 12) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LPMODE_FLAG (1 << 10) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_DRIFTGUARD_FLAG (1 << 3) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_MASK (0x7) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LP_BYPASS (0x5) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_FAST_RELOCK (0x6) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LOCK (0x7) - - ioport32_t clken2_pll; -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LPMODE_FLAG (1 << 10) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_DRIFTGUARD_FLAG (1 << 3) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_MASK (0x7) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LP_STOP (0x1) -#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LOCK (0x7) - - PADD32[6]; - - const ioport32_t idlest_ckgen; -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_EMU_PERIPH_CLK_FLAG (1 << 13) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CAM_CLK_FLAG (1 << 12) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_DSS1_CLK_FLAG (1 << 11) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_TV_CLK_FLAG (1 << 10) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_FUNC96M_CLK_FLAG (1 << 9) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_EMU_CORE_CLK_FLAG (1 << 8) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_54M_CLK_FLAG (1 << 5) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_12M_CLK_FLAG (1 << 4) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_48M_CLK_FLAG (1 << 3) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_96M_CLK_FLAG (1 << 2) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_PERIPH_CLK_FLAG (1 << 1) -#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG (1 << 0) - - const ioport32_t idlest2_ckgen; -#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_FUNC120M_CLK_FLAG (1 << 3) -#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_120M_CLK_FLAG (1 << 1) -#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_PERIPH2_CLK_FLAG (1 << 0) - - PADD32[2]; - - ioport32_t autoidle_pll; -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK (0x7 << 3) -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_DISABLED (0x0 << 3) -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC (0x1 << 3) -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK (0x7) -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_DISABLED (0x0) -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC (0x1) -#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC_BYPASS (0x5) - - ioport32_t autoidle2_pll; -#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK (0x7) -#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_DISABLED (0x0) -#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC (0x1) - - PADD32[2]; - - ioport32_t clksel1_pll; -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_(x) (((x) & 0x1f) << 27) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_MASK (0x7ff << 16) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT(x) (((x) & 0x7ff) << 16) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_MASK (0x7f << 8) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV(x) (((x) & 0x7f) << 8) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_96M_FLAG (1 << 6) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_54M_FLAG (1 << 5) -#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_48M_FLAG (1 << 3) - - ioport32_t clksel2_pll; -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_MASK (0xff << 24) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_(x) (((x) & 0xff) << 24) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_MASK (0x7 << 21) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_500 (0x2 << 21) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_1000 (0x4 << 21) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT_MASK (0xfff << 8) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT(x) (((x) & 0xfff) << 8) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV_MASK (0x7f) -#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV(x) ((x) & 0x7f) - - ioport32_t clksel3_pll; -#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M_MASK (0xf) -#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M(x) ((x) & 0xf) - - ioport32_t clksel4_pll; -#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) -#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT(x) (((x) & 0x7ff) << 8) -#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK (0x7f) -#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV(x) ((x) & 0x7f) - - ioport32_t clksel5_pll; -#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK (0x1f) -#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M(x) ((x) & 0x1f) -} clock_control_cm_regs_t; - -#endif -/** - * @} - */ - Index: uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h (revision 150a271898ef7efbc0fcad8d33cfafa0104fdb78) +++ uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h (revision 150a271898ef7efbc0fcad8d33cfafa0104fdb78) @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvclockcontrolcm + * @{ + */ +/** @file + * @brief Clock Control Clock Management IO register structure. + */ +#ifndef AMDM37x_CLOCK_CONTROL_CM_H +#define AMDM37x_CLOCK_CONTROL_CM_H +#include +#include + +/* AM/DM37x TRM p.485 */ +#define CLOCK_CONTROL_CM_BASE_ADDRESS 0x48004d00 +#define CLOCK_CONTROL_CM_SIZE 8192 + +/** Clock control register map + * + * Periph DPLL == DPLL4 + * Core DPLL == DPLL3 + */ +typedef struct { + ioport32_t clken_pll; +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_PERIPH_FLAG (1 << 31) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_CAM_FLAG (1 << 30) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_DSS1_FLAG (1 << 29) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_TV_FLAG (1 << 28) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_96M_FLAG (1 << 27) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_DRIFTGUARD_FLAG (1 << 19) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_MASK (0x7 << 16) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LP_STOP (0x1 << 16) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH_DPLL_LOCK (0x7 << 16) +#define CLOCK_CONTROL_CM_CLKEN_PLL_PWRDN_EMU_CORE_FLAG (1 << 12) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LPMODE_FLAG (1 << 10) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_DRIFTGUARD_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LP_BYPASS (0x5) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_FAST_RELOCK (0x6) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_CORE_DPLL_LOCK (0x7) + + ioport32_t clken2_pll; +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LPMODE_FLAG (1 << 10) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_DRIFTGUARD_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LP_STOP (0x1) +#define CLOCK_CONTROL_CM_CLKEN_PLL_EN_PERIPH2_DPLL_LOCK (0x7) + + PADD32[6]; + + const ioport32_t idlest_ckgen; +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_EMU_PERIPH_CLK_FLAG (1 << 13) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CAM_CLK_FLAG (1 << 12) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_DSS1_CLK_FLAG (1 << 11) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_TV_CLK_FLAG (1 << 10) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_FUNC96M_CLK_FLAG (1 << 9) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_EMU_CORE_CLK_FLAG (1 << 8) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_54M_CLK_FLAG (1 << 5) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_12M_CLK_FLAG (1 << 4) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_48M_CLK_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_96M_CLK_FLAG (1 << 2) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_PERIPH_CLK_FLAG (1 << 1) +#define CLOCK_CONTROL_CM_IDLEST_CKGEN_ST_CORE_CLK_FLAG (1 << 0) + + const ioport32_t idlest2_ckgen; +#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_FUNC120M_CLK_FLAG (1 << 3) +#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_120M_CLK_FLAG (1 << 1) +#define CLOCK_CONTROL_CM_IDLEST2_CKGEN_ST_PERIPH2_CLK_FLAG (1 << 0) + + PADD32[2]; + + ioport32_t autoidle_pll; +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK (0x7 << 3) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_DISABLED (0x0 << 3) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC (0x1 << 3) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_DISABLED (0x0) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC (0x1) +#define CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC_BYPASS (0x5) + + ioport32_t autoidle2_pll; +#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK (0x7) +#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_DISABLED (0x0) +#define CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC (0x1) + + PADD32[2]; + + ioport32_t clksel1_pll; +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_(x) (((x) & 0x1f) << 27) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_MASK (0x7ff << 16) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT(x) (((x) & 0x7ff) << 16) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_MASK (0x7f << 8) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV(x) (((x) & 0x7f) << 8) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_96M_FLAG (1 << 6) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_54M_FLAG (1 << 5) +#define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_48M_FLAG (1 << 3) + + ioport32_t clksel2_pll; +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_MASK (0xff << 24) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_SD_DIV_(x) (((x) & 0xff) << 24) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_MASK (0x7 << 21) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_500 (0x2 << 21) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_DCO_SEL_1000 (0x4 << 21) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT_MASK (0xfff << 8) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_MULT(x) (((x) & 0xfff) << 8) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV_MASK (0x7f) +#define CLOCK_CONTROL_CM_CLKSEL2_PLL_PERIPH_DPLL_DIV(x) ((x) & 0x7f) + + ioport32_t clksel3_pll; +#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M_MASK (0xf) +#define CLOCK_CONTROL_CM_CLKSEL3_PLL_DIV_96M(x) ((x) & 0xf) + + ioport32_t clksel4_pll; +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_MULT(x) (((x) & 0x7ff) << 8) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV_MASK (0x7f) +#define CLOCK_CONTROL_CM_CLKSEL4_PLL_PERIPH2_DPLL_DIV(x) ((x) & 0x7f) + + ioport32_t clksel5_pll; +#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M_MASK (0x1f) +#define CLOCK_CONTROL_CM_CLKSEL5_PLL_DIV120M(x) ((x) & 0x1f) +} clock_control_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/infrastructure/rootamdm37x/cm/core.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/core.h (revision 150a271898ef7efbc0fcad8d33cfafa0104fdb78) +++ uspace/drv/infrastructure/rootamdm37x/cm/core.h (revision 150a271898ef7efbc0fcad8d33cfafa0104fdb78) @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvcorecm + * @{ + */ +/** @file + * @brief CORE Clock Management IO register structure. + */ +#ifndef AMDM37x_CORE_CM_H +#define AMDM37x_CORE_CM_H +#include +#include + +/* AM/DM37x TRM p.447 */ +#define CORE_CM_BASE_ADDRESS 0x48004a00 +#define CORE_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken1; +#define CORE_CM_FCLKEN1_EN_MCBSP1_FLAG (1 << 9) +#define CORE_CM_FCLKEN1_EN_MCBSP5_FLAG (1 << 10) +#define CORE_CM_FCLKEN1_EN_GPT10_FLAG (1 << 11) +#define CORE_CM_FCLKEN1_EN_GPT11_FLAG (1 << 12) +#define CORE_CM_FCLKEN1_EN_UART1_FLAG (1 << 13) +#define CORE_CM_FCLKEN1_EN_UART2_FLAG (1 << 14) +#define CORE_CM_FCLKEN1_EN_I2C1_FLAG (1 << 15) +#define CORE_CM_FCLKEN1_EN_I2C2_FLAG (1 << 16) +#define CORE_CM_FCLKEN1_EN_I2C3_FLAG (1 << 17) +#define CORE_CM_FCLKEN1_EN_MCSPI1_FLAG (1 << 18) +#define CORE_CM_FCLKEN1_EN_MCSPI2_FLAG (1 << 19) +#define CORE_CM_FCLKEN1_EN_MCSPI3_FLAG (1 << 20) +#define CORE_CM_FCLKEN1_EN_MCSPI4_FLAG (1 << 21) +#define CORE_CM_FCLKEN1_EN_HDQ_FLAG (1 << 22) +#define CORE_CM_FCLKEN1_EN_MMC1_FLAG (1 << 24) +#define CORE_CM_FCLKEN1_EN_MMC2_FLAG (1 << 25) +#define CORE_CM_FCLKEN1_EN_MMC3_FLAG (1 << 30) + + PADD32; + ioport32_t fclken3; +#define CORE_CM_FCLKEN3_EN_TS_FLAG (1 << 1) +#define CORE_CM_FCLKEN3_EN_USBTLL_FLAG (1 << 2) + + PADD32; + ioport32_t iclken1; +#define CORE_CM_ICLKEN1_EN_SDRC_FLAG (1 << 1) +#define CORE_CM_ICLKEN1_EN_HSOTGUSB_FLAG (1 << 4) +#define CORE_CM_ICLKEN1_EN_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_ICLKEN1_EN_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_ICLKEN1_EN_MCBSP1_FLAG (1 << 9) +#define CORE_CM_ICLKEN1_EN_MCBSP5_FLAG (1 << 10) +#define CORE_CM_ICLKEN1_EN_GPT10_FLAG (1 << 11) +#define CORE_CM_ICLKEN1_EN_GPT11_FLAG (1 << 12) +#define CORE_CM_ICLKEN1_EN_UART1_FLAG (1 << 13) +#define CORE_CM_ICLKEN1_EN_UART2_FLAG (1 << 14) +#define CORE_CM_ICLKEN1_EN_I2C1_FLAG (1 << 15) +#define CORE_CM_ICLKEN1_EN_I2C2_FLAG (1 << 16) +#define CORE_CM_ICLKEN1_EN_I2C3_FLAG (1 << 17) +#define CORE_CM_ICLKEN1_EN_MCSPI1_FLAG (1 << 18) +#define CORE_CM_ICLKEN1_EN_MCSPI2_FLAG (1 << 19) +#define CORE_CM_ICLKEN1_EN_MCSPI3_FLAG (1 << 20) +#define CORE_CM_ICLKEN1_EN_MCSPI4_FLAG (1 << 21) +#define CORE_CM_ICLKEN1_EN_HDQ_FLAG (1 << 22) +#define CORE_CM_ICLKEN1_EN_MMC1_FLAG (1 << 24) +#define CORE_CM_ICLKEN1_EN_MMC2_FLAG (1 << 25) +#define CORE_CM_ICLKEN1_EN_ICR_FLAG (1 << 29) +#define CORE_CM_ICLKEN1_EN_MMC3_FLAG (1 << 30) + + ioport32_t reserved1; + ioport32_t iclken3; +#define CORE_CM_ICLKEN3_EN_USBTLL_FLAG (1 << 2) + + PADD32; + const ioport32_t idlest1; +#define CORE_CM_IDLEST1_ST_SDRC_FLAG (1 << 1) +#define CORE_CM_IDLEST1_ST_SDMA_FLAG (1 << 2) +#define CORE_CM_IDLEST1_ST_HSOTGUSB_STBY_FLAG (1 << 4) +#define CORE_CM_IDLEST1_ST_HSOTGUSB_IDLE_FLAG (1 << 5) +#define CORE_CM_IDLEST1_ST_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_IDLEST1_ST_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_IDLEST1_ST_MCBSP1_FLAG (1 << 9) +#define CORE_CM_IDLEST1_ST_MCBSP5_FLAG (1 << 10) +#define CORE_CM_IDLEST1_ST_GPT10_FLAG (1 << 11) +#define CORE_CM_IDLEST1_ST_GPT11_FLAG (1 << 12) +#define CORE_CM_IDLEST1_ST_UART1_FLAG (1 << 13) +#define CORE_CM_IDLEST1_ST_UART2_FLAG (1 << 14) +#define CORE_CM_IDLEST1_ST_I2C1_FLAG (1 << 15) +#define CORE_CM_IDLEST1_ST_I2C2_FLAG (1 << 16) +#define CORE_CM_IDLEST1_ST_I2C3_FLAG (1 << 17) +#define CORE_CM_IDLEST1_ST_MCSPI1_FLAG (1 << 18) +#define CORE_CM_IDLEST1_ST_MCSPI2_FLAG (1 << 19) +#define CORE_CM_IDLEST1_ST_MCSPI3_FLAG (1 << 20) +#define CORE_CM_IDLEST1_ST_MCSPI4_FLAG (1 << 21) +#define CORE_CM_IDLEST1_ST_HDQ_FLAG (1 << 22) +#define CORE_CM_IDLEST1_ST_MMC1_FLAG (1 << 24) +#define CORE_CM_IDLEST1_ST_MMC2_FLAG (1 << 25) +#define CORE_CM_IDLEST1_ST_ICR_FLAG (1 << 29) +#define CORE_CM_IDLEST1_ST_MMC3_FLAG (1 << 30) + + const ioport32_t reserved2; + const ioport32_t idlest3; +#define CORE_CM_IDLEST3_ST_USBTLL_FLAG (1 << 2) + + PADD32; + ioport32_t autoidle1; +#define CORE_CM_AUTOIDLE1_AUTO_HSOTGUSB_FLAG (1 << 4) +#define CORE_CM_AUTOIDLE1_AUTO_SCMCTRL_FLAG (1 << 6) +#define CORE_CM_AUTOIDLE1_AUTO_MAILBOXES_FLAG (1 << 7) +#define CORE_CM_AUTOIDLE1_AUTO_MCBSP1_FLAG (1 << 9) +#define CORE_CM_AUTOIDLE1_AUTO_MCBSP5_FLAG (1 << 10) +#define CORE_CM_AUTOIDLE1_AUTO_GPT10_FLAG (1 << 11) +#define CORE_CM_AUTOIDLE1_AUTO_GPT11_FLAG (1 << 12) +#define CORE_CM_AUTOIDLE1_AUTO_UART1_FLAG (1 << 13) +#define CORE_CM_AUTOIDLE1_AUTO_UART2_FLAG (1 << 14) +#define CORE_CM_AUTOIDLE1_AUTO_I2C1_FLAG (1 << 15) +#define CORE_CM_AUTOIDLE1_AUTO_I2C2_FLAG (1 << 16) +#define CORE_CM_AUTOIDLE1_AUTO_I2C3_FLAG (1 << 17) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI1_FLAG (1 << 18) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI2_FLAG (1 << 19) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI3_FLAG (1 << 20) +#define CORE_CM_AUTOIDLE1_AUTO_MCSPI4_FLAG (1 << 21) +#define CORE_CM_AUTOIDLE1_AUTO_HDQ_FLAG (1 << 22) +#define CORE_CM_AUTOIDLE1_AUTO_MMC1_FLAG (1 << 24) +#define CORE_CM_AUTOIDLE1_AUTO_MMC2_FLAG (1 << 25) +#define CORE_CM_AUTOIDLE1_AUTO_ICR_FLAG (1 << 29) +#define CORE_CM_AUTOIDLE1_AUTO_MMC3_FLAG (1 << 30) + + ioport32_t reserved3; + ioport32_t autoidle3; +#define CORE_CM_AUTOIDLE3_AUTO_USBTLL_FLAG (1 << 2) + + PADD32; + ioport32_t clksel; +#define CORE_CM_CLKSEL_CLKSEL_L3_MASK (0x3 << 0) +#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 (0x1 << 0) +#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2 (0x2 << 0) +#define CORE_CM_CLKSEL_CLKSEL_L4_MASK (0x3 << 2) +#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED1 (0x1 << 2) +#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED2 (0x2 << 2) +#define CORE_CM_CLKSEL_CLKSEL_96M_MASK (0x3 << 12) +#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED1 (0x1 << 12) +#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED2 (0x2 << 12) +#define CORE_CM_CLKSEL_CLKSEL_GPT10_FLAG (1 << 6) +#define CORE_CM_CLKSEL_CLKSEL_GPT11_FLAG (1 << 7) + + PADD32; + ioport32_t clkstctrl; +#define CORE_CM_CLKCTRL_CLKCTRL_L3_MASK (0x3 << 0) +#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_EN (0x0 << 0) +#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_DIS (0x3 << 0) +#define CORE_CM_CLKCTRL_CLKCTRL_L4_MASK (0x3 << 2) +#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_EN (0x0 << 2) +#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_DIS (0x3 << 2) + + const ioport32_t clkstst; +#define CORE_CM_CLKSTST_CLKACTIVITY_L3_FLAG (1 << 0) +#define CORE_CM_CLKSTST_CLKACTIVITY_L4_FLAG (1 << 1) +} core_cm_regs_t; + +#endif +/** + * @} + */ Index: uspace/drv/infrastructure/rootamdm37x/cm/usbhost.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/cm/usbhost.h (revision 150a271898ef7efbc0fcad8d33cfafa0104fdb78) +++ uspace/drv/infrastructure/rootamdm37x/cm/usbhost.h (revision 150a271898ef7efbc0fcad8d33cfafa0104fdb78) @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2012 Jan Vesely + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup amdm37xdrvusbhostcm + * @{ + */ +/** @file + * @brief USBHOST Clock Management IO register structure. + */ +#ifndef AMDM37x_USBHOST_CM_H +#define AMDM37x_USBHOST_CM_H +#include +#include + +/* AM/DM37x TRM p.447 */ +#define USBHOST_CM_BASE_ADDRESS 0x48005400 +#define USBHOST_CM_SIZE 8192 + +typedef struct { + ioport32_t fclken; +#define USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG (1 << 0) +#define USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG (1 << 1) + + PADD32[3]; + ioport32_t iclken; +#define USBHOST_CM_ICLKEN_EN_USBHOST (1 << 0) + + PADD32[3]; + const ioport32_t idlest; +#define USBHOST_CM_IDLEST_ST_USBHOST_STDBY_FLAG (1 << 0) +#define USBHOST_CM_IDLEST_ST_USBHOST_IDLE_FLAG (1 << 1) + + PADD32[3]; + ioport32_t autoidle; +#define USBHOST_CM_AUTOIDLE_AUTO_USBHOST_FLAG (1 << 0) + + PADD32[4]; + ioport32_t sleepdep; +#define USBHOST_CM_SLEEPDEP_EN_MPU_FLAG (1 << 1) +#define USBHOST_CM_SLEEPDEP_EN_IVA2_FLAG (1 << 2) + + ioport32_t clkstctrl; +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_MASK (0x3 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_DIS (0x0 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_SLEEP (0x1 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_WAKEUP (0x2 << 0) +#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_EN (0x3 << 0) + + ioport32_t clkstst; +#define USBHOST_CM_CLKSTCTRL_CLKSTST_CLKACTIVITY_USBHOST (1 << 0) +} usbhost_cm_regs_t; + +#endif +/** + * @} + */ + Index: uspace/drv/infrastructure/rootamdm37x/core_cm.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/core_cm.h (revision f5ffc9a1bd3617efdb275ac8185b46800cc10b07) +++ (revision ) @@ -1,188 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvcorecm - * @{ - */ -/** @file - * @brief CORE Clock Management IO register structure. - */ -#ifndef AMDM37x_CORE_CM_H -#define AMDM37x_CORE_CM_H -#include -#include - -/* AM/DM37x TRM p.447 */ -#define CORE_CM_BASE_ADDRESS 0x48004a00 -#define CORE_CM_SIZE 8192 - -typedef struct { - ioport32_t fclken1; -#define CORE_CM_FCLKEN1_EN_MCBSP1_FLAG (1 << 9) -#define CORE_CM_FCLKEN1_EN_MCBSP5_FLAG (1 << 10) -#define CORE_CM_FCLKEN1_EN_GPT10_FLAG (1 << 11) -#define CORE_CM_FCLKEN1_EN_GPT11_FLAG (1 << 12) -#define CORE_CM_FCLKEN1_EN_UART1_FLAG (1 << 13) -#define CORE_CM_FCLKEN1_EN_UART2_FLAG (1 << 14) -#define CORE_CM_FCLKEN1_EN_I2C1_FLAG (1 << 15) -#define CORE_CM_FCLKEN1_EN_I2C2_FLAG (1 << 16) -#define CORE_CM_FCLKEN1_EN_I2C3_FLAG (1 << 17) -#define CORE_CM_FCLKEN1_EN_MCSPI1_FLAG (1 << 18) -#define CORE_CM_FCLKEN1_EN_MCSPI2_FLAG (1 << 19) -#define CORE_CM_FCLKEN1_EN_MCSPI3_FLAG (1 << 20) -#define CORE_CM_FCLKEN1_EN_MCSPI4_FLAG (1 << 21) -#define CORE_CM_FCLKEN1_EN_HDQ_FLAG (1 << 22) -#define CORE_CM_FCLKEN1_EN_MMC1_FLAG (1 << 24) -#define CORE_CM_FCLKEN1_EN_MMC2_FLAG (1 << 25) -#define CORE_CM_FCLKEN1_EN_MMC3_FLAG (1 << 30) - - PADD32; - ioport32_t fclken3; -#define CORE_CM_FCLKEN3_EN_TS_FLAG (1 << 1) -#define CORE_CM_FCLKEN3_EN_USBTLL_FLAG (1 << 2) - - PADD32; - ioport32_t iclken1; -#define CORE_CM_ICLKEN1_EN_SDRC_FLAG (1 << 1) -#define CORE_CM_ICLKEN1_EN_HSOTGUSB_FLAG (1 << 4) -#define CORE_CM_ICLKEN1_EN_SCMCTRL_FLAG (1 << 6) -#define CORE_CM_ICLKEN1_EN_MAILBOXES_FLAG (1 << 7) -#define CORE_CM_ICLKEN1_EN_MCBSP1_FLAG (1 << 9) -#define CORE_CM_ICLKEN1_EN_MCBSP5_FLAG (1 << 10) -#define CORE_CM_ICLKEN1_EN_GPT10_FLAG (1 << 11) -#define CORE_CM_ICLKEN1_EN_GPT11_FLAG (1 << 12) -#define CORE_CM_ICLKEN1_EN_UART1_FLAG (1 << 13) -#define CORE_CM_ICLKEN1_EN_UART2_FLAG (1 << 14) -#define CORE_CM_ICLKEN1_EN_I2C1_FLAG (1 << 15) -#define CORE_CM_ICLKEN1_EN_I2C2_FLAG (1 << 16) -#define CORE_CM_ICLKEN1_EN_I2C3_FLAG (1 << 17) -#define CORE_CM_ICLKEN1_EN_MCSPI1_FLAG (1 << 18) -#define CORE_CM_ICLKEN1_EN_MCSPI2_FLAG (1 << 19) -#define CORE_CM_ICLKEN1_EN_MCSPI3_FLAG (1 << 20) -#define CORE_CM_ICLKEN1_EN_MCSPI4_FLAG (1 << 21) -#define CORE_CM_ICLKEN1_EN_HDQ_FLAG (1 << 22) -#define CORE_CM_ICLKEN1_EN_MMC1_FLAG (1 << 24) -#define CORE_CM_ICLKEN1_EN_MMC2_FLAG (1 << 25) -#define CORE_CM_ICLKEN1_EN_ICR_FLAG (1 << 29) -#define CORE_CM_ICLKEN1_EN_MMC3_FLAG (1 << 30) - - ioport32_t reserved1; - ioport32_t iclken3; -#define CORE_CM_ICLKEN3_EN_USBTLL_FLAG (1 << 2) - - PADD32; - const ioport32_t idlest1; -#define CORE_CM_IDLEST1_ST_SDRC_FLAG (1 << 1) -#define CORE_CM_IDLEST1_ST_SDMA_FLAG (1 << 2) -#define CORE_CM_IDLEST1_ST_HSOTGUSB_STBY_FLAG (1 << 4) -#define CORE_CM_IDLEST1_ST_HSOTGUSB_IDLE_FLAG (1 << 5) -#define CORE_CM_IDLEST1_ST_SCMCTRL_FLAG (1 << 6) -#define CORE_CM_IDLEST1_ST_MAILBOXES_FLAG (1 << 7) -#define CORE_CM_IDLEST1_ST_MCBSP1_FLAG (1 << 9) -#define CORE_CM_IDLEST1_ST_MCBSP5_FLAG (1 << 10) -#define CORE_CM_IDLEST1_ST_GPT10_FLAG (1 << 11) -#define CORE_CM_IDLEST1_ST_GPT11_FLAG (1 << 12) -#define CORE_CM_IDLEST1_ST_UART1_FLAG (1 << 13) -#define CORE_CM_IDLEST1_ST_UART2_FLAG (1 << 14) -#define CORE_CM_IDLEST1_ST_I2C1_FLAG (1 << 15) -#define CORE_CM_IDLEST1_ST_I2C2_FLAG (1 << 16) -#define CORE_CM_IDLEST1_ST_I2C3_FLAG (1 << 17) -#define CORE_CM_IDLEST1_ST_MCSPI1_FLAG (1 << 18) -#define CORE_CM_IDLEST1_ST_MCSPI2_FLAG (1 << 19) -#define CORE_CM_IDLEST1_ST_MCSPI3_FLAG (1 << 20) -#define CORE_CM_IDLEST1_ST_MCSPI4_FLAG (1 << 21) -#define CORE_CM_IDLEST1_ST_HDQ_FLAG (1 << 22) -#define CORE_CM_IDLEST1_ST_MMC1_FLAG (1 << 24) -#define CORE_CM_IDLEST1_ST_MMC2_FLAG (1 << 25) -#define CORE_CM_IDLEST1_ST_ICR_FLAG (1 << 29) -#define CORE_CM_IDLEST1_ST_MMC3_FLAG (1 << 30) - - const ioport32_t reserved2; - const ioport32_t idlest3; -#define CORE_CM_IDLEST3_ST_USBTLL_FLAG (1 << 2) - - PADD32; - ioport32_t autoidle1; -#define CORE_CM_AUTOIDLE1_AUTO_HSOTGUSB_FLAG (1 << 4) -#define CORE_CM_AUTOIDLE1_AUTO_SCMCTRL_FLAG (1 << 6) -#define CORE_CM_AUTOIDLE1_AUTO_MAILBOXES_FLAG (1 << 7) -#define CORE_CM_AUTOIDLE1_AUTO_MCBSP1_FLAG (1 << 9) -#define CORE_CM_AUTOIDLE1_AUTO_MCBSP5_FLAG (1 << 10) -#define CORE_CM_AUTOIDLE1_AUTO_GPT10_FLAG (1 << 11) -#define CORE_CM_AUTOIDLE1_AUTO_GPT11_FLAG (1 << 12) -#define CORE_CM_AUTOIDLE1_AUTO_UART1_FLAG (1 << 13) -#define CORE_CM_AUTOIDLE1_AUTO_UART2_FLAG (1 << 14) -#define CORE_CM_AUTOIDLE1_AUTO_I2C1_FLAG (1 << 15) -#define CORE_CM_AUTOIDLE1_AUTO_I2C2_FLAG (1 << 16) -#define CORE_CM_AUTOIDLE1_AUTO_I2C3_FLAG (1 << 17) -#define CORE_CM_AUTOIDLE1_AUTO_MCSPI1_FLAG (1 << 18) -#define CORE_CM_AUTOIDLE1_AUTO_MCSPI2_FLAG (1 << 19) -#define CORE_CM_AUTOIDLE1_AUTO_MCSPI3_FLAG (1 << 20) -#define CORE_CM_AUTOIDLE1_AUTO_MCSPI4_FLAG (1 << 21) -#define CORE_CM_AUTOIDLE1_AUTO_HDQ_FLAG (1 << 22) -#define CORE_CM_AUTOIDLE1_AUTO_MMC1_FLAG (1 << 24) -#define CORE_CM_AUTOIDLE1_AUTO_MMC2_FLAG (1 << 25) -#define CORE_CM_AUTOIDLE1_AUTO_ICR_FLAG (1 << 29) -#define CORE_CM_AUTOIDLE1_AUTO_MMC3_FLAG (1 << 30) - - ioport32_t reserved3; - ioport32_t autoidle3; -#define CORE_CM_AUTOIDLE3_AUTO_USBTLL_FLAG (1 << 2) - - PADD32; - ioport32_t clksel; -#define CORE_CM_CLKSEL_CLKSEL_L3_MASK (0x3 << 0) -#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED1 (0x1 << 0) -#define CORE_CM_CLKSEL_CLKSEL_L3_DIVIDED2 (0x2 << 0) -#define CORE_CM_CLKSEL_CLKSEL_L4_MASK (0x3 << 2) -#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED1 (0x1 << 2) -#define CORE_CM_CLKSEL_CLKSEL_L4_DIVIDED2 (0x2 << 2) -#define CORE_CM_CLKSEL_CLKSEL_96M_MASK (0x3 << 12) -#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED1 (0x1 << 12) -#define CORE_CM_CLKSEL_CLKSEL_96M_DIVIDED2 (0x2 << 12) -#define CORE_CM_CLKSEL_CLKSEL_GPT10_FLAG (1 << 6) -#define CORE_CM_CLKSEL_CLKSEL_GPT11_FLAG (1 << 7) - - PADD32; - ioport32_t clkstctrl; -#define CORE_CM_CLKCTRL_CLKCTRL_L3_MASK (0x3 << 0) -#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_EN (0x0 << 0) -#define CORE_CM_CLKCTRL_CLKCTRL_L3_AUTO_DIS (0x3 << 0) -#define CORE_CM_CLKCTRL_CLKCTRL_L4_MASK (0x3 << 2) -#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_EN (0x0 << 2) -#define CORE_CM_CLKCTRL_CLKCTRL_L4_AUTO_DIS (0x3 << 2) - - const ioport32_t clkstst; -#define CORE_CM_CLKSTST_CLKACTIVITY_L3_FLAG (1 << 0) -#define CORE_CM_CLKSTST_CLKACTIVITY_L4_FLAG (1 << 1) -} core_cm_regs_t; - -#endif -/** - * @} - */ Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c =================================================================== --- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c (revision f5ffc9a1bd3617efdb275ac8185b46800cc10b07) +++ uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c (revision 150a271898ef7efbc0fcad8d33cfafa0104fdb78) @@ -48,7 +48,7 @@ #include "uhh.h" #include "usbtll.h" -#include "core_cm.h" -#include "clock_control_cm.h" -#include "usbhost_cm.h" +#include "cm/core.h" +#include "cm/clock_control.h" +#include "cm/usbhost.h" #define NAME "rootamdm37x" Index: uspace/drv/infrastructure/rootamdm37x/usbhost_cm.h =================================================================== --- uspace/drv/infrastructure/rootamdm37x/usbhost_cm.h (revision f5ffc9a1bd3617efdb275ac8185b46800cc10b07) +++ (revision ) @@ -1,82 +1,0 @@ -/* - * Copyright (c) 2012 Jan Vesely - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup amdm37xdrvusbhostcm - * @{ - */ -/** @file - * @brief USBHOST Clock Management IO register structure. - */ -#ifndef AMDM37x_USBHOST_CM_H -#define AMDM37x_USBHOST_CM_H -#include -#include - -/* AM/DM37x TRM p.447 */ -#define USBHOST_CM_BASE_ADDRESS 0x48005400 -#define USBHOST_CM_SIZE 8192 - -typedef struct { - ioport32_t fclken; -#define USBHOST_CM_FCLKEN_EN_USBHOST1_FLAG (1 << 0) -#define USBHOST_CM_FCLKEN_EN_USBHOST2_FLAG (1 << 1) - - PADD32[3]; - ioport32_t iclken; -#define USBHOST_CM_ICLKEN_EN_USBHOST (1 << 0) - - PADD32[3]; - const ioport32_t idlest; -#define USBHOST_CM_IDLEST_ST_USBHOST_STDBY_FLAG (1 << 0) -#define USBHOST_CM_IDLEST_ST_USBHOST_IDLE_FLAG (1 << 1) - - PADD32[3]; - ioport32_t autoidle; -#define USBHOST_CM_AUTOIDLE_AUTO_USBHOST_FLAG (1 << 0) - - PADD32[4]; - ioport32_t sleepdep; -#define USBHOST_CM_SLEEPDEP_EN_MPU_FLAG (1 << 1) -#define USBHOST_CM_SLEEPDEP_EN_IVA2_FLAG (1 << 2) - - ioport32_t clkstctrl; -#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_MASK (0x3 << 0) -#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_DIS (0x0 << 0) -#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_SLEEP (0x1 << 0) -#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_SUPERVISED_WAKEUP (0x2 << 0) -#define USBHOST_CM_CLKSTCTRL_CLKSTCTRL_USBHOST_AUTO_EN (0x3 << 0) - - ioport32_t clkstst; -#define USBHOST_CM_CLKSTCTRL_CLKSTST_CLKACTIVITY_USBHOST (1 << 0) -} usbhost_cm_regs_t; - -#endif -/** - * @} - */ -