Index: arch/mips32/src/interrupt.c
===================================================================
--- arch/mips32/src/interrupt.c	(revision 74fbedb410d3a5939cd2f14e3a15cd2654eb37cf)
+++ arch/mips32/src/interrupt.c	(revision 12fdd28585b2ba4f5b93eb59aac420a9be27d2de)
@@ -77,7 +77,24 @@
 }
 
+/* TODO: This is SMP unsafe!!! */
+static unsigned long nextcount;
+/** Start hardware clock */
+static void timer_start(void)
+{
+	nextcount = cp0_compare_value + cp0_count_read();
+	cp0_compare_write(nextcount);
+}
+
 static void timer_exception(int n, istate_t *istate)
 {
-	cp0_compare_write(cp0_count_read() + cp0_compare_value); 
+	unsigned long drift;
+
+	drift = cp0_count_read() - nextcount;
+	while (drift > cp0_compare_value) {
+		drift -= cp0_compare_value;
+		CPU->missed_clock_ticks++;
+	}
+	nextcount = cp0_count_read() + cp0_compare_value - drift;
+	cp0_compare_write(nextcount);
 	clock();
 }
@@ -101,4 +118,5 @@
 	int_register(0, "swint0", swint0);
 	int_register(1, "swint1", swint1);
+	timer_start();
 }
 
Index: arch/mips32/src/mips32.c
===================================================================
--- arch/mips32/src/mips32.c	(revision 74fbedb410d3a5939cd2f14e3a15cd2654eb37cf)
+++ arch/mips32/src/mips32.c	(revision 12fdd28585b2ba4f5b93eb59aac420a9be27d2de)
@@ -81,6 +81,4 @@
 	/* Initialize dispatch table */
 	exception_init();
-	interrupt_init();
-
 	arc_init();
 
@@ -90,4 +88,5 @@
 	memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
 
+	interrupt_init();
 	/*
 	 * Switch to BEV normal level so that exception vectors point to the kernel.
@@ -100,13 +99,9 @@
 	 */
 	cp0_mask_all_int();
+
 	/*
 	 * Unmask hardware clock interrupt.
 	 */
 	cp0_unmask_int(TIMER_IRQ);
-
-	/*
-	 * Start hardware clock.
-	 */
-	cp0_compare_write(cp0_compare_value + cp0_count_read());
 
 	console_init();