Index: kernel/arch/mips32/include/context_offset.h
===================================================================
--- kernel/arch/mips32/include/context_offset.h	(revision 27ba40f4ccf8a83c8054ca09330d1974972b838c)
+++ kernel/arch/mips32/include/context_offset.h	(revision 12f9f0d0827e1f7c54cf26d56ffabf49e22936f7)
@@ -63,119 +63,126 @@
 #ifdef __ASM__
 
+#ifdef KERNEL
+
 #include <arch/asm/regname.h>
 
-# ctx: address of the structure with saved context
+#else /* KERNEL */
+
+#include <libarch/regname.h>
+
+#endif /* KERNEL */
+
+/* ctx: address of the structure with saved context */
 .macro CONTEXT_SAVE_ARCH_CORE ctx:req
-	sw $s0,OFFSET_S0(\ctx)
-	sw $s1,OFFSET_S1(\ctx)
-	sw $s2,OFFSET_S2(\ctx)
-	sw $s3,OFFSET_S3(\ctx)
-	sw $s4,OFFSET_S4(\ctx)
-	sw $s5,OFFSET_S5(\ctx)
-	sw $s6,OFFSET_S6(\ctx)
-	sw $s7,OFFSET_S7(\ctx)
-	sw $s8,OFFSET_S8(\ctx)
-	sw $gp,OFFSET_GP(\ctx)
-
+	sw $s0, OFFSET_S0(\ctx)
+	sw $s1, OFFSET_S1(\ctx)
+	sw $s2, OFFSET_S2(\ctx)
+	sw $s3, OFFSET_S3(\ctx)
+	sw $s4, OFFSET_S4(\ctx)
+	sw $s5, OFFSET_S5(\ctx)
+	sw $s6, OFFSET_S6(\ctx)
+	sw $s7, OFFSET_S7(\ctx)
+	sw $s8, OFFSET_S8(\ctx)
+	sw $gp, OFFSET_GP(\ctx)
+	
 #ifndef KERNEL
-	sw $k1,OFFSET_TLS(\ctx)
-
+	sw $k1, OFFSET_TLS(\ctx)
+	
 #ifdef CONFIG_FPU
-	mfc1 $t0,$20
+	mfc1 $t0, $20
 	sw $t0, OFFSET_F20(\ctx)
-
-	mfc1 $t0,$21
+	
+	mfc1 $t0, $21
 	sw $t0, OFFSET_F21(\ctx)
-
-	mfc1 $t0,$22
+	
+	mfc1 $t0, $22
 	sw $t0, OFFSET_F22(\ctx)
-
-	mfc1 $t0,$23
+	
+	mfc1 $t0, $23
 	sw $t0, OFFSET_F23(\ctx)
-
-	mfc1 $t0,$24
+	
+	mfc1 $t0, $24
 	sw $t0, OFFSET_F24(\ctx)
-
-	mfc1 $t0,$25
+	
+	mfc1 $t0, $25
 	sw $t0, OFFSET_F25(\ctx)
-
-	mfc1 $t0,$26
+	
+	mfc1 $t0, $26
 	sw $t0, OFFSET_F26(\ctx)
-
-	mfc1 $t0,$27
+	
+	mfc1 $t0, $27
 	sw $t0, OFFSET_F27(\ctx)
-
-	mfc1 $t0,$28
+	
+	mfc1 $t0, $28
 	sw $t0, OFFSET_F28(\ctx)
-
-	mfc1 $t0,$29
+	
+	mfc1 $t0, $29
 	sw $t0, OFFSET_F29(\ctx)
 	
-	mfc1 $t0,$30
+	mfc1 $t0, $30
 	sw $t0, OFFSET_F30(\ctx)
 #endif /* CONFIG_FPU */
 #endif /* KERNEL */
-
-	sw $ra,OFFSET_PC(\ctx)
-	sw $sp,OFFSET_SP(\ctx)
+	
+	sw $ra, OFFSET_PC(\ctx)
+	sw $sp, OFFSET_SP(\ctx)
 .endm
 
-# ctx: address of the structure with saved context
+/* ctx: address of the structure with saved context */
 .macro CONTEXT_RESTORE_ARCH_CORE ctx:req
-	lw $s0,OFFSET_S0(\ctx)
-	lw $s1,OFFSET_S1(\ctx)
-	lw $s2,OFFSET_S2(\ctx)
-	lw $s3,OFFSET_S3(\ctx)
-	lw $s4,OFFSET_S4(\ctx)
-	lw $s5,OFFSET_S5(\ctx)
-	lw $s6,OFFSET_S6(\ctx)
-	lw $s7,OFFSET_S7(\ctx)
-	lw $s8,OFFSET_S8(\ctx)
-	lw $gp,OFFSET_GP(\ctx)
+	lw $s0, OFFSET_S0(\ctx)
+	lw $s1, OFFSET_S1(\ctx)
+	lw $s2, OFFSET_S2(\ctx)
+	lw $s3, OFFSET_S3(\ctx)
+	lw $s4, OFFSET_S4(\ctx)
+	lw $s5, OFFSET_S5(\ctx)
+	lw $s6, OFFSET_S6(\ctx)
+	lw $s7, OFFSET_S7(\ctx)
+	lw $s8, OFFSET_S8(\ctx)
+	lw $gp, OFFSET_GP(\ctx)
 #ifndef KERNEL
-	lw $k1,OFFSET_TLS(\ctx)
-
+	lw $k1, OFFSET_TLS(\ctx)
+	
 #ifdef CONFIG_FPU
 	lw $t0, OFFSET_F20(\ctx)
-	mtc1 $t0,$20
-
+	mtc1 $t0, $20
+	
 	lw $t0, OFFSET_F21(\ctx)
-	mtc1 $t0,$21
-
+	mtc1 $t0, $21
+	
 	lw $t0, OFFSET_F22(\ctx)
-	mtc1 $t0,$22
-
+	mtc1 $t0, $22
+	
 	lw $t0, OFFSET_F23(\ctx)
-	mtc1 $t0,$23
-
+	mtc1 $t0, $23
+	
 	lw $t0, OFFSET_F24(\ctx)
-	mtc1 $t0,$24
-
+	mtc1 $t0, $24
+	
 	lw $t0, OFFSET_F25(\ctx)
-	mtc1 $t0,$25
-
+	mtc1 $t0, $25
+	
 	lw $t0, OFFSET_F26(\ctx)
-	mtc1 $t0,$26
-
+	mtc1 $t0, $26
+	
 	lw $t0, OFFSET_F27(\ctx)
-	mtc1 $t0,$27
-
+	mtc1 $t0, $27
+	
 	lw $t0, OFFSET_F28(\ctx)
-	mtc1 $t0,$28
-
+	mtc1 $t0, $28
+	
 	lw $t0, OFFSET_F29(\ctx)
-	mtc1 $t0,$29
-
+	mtc1 $t0, $29
+	
 	lw $t0, OFFSET_F30(\ctx)
-	mtc1 $t0,$30
+	mtc1 $t0, $30
 #endif /* CONFIG_FPU */
 #endif /* KERNEL */
-
-	lw $ra,OFFSET_PC(\ctx)
-	lw $sp,OFFSET_SP(\ctx)
+	
+	lw $ra, OFFSET_PC(\ctx)
+	lw $sp, OFFSET_SP(\ctx)
 .endm
 
-#endif
-
+#endif /* __ASM__ */
 
 #endif
Index: kernel/arch/mips32/include/cp0.h
===================================================================
--- kernel/arch/mips32/include/cp0.h	(revision 27ba40f4ccf8a83c8054ca09330d1974972b838c)
+++ kernel/arch/mips32/include/cp0.h	(revision 12f9f0d0827e1f7c54cf26d56ffabf49e22936f7)
@@ -36,10 +36,4 @@
 #define KERN_mips32_CP0_H_
 
-#ifdef KERNEL
-#include <typedefs.h>
-#else
-#include <sys/types.h>
-#endif
-
 #define cp0_status_ie_enabled_bit     (1 << 0)
 #define cp0_status_exl_exception_bit  (1 << 1)
@@ -49,33 +43,50 @@
 #define cp0_status_fpu_bit            (1 << 29)
 
-#define cp0_status_im_shift		8
-#define cp0_status_im_mask              0xff00
+#define cp0_status_im_shift  8
+#define cp0_status_im_mask   0xff00
 
-#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
-#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
+#define cp0_cause_excno(cause)   ((cause >> 2) & 0x1f)
+#define cp0_cause_coperr(cause)  ((cause >> 28) & 0x3)
 
-#define fpu_cop_id 1
+#define fpu_cop_id  1
 
 /*
  * Magic value for use in msim.
  */
-#define cp0_compare_value 		100000
+#define cp0_compare_value  100000
 
-#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
-#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
-#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1 << (cp0_status_im_shift + (it))))
-#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1 << (cp0_status_im_shift + (it))))
+#define cp0_mask_all_int() \
+	cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
 
-#define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \
-  { \
-      uint32_t retval; \
-      asm volatile ("mfc0 %0, $" #reg : "=r"(retval)); \
-      return retval; \
-  }
+#define cp0_unmask_all_int() \
+	cp0_status_write(cp0_status_read() | cp0_status_im_mask)
 
-#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \
- { \
-    asm volatile ("mtc0 %0, $" #reg : : "r"(val) ); \
- }
+#define cp0_mask_int(it) \
+	cp0_status_write(cp0_status_read() & ~(1 << (cp0_status_im_shift + (it))))
+
+#define cp0_unmask_int(it) \
+	cp0_status_write(cp0_status_read() | (1 << (cp0_status_im_shift + (it))))
+
+#define GEN_READ_CP0(nm, reg) \
+	static inline uint32_t cp0_ ##nm##_read(void) \
+	{ \
+		uint32_t retval; \
+		\
+		asm volatile ( \
+			"mfc0 %0, $" #reg \
+			: "=r"(retval) \
+		); \
+		\
+		return retval; \
+	}
+
+#define GEN_WRITE_CP0(nm, reg) \
+	static inline void cp0_ ##nm##_write(uint32_t val) \
+	{ \
+		asm volatile ( \
+			"mtc0 %0, $" #reg \
+			:: "r"(val) \
+		); \
+	}
 
 GEN_READ_CP0(index, 0);
Index: kernel/arch/mips32/include/istate.h
===================================================================
--- kernel/arch/mips32/include/istate.h	(revision 27ba40f4ccf8a83c8054ca09330d1974972b838c)
+++ kernel/arch/mips32/include/istate.h	(revision 12f9f0d0827e1f7c54cf26d56ffabf49e22936f7)
@@ -36,13 +36,15 @@
 #define KERN_mips32_ISTATE_H_
 
+#include <trace.h>
+
+#ifdef KERNEL
+
 #include <arch/cp0.h>
 
-#ifdef KERNEL
-#include <typedefs.h>
-#include <trace.h>
-#else
-#include <sys/types.h>
-#define NO_TRACE
-#endif
+#else /* KERNEL */
+
+#include <libarch/cp0.h>
+
+#endif /* KERNEL */
 
 typedef struct istate {
Index: kernel/arch/mips32/include/mm/frame.h
===================================================================
--- kernel/arch/mips32/include/mm/frame.h	(revision 27ba40f4ccf8a83c8054ca09330d1974972b838c)
+++ kernel/arch/mips32/include/mm/frame.h	(revision 12f9f0d0827e1f7c54cf26d56ffabf49e22936f7)
@@ -39,5 +39,4 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
-#ifdef KERNEL
 #ifndef __ASM__
 
@@ -46,5 +45,4 @@
 
 #endif /* __ASM__ */
-#endif /* KERNEL */
 
 #endif
Index: kernel/arch/mips32/include/mm/page.h
===================================================================
--- kernel/arch/mips32/include/mm/page.h	(revision 27ba40f4ccf8a83c8054ca09330d1974972b838c)
+++ kernel/arch/mips32/include/mm/page.h	(revision 12f9f0d0827e1f7c54cf26d56ffabf49e22936f7)
@@ -49,6 +49,4 @@
 #	define PA2KA(x)	((x) + 0x80000000)
 #endif
-
-#ifdef KERNEL
 
 /*
@@ -188,6 +186,4 @@
 #endif /* __ASM__ */
 
-#endif /* KERNEL */
-
 #endif