Changes in / [fa33ac4:119b46e] in mainline
- Files:
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- 8 added
- 6 deleted
- 31 edited
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HelenOS.config
rfa33ac4 r119b46e 44 44 % Machine type 45 45 @ "msim" MSIM 46 @ "b gxemul" GXEmulbig endian47 @ "l gxemul" GXEmullittle endian46 @ "bmalta" MIPS Malta Development Board big endian 47 @ "lmalta" MIPS Malta Development Board little endian 48 48 ! [PLATFORM=mips32] MACHINE (choice) 49 49 … … 115 115 ! [PLATFORM=arm32&(PROCESSOR=cortex_a8)] PROCESSOR_ARCH (choice) 116 116 117 % CPU type 118 @ "R4000" MIPS R4000 119 ! [PLATFORM=mips32&MACHINE=msim] PROCESSOR (choice) 120 121 % CPU type 122 @ "4Kc" MIPS 4Kc 123 ! [PLATFORM=mips32&(MACHINE=bmalta|MACHINE=lmalta)] PROCESSOR (choice) 124 117 125 % RAM disk format 118 126 @ "tmpfs" TMPFS image … … 193 201 % User space architecture 194 202 @ "mips32" 195 ! [PLATFORM=mips32&(MACHINE=msim|MACHINE=l gxemul)] UARCH (choice)203 ! [PLATFORM=mips32&(MACHINE=msim|MACHINE=lmalta)] UARCH (choice) 196 204 197 205 % User space architecture 198 206 @ "mips32eb" 199 ! [PLATFORM=mips32&MACHINE=b gxemul] UARCH (choice)207 ! [PLATFORM=mips32&MACHINE=bmalta] UARCH (choice) 200 208 201 209 % User space architecture … … 270 278 271 279 % Image format 272 @ "e coff"273 ! [PLATFORM=mips32&(MACHINE=b gxemul|MACHINE=lgxemul)] IMAGE (choice)280 @ "elf" 281 ! [PLATFORM=mips32&(MACHINE=bmalta|MACHINE=lmalta)] IMAGE (choice) 274 282 275 283 % Image format … … 360 368 ! [PLATFORM=ia32|PLATFORM=amd64|PLATFORM=ia64|PLATFORM=sparc64] CONFIG_FPU (y) 361 369 362 % FPU support363 ! [PLATFORM=mips32&(MACHINE=lgxemul|MACHINE=bgxemul)] CONFIG_FPU (y)364 365 370 ## armv7 made fpu hardware compulsory 366 371 % FPU support … … 447 452 @ "generic" Monitor or serial line 448 453 @ "none" No output device 449 ! [PLATFORM=ia32|PLATFORM=amd64|PLATFORM=sparc64|PLATFORM=ppc32|(PLATFORM=ia64&MACHINE=i460GX)|(PLATFORM=mips32&MACHINE=msim)|(PLATFORM=mips64&MACHINE=msim)] CONFIG_HID_OUT (choice) 450 451 % Output device class 452 @ "generic" Monitor or serial line 453 @ "monitor" Monitor 454 @ "serial" Serial line 455 @ "none" No output device 456 ! [PLATFORM=mips32&(MACHINE=bgxemul|MACHINE=lgxemul)] CONFIG_HID_OUT (choice) 454 ! [PLATFORM=ia32|PLATFORM=amd64|PLATFORM=sparc64|PLATFORM=ppc32|(PLATFORM=ia64&MACHINE=i460GX)|(PLATFORM=mips32&(MACHINE=msim|MACHINE=bmalta|MACHINE=lmalta))|(PLATFORM=mips64&MACHINE=msim)] CONFIG_HID_OUT (choice) 457 455 458 456 % PC keyboard support … … 465 463 ! [(CONFIG_HID_IN=generic|CONFIG_HID_IN=keyboard)&PLATFORM=arm32&MACHINE=integratorcp] CONFIG_PC_KBD (y/n) 466 464 467 % Support for msim /GXemulkeyboard468 ! [CONFIG_HID_IN=generic& (PLATFORM=mips32|PLATFORM=mips64)] CONFIG_MIPS_KBD (y/n)469 470 % Support for msim /GXemulprinter471 ! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)& (PLATFORM=mips32|PLATFORM=mips64)] CONFIG_MIPS_PRN (y/n)465 % Support for msim keyboard 466 ! [CONFIG_HID_IN=generic&MACHINE=msim] CONFIG_MSIM_KBD (y/n) 467 468 % Support for msim printer 469 ! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=serial)&MACHINE=msim] CONFIG_MSIM_PRN (y/n) 472 470 473 471 % Support for VIA CUDA controller … … 511 509 512 510 % Dummy serial line input 513 ! [CONFIG_M IPS_KBD=y|CONFIG_ARM_KBD=y] CONFIG_DSRLNIN (y)511 ! [CONFIG_MSIM_KBD=y|CONFIG_ARM_KBD=y] CONFIG_DSRLNIN (y) 514 512 515 513 % Dummy serial line output 516 ! [CONFIG_M IPS_PRN=y|CONFIG_ARM_PRN=y] CONFIG_DSRLNOUT (y)514 ! [CONFIG_MSIM_PRN=y|CONFIG_ARM_PRN=y] CONFIG_DSRLNOUT (y) 517 515 518 516 % Serial line input module … … 527 525 % Framebuffer support 528 526 ! [CONFIG_HID_OUT=generic&(PLATFORM=ia32|PLATFORM=amd64|PLATFORM=ppc32)] CONFIG_FB (y/n) 529 530 % Framebuffer support531 ! [(CONFIG_HID_OUT=generic|CONFIG_HID_OUT=monitor)&PLATFORM=mips32&(MACHINE=lgxemul|MACHINE=bgxemul)] CONFIG_FB (y/n)532 527 533 528 % Framebuffer support -
boot/arch/mips32/Makefile.inc
rfa33ac4 r119b46e 29 29 BFD_ARCH = mips 30 30 BITS = 32 31 EXTRA_CFLAGS = -msoft-float -mno-abicalls -G 0 -fno-zero-initialized-in-bss -m ips3 -mabi=3231 EXTRA_CFLAGS = -msoft-float -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mabi=32 32 32 33 RD_SRVS_NON_ESSENTIAL += \34 $(USPACE_PATH)/srv/bd/gxe_bd/gxe_bd35 36 ifeq ($(MACHINE),lgxemul)37 BFD_NAME = elf32-tradlittlemips38 BFD_OUTPUT = ecoff-littlemips39 ENDIANESS = LE40 endif41 ifeq ($(MACHINE),bgxemul)42 BFD_NAME = elf32-tradbigmips43 BFD_OUTPUT = ecoff-bigmips44 ENDIANESS = BE45 endif46 33 ifeq ($(MACHINE),msim) 47 34 BFD_NAME = elf32-tradlittlemips 48 35 BFD_OUTPUT = binary 49 36 ENDIANESS = LE 37 EXTRA_CFLAGS += -march=r4000 50 38 endif 39 ifeq ($(MACHINE),lmalta) 40 BFD_NAME = elf32-tradlittlemips 41 BFD_OUTPUT = elf32-tradlittlemips 42 ENDIANESS = LE 43 EXTRA_CFLAGS += -march=4kc 44 endif 45 ifeq ($(MACHINE),bmalta) 46 BFD_NAME = elf32-tradbigmips 47 BFD_OUTPUT = elf32-tradbigmips 48 ENDIANESS = BE 49 EXTRA_CFLAGS += -march=4kc 50 endif 51 51 52 52 53 SOURCES = \ -
boot/arch/mips32/_link.ld.in
rfa33ac4 r119b46e 2 2 3 3 SECTIONS { 4 #if defined(MACHINE_msim) 4 5 . = 0xbfc00000; 6 #elif defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 7 . = 0x80103000; 8 #endif 5 9 .text : { 6 10 *(BOOTSTRAP); -
boot/arch/mips32/include/arch.h
rfa33ac4 r119b46e 33 33 #define PAGE_SIZE (1 << PAGE_WIDTH) 34 34 35 #if defined(MACHINE_msim) 35 36 #define CPUMAP_OFFSET 0x00001000 36 37 #define STACK_OFFSET 0x00002000 … … 41 42 #define MSIM_VIDEORAM_ADDRESS 0xb0000000 42 43 #define MSIM_DORDER_ADDRESS 0xb0000100 44 #endif 45 46 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 47 #define CPUMAP_OFFSET 0x00100000 48 #define STACK_OFFSET 0x00101000 49 #define BOOTINFO_OFFSET 0x00102000 50 #define BOOT_OFFSET 0x00200000 51 #define LOADER_OFFSET 0x00103000 52 53 #define YAMON_SUBR_BASE PA2KA(0x1fc00500) 54 #define YAMON_SUBR_PRINT_COUNT (YAMON_SUBR_BASE + 0x4) 55 #endif 43 56 44 57 #ifndef __ASM__ 45 58 #define PA2KA(addr) (((uintptr_t) (addr)) + 0x80000000) 59 #define PA2KSEG(addr) (((uintptr_t) (addr)) + 0xa0000000) 60 #define KA2PA(addr) (((uintptr_t) (addr)) - 0x80000000) 46 61 #define KSEG2PA(addr) (((uintptr_t) (addr)) - 0xa0000000) 47 62 #else -
boot/arch/mips32/include/types.h
rfa33ac4 r119b46e 47 47 48 48 typedef struct { 49 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 50 uint32_t sdram_size; 51 #endif 49 52 uint32_t cpumap; 50 53 size_t cnt; -
boot/arch/mips32/src/asm.S
rfa33ac4 r119b46e 51 51 and $a0, $a1, $a0 52 52 mtc0 $a0, $status 53 54 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 55 /* 56 * Remember the size of the SDRAM in bootinfo. 57 */ 58 la $a0, PA2KA(BOOTINFO_OFFSET) 59 sw $a3, 0($a0) 60 #endif 53 61 54 62 /* -
boot/arch/mips32/src/main.c
rfa33ac4 r119b46e 65 65 for (i = 0; i < COMPONENTS; i++) 66 66 printf(" %p|%p: %s image (%zu/%zu bytes)\n", components[i].start, 67 (void *) KSEG2PA(components[i].start), components[i].name, 68 components[i].inflated, components[i].size); 67 (uintptr_t) components[i].start >= PA2KSEG(0) ? 68 (void *) KSEG2PA(components[i].start) : 69 (void *) KA2PA(components[i].start), 70 components[i].name, components[i].inflated, 71 components[i].size); 69 72 70 73 void *dest[COMPONENTS]; … … 93 96 94 97 for (i = cnt; i > 0; i--) { 98 #ifdef MACHINE_msim 95 99 void *tail = dest[i - 1] + components[i].inflated; 96 100 if (tail >= ((void *) PA2KA(LOADER_OFFSET))) { … … 99 103 halt(); 100 104 } 105 #endif 101 106 102 107 printf("%s ", components[i - 1].name); -
boot/arch/mips32/src/putchar.c
rfa33ac4 r119b46e 32 32 #include <str.h> 33 33 34 #ifdef PUTCHAR_ADDRESS 35 #undef PUTCHAR_ADDRESS 36 #endif 37 38 #if defined(MACHINE_msim) 39 #define _putchar(ch) msim_putchar((ch)) 40 static void msim_putchar(const wchar_t ch) 41 { 42 *((char *) MSIM_VIDEORAM_ADDRESS) = ch; 43 } 44 #endif 45 46 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 47 #define _putchar(ch) yamon_putchar((ch)) 48 typedef void (**yamon_print_count_ptr_t)(uint32_t, const char *, uint32_t); 49 yamon_print_count_ptr_t yamon_print_count = 50 (yamon_print_count_ptr_t) YAMON_SUBR_PRINT_COUNT; 51 52 static void yamon_putchar(const wchar_t wch) 53 { 54 const char ch = (char) wch; 55 56 (*yamon_print_count)(0, &ch, 1); 57 } 58 #endif 59 34 60 void putchar(const wchar_t ch) 35 61 { 36 62 if (ascii_check(ch)) 37 *((char *) MSIM_VIDEORAM_ADDRESS) = ch;63 _putchar(ch); 38 64 else 39 *((char *) MSIM_VIDEORAM_ADDRESS) = U_SPECIAL;65 _putchar(U_SPECIAL); 40 66 } 67 -
kernel/arch/mips32/Makefile.inc
rfa33ac4 r119b46e 29 29 BFD_ARCH = mips 30 30 BFD = binary 31 GCC_CFLAGS += -msoft-float -mno-abicalls -G 0 -fno-zero-initialized-in-bss -m ips3 -mabi=3231 GCC_CFLAGS += -msoft-float -mno-abicalls -G 0 -fno-zero-initialized-in-bss -mabi=32 32 32 33 33 BITS = 32 … … 36 36 # 37 37 38 ifeq ($(MACHINE),lgxemul)39 BFD_NAME = elf32-tradlittlemips40 ENDIANESS = LE41 endif42 ifeq ($(MACHINE),bgxemul)43 BFD_NAME = elf32-tradbigmips44 ENDIANESS = BE45 GCC_CFLAGS += -D__BE__46 endif47 38 ifeq ($(MACHINE),msim) 48 39 BFD_NAME = elf32-tradlittlemips 49 40 ENDIANESS = LE 41 GCC_CFLAGS += -march=r4000 42 endif 43 ifeq ($(MACHINE),bmalta) 44 BFD_NAME = elf32-tradbigmips 45 ENDIANESS = BE 46 GCC_CFLAGS += -D__BE__ -march=4kc 47 endif 48 ifeq ($(MACHINE),lmalta) 49 BFD_NAME = elf32-tradlittlemips 50 ENDIANESS = LE 51 GCC_CFLAGS += -march=4kc 50 52 endif 51 53 … … 69 71 arch/$(KARCH)/src/fpu_context.c \ 70 72 arch/$(KARCH)/src/ddi/ddi.c \ 71 arch/$(KARCH)/src/smp/dorder.c \ 72 arch/$(KARCH)/src/smp/smp.c 73 arch/$(KARCH)/src/smp/smp.c \ 74 arch/$(KARCH)/src/machine_func.c 75 76 ifeq ($(MACHINE),msim) 77 ARCH_SOURCES += \ 78 arch/$(KARCH)/src/smp/dorder.c 79 endif 80 81 ifeq ($(MACHINE),$(filter lmalta bmalta,$(MACHINE))) 82 ARCH_SOURCES += arch/$(KARCH)/src/mach/malta/malta.c 83 endif 84 ifeq ($(MACHINE),msim) 85 ARCH_SOURCES += arch/$(KARCH)/src/mach/msim/msim.c 86 endif 87 -
kernel/arch/mips32/_link.ld.in
rfa33ac4 r119b46e 10 10 #define mips mips 11 11 12 #if defined(MACHINE_msim) 12 13 #define KERNEL_LOAD_ADDRESS 0x80100000 14 #endif 15 16 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 17 #define KERNEL_LOAD_ADDRESS 0x80200000 18 #endif 13 19 14 20 OUTPUT_ARCH(mips) -
kernel/arch/mips32/include/arch/arch.h
rfa33ac4 r119b46e 44 44 extern size_t cpu_count; 45 45 46 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 47 extern size_t sdram_size; 48 #endif 49 46 50 typedef struct { 47 51 void *addr; … … 51 55 52 56 typedef struct { 57 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 58 uint32_t sdram_size; 59 #endif 53 60 uint32_t cpumap; 54 61 size_t cnt; -
kernel/arch/mips32/include/arch/cp0.h
rfa33ac4 r119b46e 45 45 #define cp0_status_im_shift 8 46 46 #define cp0_status_im_mask 0xff00 47 48 #define cp0_cause_ip_shift 8 49 #define cp0_cause_ip_mask 0xff00 47 50 48 51 #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) -
kernel/arch/mips32/include/arch/mm/tlb.h
rfa33ac4 r119b46e 41 41 #include <trace.h> 42 42 43 #if defined(PROCESSOR_R4000) 43 44 #define TLB_ENTRY_COUNT 48 45 #define TLB_INDEX_BITS 6 46 #elif defined(PROCESSOR_4Kc) 47 #define TLB_ENTRY_COUNT 16 48 #define TLB_INDEX_BITS 4 49 #else 50 #error Please define TLB_ENTRY_COUNT for the target processor. 51 #endif 44 52 45 #define TLB_WIRED 1 46 #define TLB_KSTACK_WIRED_INDEX 0 53 #define TLB_WIRED 0 47 54 48 55 #define TLB_PAGE_MASK_4K (0x000 << 13) … … 112 119 #ifdef __BE__ 113 120 unsigned p : 1; 114 unsigned : 25;115 unsigned index : 6;121 unsigned : 32 - TLB_INDEX_BITS - 1; 122 unsigned index : TLB_INDEX_BITS; 116 123 #else 117 unsigned index : 6;118 unsigned : 25;124 unsigned index : TLB_INDEX_BITS; 125 unsigned : 32 - TLB_INDEX_BITS - 1; 119 126 unsigned p : 1; 120 127 #endif -
kernel/arch/mips32/src/exception.c
rfa33ac4 r119b46e 165 165 static void interrupt_exception(unsigned int n, istate_t *istate) 166 166 { 167 uint32_t ip; 168 uint32_t im; 169 167 170 /* Decode interrupt number and process the interrupt */ 168 uint32_t cause = (cp0_cause_read() >> 8) & 0xff; 171 ip = (cp0_cause_read() & cp0_cause_ip_mask) >> cp0_cause_ip_shift; 172 im = (cp0_status_read() & cp0_status_im_mask) >> cp0_status_im_shift; 169 173 170 174 unsigned int i; 171 175 for (i = 0; i < 8; i++) { 172 if (cause & (1 << i)) { 176 177 /* 178 * The interrupt could only occur if it is unmasked in the 179 * status register. On the other hand, an interrupt can be 180 * apparently pending even if it is masked, so we need to 181 * check both the masked and pending interrupts. 182 */ 183 if (im & ip & (1 << i)) { 173 184 irq_t *irq = irq_dispatch_and_lock(i); 174 185 if (irq) { -
kernel/arch/mips32/src/interrupt.c
rfa33ac4 r119b46e 45 45 #define IRQ_COUNT 8 46 46 #define TIMER_IRQ 7 47 48 #ifdef MACHINE_msim 47 49 #define DORDER_IRQ 5 50 #endif 48 51 49 52 function virtual_timer_fnc = NULL; 50 53 static irq_t timer_irq; 54 55 #ifdef MACHINE_msim 51 56 static irq_t dorder_irq; 57 #endif 52 58 53 59 // TODO: This is SMP unsafe!!! … … 151 157 } 152 158 159 #ifdef MACHINE_msim 153 160 static irq_ownership_t dorder_claim(irq_t *irq) 154 161 { … … 160 167 dorder_ipi_ack(1 << dorder_cpuid()); 161 168 } 169 #endif 162 170 163 171 /* Initialize basic tables for exception dispatching */ … … 176 184 cp0_unmask_int(TIMER_IRQ); 177 185 186 #ifdef MACHINE_msim 178 187 irq_initialize(&dorder_irq); 179 188 dorder_irq.devno = device_assign_devno(); … … 184 193 185 194 cp0_unmask_int(DORDER_IRQ); 195 #endif 186 196 } 187 197 -
kernel/arch/mips32/src/mips32.c
rfa33ac4 r119b46e 41 41 #include <memstr.h> 42 42 #include <userspace.h> 43 #include <console/console.h>44 43 #include <syscall/syscall.h> 45 44 #include <sysinfo/sysinfo.h> 46 45 #include <arch/debug.h> 47 46 #include <arch/debugger.h> 48 #include <arch/drivers/msim.h> 49 #include <genarch/fb/fb.h> 50 #include <genarch/drivers/dsrln/dsrlnin.h> 51 #include <genarch/drivers/dsrln/dsrlnout.h> 52 #include <genarch/srln/srln.h> 47 #include <arch/machine_func.h> 53 48 54 49 /* Size of the code jumping to the exception handler code … … 70 65 71 66 size_t cpu_count = 0; 67 68 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 69 size_t sdram_size = 0; 70 #endif 72 71 73 72 /** Performs mips32-specific initialization before main_bsp() is called. */ … … 88 87 cpu_count++; 89 88 } 89 90 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 91 sdram_size = bootinfo->sdram_size; 92 #endif 93 94 /* Initialize machine_ops pointer. */ 95 machine_ops_init(); 90 96 } 91 97 … … 124 130 { 125 131 interrupt_init(); 126 127 #ifdef CONFIG_FB 128 /* GXemul framebuffer */ 129 fb_properties_t gxemul_prop = { 130 .addr = 0x12000000, 131 .offset = 0, 132 .x = 640, 133 .y = 480, 134 .scan = 1920, 135 .visual = VISUAL_RGB_8_8_8, 136 }; 137 138 outdev_t *fbdev = fb_init(&gxemul_prop); 139 if (fbdev) 140 stdout_wire(fbdev); 141 #endif 142 143 #ifdef CONFIG_MIPS_PRN 144 outdev_t *dsrlndev = dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS); 145 if (dsrlndev) 146 stdout_wire(dsrlndev); 147 #endif 132 133 machine_init(); 134 machine_output_init(); 148 135 } 149 136 … … 158 145 void arch_post_smp_init(void) 159 146 { 160 static const char *platform;161 162 147 /* Set platform name. */ 163 #ifdef MACHINE_msim 164 platform = "msim"; 165 #endif 166 #ifdef MACHINE_bgxemul 167 platform = "gxemul"; 168 #endif 169 #ifdef MACHINE_lgxemul 170 platform = "gxemul"; 171 #endif 172 sysinfo_set_item_data("platform", NULL, (void *) platform, 173 str_size(platform)); 174 175 #ifdef CONFIG_MIPS_KBD 176 /* 177 * Initialize the msim/GXemul keyboard port. Then initialize the serial line 178 * module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts. 179 */ 180 dsrlnin_instance_t *dsrlnin_instance 181 = dsrlnin_init((dsrlnin_t *) MSIM_KBD_ADDRESS, MSIM_KBD_IRQ); 182 if (dsrlnin_instance) { 183 srln_instance_t *srln_instance = srln_init(); 184 if (srln_instance) { 185 indev_t *sink = stdin_wire(); 186 indev_t *srln = srln_wire(srln_instance, sink); 187 dsrlnin_wire(dsrlnin_instance, srln); 188 cp0_unmask_int(MSIM_KBD_IRQ); 189 } 190 } 191 192 /* 193 * This is the necessary evil until the userspace driver is entirely 194 * self-sufficient. 195 */ 196 sysinfo_set_item_val("kbd", NULL, true); 197 sysinfo_set_item_val("kbd.inr", NULL, MSIM_KBD_IRQ); 198 sysinfo_set_item_val("kbd.address.physical", NULL, 199 PA2KA(MSIM_KBD_ADDRESS)); 200 #endif 148 sysinfo_set_item_data("platform", NULL, 149 (void *) machine_get_platform_name(), 150 str_size(machine_get_platform_name())); 151 152 machine_input_init(); 201 153 } 202 154 -
kernel/arch/mips32/src/mm/frame.c
rfa33ac4 r119b46e 40 40 #include <mm/asid.h> 41 41 #include <config.h> 42 #ifdef MACHINE_msim 42 43 #include <arch/drivers/msim.h> 44 #endif 45 #include <arch/arch.h> 43 46 #include <print.h> 44 47 … … 84 87 return false; 85 88 #endif 86 87 #if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul) 88 /* gxemul devices */ 89 if (overlaps(frame << ZERO_PAGE_WIDTH, ZERO_PAGE_SIZE, 90 0x10000000, MiB2SIZE(256))) 89 90 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 91 if (frame >= (sdram_size >> ZERO_PAGE_WIDTH)) 91 92 return false; 92 93 #endif … … 225 226 if (ZERO_PAGE_VALUE != 0xdeadbeef) 226 227 avail = false; 227 #if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul)228 else {229 ZERO_PAGE_VALUE_KSEG1(frame) = 0xaabbccdd;230 if (ZERO_PAGE_VALUE_KSEG1(frame) != 0xaabbccdd)231 avail = false;232 }233 #endif234 228 } 235 229 } … … 247 241 /* Blacklist interrupt vector frame */ 248 242 frame_mark_unavailable(0, 1); 243 244 #if defined(MACHINE_lmalta) || defined(MACHINE_bmalta) 245 /* Blacklist memory regions used by YAMON. 246 * 247 * The YAMON User's Manual vaguely says the following physical addresses 248 * are taken by YAMON: 249 * 250 * 0x1000 YAMON functions 251 * 0x5000 YAMON code 252 * 253 * These addresses overlap with the beginning of the SDRAM so we need to 254 * make sure they cannot be allocated. 255 * 256 * The User's Manual unfortunately does not say where does the SDRAM 257 * portion used by YAMON end. 258 * 259 * Looking into the YAMON 02.21 sources, it looks like the first free 260 * address is computed dynamically and depends on the size of the YAMON 261 * image. From the YAMON binary, it appears to be 0xc0d50 or roughly 262 * 772 KiB for that particular version. 263 * 264 * Linux is linked to 1MiB which seems to be a safe bet and a reasonable 265 * upper bound for memory taken by YAMON. We will use it too. 266 */ 267 frame_mark_unavailable(0, 1024 * 1024 / FRAME_SIZE); 268 #endif 249 269 250 270 /* Cleanup */ -
kernel/arch/mips32/src/mm/tlb.c
rfa33ac4 r119b46e 48 48 #include <symtab.h> 49 49 50 static pte_t *find_mapping_and_check(uintptr_t, int, istate_t *); 50 #define PFN_SHIFT 12 51 #define VPN_SHIFT 12 52 #define ADDR2VPN(a) ((a) >> VPN_SHIFT) 53 #define ADDR2VPN2(a) (ADDR2VPN((a)) >> 1) 54 #define VPN2ADDR(vpn) ((vpn) << VPN_SHIFT) 55 #define VPN22ADDR(vpn2) (VPN2ADDR(vpn2) << 1) 56 #define PFN2ADDR(pfn) ((pfn) << PFN_SHIFT) 57 58 #define BANK_SELECT_BIT(a) (((a) >> PAGE_WIDTH) & 1) 59 51 60 52 61 /** Initialize TLB. … … 84 93 { 85 94 entry_lo_t lo; 86 entry_hi_t hi;87 asid_t asid;88 95 uintptr_t badvaddr; 96 uintptr_t page; 89 97 pte_t *pte; 90 98 91 99 badvaddr = cp0_badvaddr_read(); 92 asid = AS->asid;93 94 pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate);95 if (pte ) {100 page = ALIGN_DOWN(badvaddr, PAGE_SIZE); 101 102 pte = page_mapping_find(AS, page, true); 103 if (pte && pte->p) { 96 104 /* 97 105 * Record access to PTE. … … 99 107 pte->a = 1; 100 108 101 tlb_prepare_entry_hi(&hi, asid, badvaddr);102 109 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, 103 110 pte->cacheable, pte->pfn); … … 106 113 * New entry is to be inserted into TLB 107 114 */ 108 cp0_entry_hi_write(hi.value); 109 if ((badvaddr / PAGE_SIZE) % 2 == 0) { 115 if (BANK_SELECT_BIT(badvaddr) == 0) { 110 116 cp0_entry_lo0_write(lo.value); 111 117 cp0_entry_lo1_write(0); … … 116 122 cp0_pagemask_write(TLB_PAGE_MASK_16K); 117 123 tlbwr(); 118 } 124 return; 125 } 126 127 (void) as_page_fault(page, PF_ACCESS_READ, istate); 119 128 } 120 129 … … 125 134 void tlb_invalid(istate_t *istate) 126 135 { 136 entry_lo_t lo; 127 137 tlb_index_t index; 128 138 uintptr_t badvaddr; 129 entry_lo_t lo; 130 entry_hi_t hi; 139 uintptr_t page; 131 140 pte_t *pte; 132 133 badvaddr = cp0_badvaddr_read();134 141 135 142 /* 136 143 * Locate the faulting entry in TLB. 137 144 */ 138 hi.value = cp0_entry_hi_read();139 tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);140 cp0_entry_hi_write(hi.value);141 145 tlbp(); 142 146 index.value = cp0_index_read(); 143 147 148 #if defined(PROCESSOR_4Kc) 149 /* 150 * This can happen on a 4Kc when Status.EXL is 1 and there is a TLB miss. 151 * EXL is 1 when interrupts are disabled. The combination of a TLB miss 152 * and disabled interrupts is possible in copy_to/from_uspace(). 153 */ 154 if (index.p) { 155 tlb_refill(istate); 156 return; 157 } 158 #endif 159 144 160 ASSERT(!index.p); 145 161 146 pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate); 147 if (pte) { 162 badvaddr = cp0_badvaddr_read(); 163 page = ALIGN_DOWN(badvaddr, PAGE_SIZE); 164 165 pte = page_mapping_find(AS, page, true); 166 if (pte && pte->p) { 148 167 /* 149 168 * Read the faulting TLB entry. … … 162 181 * The entry is to be updated in TLB. 163 182 */ 164 if ( (badvaddr / PAGE_SIZE) % 2== 0)183 if (BANK_SELECT_BIT(badvaddr) == 0) 165 184 cp0_entry_lo0_write(lo.value); 166 185 else 167 186 cp0_entry_lo1_write(lo.value); 168 cp0_pagemask_write(TLB_PAGE_MASK_16K);169 187 tlbwi(); 170 } 188 return; 189 } 190 191 (void) as_page_fault(page, PF_ACCESS_READ, istate); 171 192 } 172 193 … … 177 198 void tlb_modified(istate_t *istate) 178 199 { 200 entry_lo_t lo; 179 201 tlb_index_t index; 180 202 uintptr_t badvaddr; 181 entry_lo_t lo; 182 entry_hi_t hi; 203 uintptr_t page; 183 204 pte_t *pte; 184 205 185 206 badvaddr = cp0_badvaddr_read(); 207 page = ALIGN_DOWN(badvaddr, PAGE_SIZE); 186 208 187 209 /* 188 210 * Locate the faulting entry in TLB. 189 211 */ 190 hi.value = cp0_entry_hi_read();191 tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);192 cp0_entry_hi_write(hi.value);193 212 tlbp(); 194 213 index.value = cp0_index_read(); 195 214 196 215 /* 197 * Fail if the entry is not in TLB. 216 * Emit warning if the entry is not in TLB. 217 * 218 * We do not assert on this because this could be a manifestation of 219 * an emulator bug, such as QEMU Bug #1128935: 220 * https://bugs.launchpad.net/qemu/+bug/1128935 198 221 */ 199 ASSERT(!index.p); 200 201 pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate); 202 if (pte) { 222 if (index.p) { 223 printf("%s: TLBP failed in exception handler (badvaddr=%#" 224 PRIxn ", ASID=%d).\n", __func__, badvaddr, 225 AS ? AS->asid : -1); 226 return; 227 } 228 229 pte = page_mapping_find(AS, page, true); 230 if (pte && pte->p && pte->w) { 203 231 /* 204 232 * Read the faulting TLB entry. … … 218 246 * The entry is to be updated in TLB. 219 247 */ 220 if ( (badvaddr / PAGE_SIZE) % 2== 0)248 if (BANK_SELECT_BIT(badvaddr) == 0) 221 249 cp0_entry_lo0_write(lo.value); 222 250 else 223 251 cp0_entry_lo1_write(lo.value); 224 cp0_pagemask_write(TLB_PAGE_MASK_16K);225 252 tlbwi(); 226 } 227 } 228 229 /** Try to find PTE for faulting address. 230 * 231 * @param badvaddr Faulting virtual address. 232 * @param access Access mode that caused the fault. 233 * @param istate Pointer to interrupted state. 234 * 235 * @return PTE on success, NULL otherwise. 236 */ 237 pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate) 238 { 239 entry_hi_t hi; 240 pte_t *pte; 241 242 hi.value = cp0_entry_hi_read(); 243 244 ASSERT(hi.asid == AS->asid); 245 246 /* 247 * Check if the mapping exists in page tables. 248 */ 249 pte = page_mapping_find(AS, badvaddr, true); 250 if (pte && pte->p && (pte->w || access != PF_ACCESS_WRITE)) { 251 /* 252 * Mapping found in page tables. 253 * Immediately succeed. 254 */ 255 return pte; 256 } 257 258 /* 259 * Mapping not found in page tables. 260 * Resort to higher-level page fault handler. 261 */ 262 if (as_page_fault(badvaddr, access, istate) == AS_PF_OK) { 263 pte = page_mapping_find(AS, badvaddr, true); 264 ASSERT(pte && pte->p); 265 ASSERT(pte->w || access != PF_ACCESS_WRITE); 266 return pte; 267 } 268 269 return NULL; 253 return; 254 } 255 256 (void) as_page_fault(page, PF_ACCESS_WRITE, istate); 270 257 } 271 258 … … 284 271 void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr) 285 272 { 286 hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2); 273 hi->value = 0; 274 hi->vpn2 = ADDR2VPN2(ALIGN_DOWN(addr, PAGE_SIZE)); 287 275 hi->asid = asid; 288 276 } … … 291 279 void tlb_print(void) 292 280 { 293 page_mask_t mask ;294 entry_lo_t lo0, lo 1;281 page_mask_t mask, mask_save; 282 entry_lo_t lo0, lo0_save, lo1, lo1_save; 295 283 entry_hi_t hi, hi_save; 296 284 unsigned int i; 297 285 298 286 hi_save.value = cp0_entry_hi_read(); 299 300 printf("[nr] [asid] [vpn2] [mask] [gvdc] [pfn ]\n"); 287 lo0_save.value = cp0_entry_lo0_read(); 288 lo1_save.value = cp0_entry_lo1_read(); 289 mask_save.value = cp0_pagemask_read(); 290 291 printf("[nr] [asid] [vpn2 ] [mask] [gvdc] [pfn ]\n"); 301 292 302 293 for (i = 0; i < TLB_ENTRY_COUNT; i++) { … … 309 300 lo1.value = cp0_entry_lo1_read(); 310 301 311 printf("%-4u %-6u % #6x %#6x %1u%1u%1u%1u %#6x\n",312 i, hi.asid, hi.vpn2, mask.mask,313 lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn);314 printf(" %1u%1u%1u%1u %#6x\n",315 lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);302 printf("%-4u %-6u %0#10x %-#6x %1u%1u%1u%1u %0#10x\n", 303 i, hi.asid, VPN22ADDR(hi.vpn2), mask.mask, 304 lo0.g, lo0.v, lo0.d, lo0.c, PFN2ADDR(lo0.pfn)); 305 printf(" %1u%1u%1u%1u %0#10x\n", 306 lo1.g, lo1.v, lo1.d, lo1.c, PFN2ADDR(lo1.pfn)); 316 307 } 317 308 318 309 cp0_entry_hi_write(hi_save.value); 310 cp0_entry_lo0_write(lo0_save.value); 311 cp0_entry_lo1_write(lo1_save.value); 312 cp0_pagemask_write(mask_save.value); 319 313 } 320 314 … … 322 316 void tlb_invalidate_all(void) 323 317 { 324 ipl_t ipl;325 318 entry_lo_t lo0, lo1; 326 319 entry_hi_t hi_save; 327 320 int i; 328 321 322 ASSERT(interrupts_disabled()); 323 329 324 hi_save.value = cp0_entry_hi_read(); 330 ipl = interrupts_disable();331 325 332 326 for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) { … … 346 340 } 347 341 348 interrupts_restore(ipl);349 342 cp0_entry_hi_write(hi_save.value); 350 343 } … … 356 349 void tlb_invalidate_asid(asid_t asid) 357 350 { 358 ipl_t ipl;359 351 entry_lo_t lo0, lo1; 360 352 entry_hi_t hi, hi_save; 361 353 int i; 362 354 355 ASSERT(interrupts_disabled()); 363 356 ASSERT(asid != ASID_INVALID); 364 357 365 358 hi_save.value = cp0_entry_hi_read(); 366 ipl = interrupts_disable();367 359 368 360 for (i = 0; i < TLB_ENTRY_COUNT; i++) { … … 386 378 } 387 379 388 interrupts_restore(ipl);389 380 cp0_entry_hi_write(hi_save.value); 390 381 } … … 400 391 { 401 392 unsigned int i; 402 ipl_t ipl;403 393 entry_lo_t lo0, lo1; 404 394 entry_hi_t hi, hi_save; 405 395 tlb_index_t index; 396 397 ASSERT(interrupts_disabled()); 406 398 407 399 if (asid == ASID_INVALID) … … 409 401 410 402 hi_save.value = cp0_entry_hi_read(); 411 ipl = interrupts_disable();412 403 413 404 for (i = 0; i < cnt + 1; i += 2) { 414 hi.value = 0;415 405 tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE); 416 406 cp0_entry_hi_write(hi.value); … … 439 429 } 440 430 441 interrupts_restore(ipl);442 431 cp0_entry_hi_write(hi_save.value); 443 432 } -
kernel/arch/mips64/src/mips64.c
rfa33ac4 r119b46e 46 46 #include <arch/debug.h> 47 47 #include <arch/debugger.h> 48 #ifdef MACHINE_msim 48 49 #include <arch/drivers/msim.h> 50 #endif 49 51 #include <genarch/fb/fb.h> 50 52 #include <genarch/drivers/dsrln/dsrlnin.h> … … 125 127 interrupt_init(); 126 128 127 #ifdef CONFIG_M IPS_PRN129 #ifdef CONFIG_MSIM_PRN 128 130 outdev_t *dsrlndev = dsrlnout_init((ioport8_t *) MSIM_KBD_ADDRESS); 129 131 if (dsrlndev) … … 151 153 str_size(platform)); 152 154 153 #ifdef CONFIG_MIPS_KBD 154 /* 155 * Initialize the msim/GXemul keyboard port. Then initialize the serial line 156 * module and connect it to the msim/GXemul keyboard. Enable keyboard interrupts. 155 #ifdef CONFIG_MSIM_KBD 156 /* 157 * Initialize the msim keyboard port. Then initialize the serial line 158 * module and connect it to the msim keyboard. Enable keyboard 159 * interrupts. 157 160 */ 158 161 dsrlnin_instance_t *dsrlnin_instance -
kernel/arch/mips64/src/mm/frame.c
rfa33ac4 r119b46e 40 40 #include <mm/asid.h> 41 41 #include <config.h> 42 #ifdef MACHINE_msim 42 43 #include <arch/drivers/msim.h> 44 #endif 43 45 #include <print.h> 44 46 -
kernel/generic/include/mm/tlb.h
rfa33ac4 r119b46e 73 73 extern void tlb_shootdown_ipi_recv(void); 74 74 #else 75 #define tlb_shootdown_start(w, x, y, z) (0)76 #define tlb_shootdown_finalize(i) ( (i) =(i));75 #define tlb_shootdown_start(w, x, y, z) interrupts_disable() 76 #define tlb_shootdown_finalize(i) (interrupts_restore(i)); 77 77 #define tlb_shootdown_ipi_recv() 78 78 #endif /* CONFIG_SMP */ -
release/Makefile
rfa33ac4 r119b46e 33 33 34 34 PROFILES = amd64 arm32/integratorcp arm32/gta02 arm32/beagleboardxm ia32 \ 35 ia64/i460GX ia64/ski mips32/GXemul mips32/msim ppc32 \ 36 sparc64/ultra 35 ia64/i460GX ia64/ski mips32/msim ppc32 sparc64/ultra 37 36 38 37 BZR = bzr -
tools/autotool.py
rfa33ac4 r119b46e 676 676 common['CC_ARGS'].append("-mabi=32") 677 677 678 if ((config['MACHINE'] == " lgxemul") or (config['MACHINE'] == "msim")):678 if ((config['MACHINE'] == "msim") or (config['MACHINE'] == "lmalta")): 679 679 target = config['PLATFORM'] 680 680 gnu_target = "mipsel-linux-gnu" 681 681 682 if ( config['MACHINE'] == "bgxemul"):682 if ((config['MACHINE'] == "bmalta")): 683 683 target = "mips32eb" 684 684 gnu_target = "mips-linux-gnu" -
uspace/Makefile
rfa33ac4 r119b46e 93 93 srv/bd/sata_bd \ 94 94 srv/bd/file_bd \ 95 srv/bd/gxe_bd \96 95 srv/bd/rd \ 97 96 srv/bd/part/guid_part \ -
uspace/app/init/init.c
rfa33ac4 r119b46e 369 369 #ifdef CONFIG_START_BD 370 370 srv_start("/srv/ata_bd"); 371 srv_start("/srv/gxe_bd");372 371 #endif 373 372 -
uspace/lib/c/arch/mips32/Makefile.common
rfa33ac4 r119b46e 27 27 # 28 28 29 GCC_CFLAGS += -msoft-float -m ips3 -mabi=3229 GCC_CFLAGS += -msoft-float -mabi=32 30 30 BASE_LIBS += $(LIBSOFTFLOAT_PREFIX)/libsoftfloat.a 31 31 … … 34 34 BFD_ARCH = mips 35 35 BFD_NAME = elf32-tradlittlemips 36 37 ifeq ($(MACHINE),msim) 38 GCC_CFLAGS += -march=r4000 39 endif 40 41 ifeq ($(MACHINE),lmalta) 42 GCC_CFLAGS += -march=4kc 43 endif 44 -
uspace/lib/c/arch/mips32eb/Makefile.common
rfa33ac4 r119b46e 27 27 # 28 28 29 GCC_CFLAGS += -msoft-float -m ips3 -mabi=3229 GCC_CFLAGS += -msoft-float -mabi=32 30 30 BASE_LIBS += $(LIBSOFTFLOAT_PREFIX)/libsoftfloat.a 31 31 … … 34 34 BFD_ARCH = mips 35 35 BFD_NAME = elf32-tradbigmips 36 37 ifeq ($(MACHINE),bmalta) 38 GCC_CFLAGS += -march=4kc 39 endif 40 -
uspace/srv/hid/input/Makefile
rfa33ac4 r119b46e 39 39 port/adb_mouse.c \ 40 40 port/chardev.c \ 41 port/gxemul.c \42 41 port/msim.c \ 43 42 port/niagara.c \ … … 48 47 proto/mousedev.c \ 49 48 ctl/apple.c \ 50 ctl/gxe_fb.c \51 49 ctl/kbdev.c \ 52 50 ctl/pc.c \ -
uspace/srv/hid/input/input.c
rfa33ac4 r119b46e 440 440 kbd_add_dev(&msim_port, &stty_ctl); 441 441 #endif 442 #if (defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul)) && defined(CONFIG_FB)443 kbd_add_dev(&gxemul_port, &gxe_fb_ctl);444 #endif445 #if defined(MACHINE_lgxemul) || defined(MACHINE_bgxemul) && !defined(CONFIG_FB)446 kbd_add_dev(&gxemul_port, &stty_ctl);447 #endif448 442 #if defined(UARCH_ppc32) 449 443 kbd_add_dev(&adb_port, &apple_ctl); -
uspace/srv/hid/input/kbd_ctl.h
rfa33ac4 r119b46e 49 49 50 50 extern kbd_ctl_ops_t apple_ctl; 51 extern kbd_ctl_ops_t gxe_fb_ctl;52 51 extern kbd_ctl_ops_t kbdev_ctl; 53 52 extern kbd_ctl_ops_t pc_ctl; -
uspace/srv/hid/input/kbd_port.h
rfa33ac4 r119b46e 51 51 extern kbd_port_ops_t adb_port; 52 52 extern kbd_port_ops_t chardev_port; 53 extern kbd_port_ops_t gxemul_port;54 53 extern kbd_port_ops_t msim_port; 55 54 extern kbd_port_ops_t niagara_port;
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