Index: kernel/test/fpu/mips1/test.c
===================================================================
--- kernel/test/fpu/mips1/test.c	(revision 1167520724b9b526c27b67f2d4bc447ef626240c)
+++ kernel/test/fpu/mips1/test.c	(revision 1167520724b9b526c27b67f2d4bc447ef626240c)
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2005 Ondrej Palkovsky
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <print.h>
+#include <debug.h>
+#include <panic.h>
+
+#include <test.h>
+#include <atomic.h>
+#include <proc/thread.h>
+#include <time/delay.h>
+
+#include <arch.h>
+
+#define THREADS		50
+#define DELAY   	10000L
+#define ATTEMPTS        5
+
+static atomic_t threads_ok;
+static waitq_t can_start;
+
+static void testit1(void *data)
+{
+	int i;
+	int arg __attribute__((aligned(16))) = (int)((unative_t) data);
+	int after_arg __attribute__((aligned(16)));
+
+	thread_detach(THREAD);
+	
+	waitq_sleep(&can_start);
+
+	for (i = 0; i<ATTEMPTS; i++) {
+		__asm__ volatile (
+			"mtc1 %0,$1"
+			:"=r"(arg)
+			);
+
+		delay(DELAY);
+		__asm__ volatile (
+			"mfc1 %0, $1"
+			:"=r"(after_arg)
+			);
+		
+		if(arg != after_arg)
+			panic("General reg tid%d: arg(%d) != %d\n", 
+			      THREAD->tid, arg, after_arg);
+	}
+
+	atomic_inc(&threads_ok);
+}
+
+static void testit2(void *data)
+{
+	int i;
+	int arg __attribute__((aligned(16))) = (int)((unative_t) data);
+	int after_arg __attribute__((aligned(16)));
+
+	thread_detach(THREAD);
+
+	waitq_sleep(&can_start);
+
+	for (i = 0; i<ATTEMPTS; i++) {
+		__asm__ volatile (
+			"mtc1 %0,$1"
+			:"=r"(arg)
+			);
+
+		scheduler();
+		__asm__ volatile (
+			"mfc1 %0,$1"
+			:"=r"(after_arg)
+			);
+		
+		if(arg != after_arg)
+			panic("General reg tid%d: arg(%d) != %d\n", 
+			      THREAD->tid, arg, after_arg);
+	}
+
+	atomic_inc(&threads_ok);
+}
+
+
+void test(void)
+{
+	thread_t *t;
+	int i;
+
+	waitq_initialize(&can_start);
+
+	printf("MIPS test #1\n");
+	printf("Creating %d threads... ", THREADS);
+
+	for (i=0; i<THREADS/2; i++) {  
+		if (!(t = thread_create(testit1, (void *)((unative_t)i*2), TASK, 0, "testit1")))
+			panic("could not create thread\n");
+		thread_ready(t);
+		if (!(t = thread_create(testit2, (void *)((unative_t)i*2+1), TASK, 0, "testit2")))
+			panic("could not create thread\n");
+		thread_ready(t);
+	}
+
+	printf("ok\n");
+	
+	thread_sleep(1);
+	waitq_wakeup(&can_start, WAKEUP_ALL);
+
+	while (atomic_get(&threads_ok) != THREADS)
+		;
+		
+	printf("Test passed.\n");
+}