Index: kernel/arch/mips32/Makefile.inc =================================================================== --- kernel/arch/mips32/Makefile.inc (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/Makefile.inc (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,135 @@ +# +# Copyright (C) 2005 Martin Decky +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +## Toolchain configuration +# + +BFD_ARCH = mips +TARGET = mipsel-linux-gnu +TOOLCHAIN_DIR = /usr/local/mipsel/bin + +## Make some default assumptions +# + +ifndef MIPS_MACHINE + MIPS_MACHINE = msim +endif + +KERNEL_LOAD_ADDRESS = 0x80100000 +INIT_ADDRESS = 0x81000000 +INIT_SIZE = 262144 + +CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss + +DEFS += -D__32_BITS__ -DMACHINE=${MIPS_MACHINE} -DKERNEL_LOAD_ADDRESS=${KERNEL_LOAD_ADDRESS} -DINIT_ADDRESS=${INIT_ADDRESS} -DINIT_SIZE=${INIT_SIZE} + +## Compile with hierarchical page tables support. +# + +CONFIG_PAGE_PT = y +DEFS += -DCONFIG_PAGE_PT + +## Compile with support for address space identifiers. +# + +CONFIG_ASID = y +CONFIG_ASID_FIFO = y + +## Accepted MACHINEs +# + +ifeq ($(MIPS_MACHINE),indy) + # GCC 4.0.1 compiled for mipsEL has problems compiling in + # BigEndian mode with the swl/swr/lwl/lwr instructions. + # We have to compile it with mips-sgi-irix5 to get it right. + + BFD_NAME = elf32-bigmips + BFD = ecoff-bigmips --impure + TARGET = mips-sgi-irix5 + TOOLCHAIN_DIR = /usr/local/mips/bin + KERNEL_LOAD_ADDRESS = 0x88002000 + CFLAGS += -EB -DBIG_ENDIAN -DARCH_HAS_FPU -march=r4600 + INIT_ADDRESS = 0 + INIT_SIZE = 0 +endif +ifeq ($(MIPS_MACHINE),lgxemul) + BFD_NAME = elf32-tradlittlemips + BFD = binary + CFLAGS += -DFB_BIG_ENDIAN -DARCH_HAS_FPU -mips3 +endif +ifeq ($(MIPS_MACHINE),bgxemul) + BFD_NAME = elf32-bigmips + BFD = ecoff-bigmips + TARGET = mips-sgi-irix5 + TOOLCHAIN_DIR = /usr/local/mips/bin + CFLAGS += -EB -DBIG_ENDIAN -DARCH_HAS_FPU -mips3 + INIT_ADDRESS = 0x81800000 +endif +ifeq ($(MIPS_MACHINE),simics) + # SIMICS 4kc emulation is broken, although for instructions + # that do not bother us + + BFD_NAME = elf32-tradlittlemips + BFD = elf32-tradlittlemips + CFLAGS += -mhard-float -mips3 -DTLBCNT=16 + TLBCNT = 16 +endif +ifeq ($(MIPS_MACHINE),msim) + BFD_NAME = elf32-tradlittlemips + BFD = binary + CFLAGS += -mhard-float -mips3 +endif + +## Compile with support for software integer division. +# + +CONFIG_SOFTINT = y + + +ARCH_SOURCES = \ + arch/$(ARCH)/src/start.S \ + arch/$(ARCH)/src/context.S \ + arch/$(ARCH)/src/panic.S \ + arch/$(ARCH)/src/mips32.c \ + arch/$(ARCH)/src/dummy.S \ + arch/$(ARCH)/src/console.c \ + arch/$(ARCH)/src/asm.S \ + arch/$(ARCH)/src/exception.c \ + arch/$(ARCH)/src/interrupt.c \ + arch/$(ARCH)/src/cache.c \ + arch/$(ARCH)/src/debugger.c \ + arch/$(ARCH)/src/cpu/cpu.c \ + arch/$(ARCH)/src/mm/frame.c \ + arch/$(ARCH)/src/mm/page.c \ + arch/$(ARCH)/src/mm/tlb.c \ + arch/$(ARCH)/src/mm/as.c \ + arch/$(ARCH)/src/fpu_context.c \ + arch/$(ARCH)/src/ddi/ddi.c \ + arch/$(ARCH)/src/drivers/arc.c \ + arch/$(ARCH)/src/drivers/msim.c \ + arch/$(ARCH)/src/drivers/serial.c Index: kernel/arch/mips32/_link.ld.in =================================================================== --- kernel/arch/mips32/_link.ld.in (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/_link.ld.in (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,60 @@ +/* + * MIPS32 linker script + * + * kernel text + * kernel data + * + */ +#undef mips +#define mips mips + +OUTPUT_ARCH(mips) + +ENTRY(kernel_image_start) + +SECTIONS { + . = KERNEL_LOAD_ADDRESS; + .text : { + ktext_start = .; + *(.text); + ktext_end = .; + } + .data : { + kdata_start = .; + *(.data); /* initialized data */ + hardcoded_ktext_size = .; + LONG(ktext_end - ktext_start); + hardcoded_kdata_size = .; + LONG(kdata_end - kdata_start); + hardcoded_load_address = .; + LONG(KERNEL_LOAD_ADDRESS); + *(.rodata*); + *(.sdata); + *(.reginfo); + /* Unfortunately IRIX does not allow us + * to include this as a last section :-( + * BSS/SBSS addresses will be wrong */ + symbol_table = .; + *(symtab.*); + } + _gp = . + 0x8000; + .lit8 : { *(.lit8) } + .lit4 : { *(.lit4) } + .sbss : { + *(.sbss); + *(.scommon); + } + .bss : { + *(.bss); /* uninitialized static variables */ + *(COMMON); /* global variables */ + } + + kdata_end = .; + + /DISCARD/ : { + *(.mdebug*); + *(.pdr); + *(.comment); + *(.note); + } +} Index: kernel/arch/mips32/include/arch.h =================================================================== --- kernel/arch/mips32/include/arch.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/arch.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_ARCH_H__ +#define __mips32_ARCH_H__ + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/arg.h =================================================================== --- kernel/arch/mips32/include/arg.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/arg.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_ARG_H__ +#define __mips32_ARG_H__ + +#include + +/** + * va_arg macro for MIPS32 - problem is that 64 bit values must be aligned on an 8-byte boundary (32bit values not) + * To satisfy this, paddings must be sometimes inserted. + */ + +typedef uintptr_t va_list; + +#define va_start(ap, lst) \ + ((ap) = (va_list)&(lst) + sizeof(lst)) + +#define va_arg(ap, type) \ + (((type *)((ap) = (va_list)( (sizeof(type) <= 4) ? ((uintptr_t)((ap) + 2*4 - 1) & (~3)) : ((uintptr_t)((ap) + 2*8 -1) & (~7)) )))[-1]) + +#define va_copy(dst,src) ((dst)=(src)) + +#define va_end(ap) + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/asm.h =================================================================== --- kernel/arch/mips32/include/asm.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/asm.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_ASM_H__ +#define __mips32_ASM_H__ + +#include +#include +#include + + +static inline void cpu_sleep(void) +{ + /* Most of the simulators do not support */ +/* __asm__ volatile ("wait"); */ +} + +/** Return base address of current stack + * + * Return the base address of the current stack. + * The stack is assumed to be STACK_SIZE bytes long. + * The stack must start on page boundary. + */ +static inline uintptr_t get_stack_base(void) +{ + uintptr_t v; + + __asm__ volatile ("and %0, $29, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1))); + + return v; +} + +extern void cpu_halt(void); +extern void asm_delay_loop(uint32_t t); +extern void userspace_asm(uintptr_t ustack, uintptr_t uspace_uarg, + uintptr_t entry); + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/asm/boot.h =================================================================== --- kernel/arch/mips32/include/asm/boot.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/asm/boot.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_BOOT_H_ +#define __mips32_BOOT_H_ + + +/* Temporary stack size for boot process */ +#define TEMP_STACK_SIZE 0x100 + +#endif + +/** @} + */ + Index: kernel/arch/mips32/include/asm/regname.h =================================================================== --- kernel/arch/mips32/include/asm/regname.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/asm/regname.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_REGNAME_H_ +#define __mips32_REGNAME_H_ + +#define zero 0 +#define at 1 +#define v0 2 +#define v1 3 +#define a0 4 +#define a1 5 +#define a2 6 +#define a3 7 +#define t0 8 +#define t1 9 +#define t2 10 +#define t3 11 +#define t4 12 +#define t5 13 +#define t6 14 +#define t7 15 +#define s0 16 +#define s1 17 +#define s2 18 +#define s3 19 +#define s4 20 +#define s5 21 +#define s6 22 +#define s7 23 +#define t8 24 +#define t9 25 +#define k0 26 +#define k1 27 +#define gp 28 +#define sp 29 +#define s8 30 +#define ra 31 + +#define rindex 0 +#define rrandom 1 +#define entrylo0 2 +#define entrylo1 3 +#define context 4 +#define pagemask 5 +#define wired 6 +#define badvaddr 8 +#define count 9 +#define entryhi 10 +#define compare 11 +#define status 12 +#define cause 13 +#define epc 14 +#define rconfig 16 +#define lladdr 17 +#define watchlo 18 +#define watchhi 19 +#define xcontext 20 +#define rdebug 23 +#define depc 24 +#define eepc 30 + + +#endif /* _REGNAME_H_ */ + +/** @} + */ Index: kernel/arch/mips32/include/atomic.h =================================================================== --- kernel/arch/mips32/include/atomic.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/atomic.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_ATOMIC_H__ +#define __mips32_ATOMIC_H__ + +#define atomic_inc(x) ((void) atomic_add(x, 1)) +#define atomic_dec(x) ((void) atomic_add(x, -1)) + +#define atomic_postinc(x) (atomic_add(x, 1) - 1) +#define atomic_postdec(x) (atomic_add(x, -1) + 1) + +#define atomic_preinc(x) atomic_add(x, 1) +#define atomic_predec(x) atomic_add(x, -1) + +/* Atomic addition of immediate value. + * + * @param val Memory location to which will be the immediate value added. + * @param i Signed immediate that will be added to *val. + * + * @return Value after addition. + */ +static inline long atomic_add(atomic_t *val, int i) +{ + long tmp, v; + + __asm__ volatile ( + "1:\n" + " ll %0, %1\n" + " addiu %0, %0, %3\n" /* same as addi, but never traps on overflow */ + " move %2, %0\n" + " sc %0, %1\n" + " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */ + " nop\n" + : "=r" (tmp), "=m" (val->count), "=r" (v) + : "i" (i), "i" (0) + ); + + return v; +} + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/barrier.h =================================================================== --- kernel/arch/mips32/include/barrier.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/barrier.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_BARRIER_H__ +#define __mips32_BARRIER_H__ + +/* + * TODO: implement true MIPS memory barriers for macros below. + */ +#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory") +#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory") + +#define memory_barrier() __asm__ volatile ("" ::: "memory") +#define read_barrier() __asm__ volatile ("" ::: "memory") +#define write_barrier() __asm__ volatile ("" ::: "memory") + +#endif + +/** @} + */ + Index: kernel/arch/mips32/include/boot.h =================================================================== --- kernel/arch/mips32/include/boot.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/boot.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2006 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __mips32_BOOT_H__ +#define __mips32_BOOT_H__ + +#define TASKMAP_MAX_RECORDS 32 + +#include + +typedef struct { + uintptr_t addr; + uint32_t size; +} utask_t; + +typedef struct { + uint32_t cnt; + utask_t tasks[TASKMAP_MAX_RECORDS]; +} bootinfo_t; + +extern bootinfo_t bootinfo; + +#endif Index: kernel/arch/mips32/include/byteorder.h =================================================================== --- kernel/arch/mips32/include/byteorder.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/byteorder.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_BYTEORDER_H__ +#define __mips32_BYTEORDER_H__ + +#include +#include + +#ifdef BIG_ENDIAN +static inline uint64_t uint64_t_le2host(uint64_t n) +{ + return uint64_t_byteorder_swap(n); +} + +static inline unative_t unative_t_le2host(unative_t n) +{ + return uint32_t_byteorder_swap(n); +} + +#else +# define unative_t_le2host(n) (n) +# define uint64_t_le2host(n) (n) +#endif + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/cache.h =================================================================== --- kernel/arch/mips32/include/cache.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/cache.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_CACHE_H__ +#define __mips32_CACHE_H__ + +#include + +extern void cache_error(istate_t *istate); + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/console.h =================================================================== --- kernel/arch/mips32/include/console.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/console.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_CONSOLE_H__ +#define __mips32_CONSOLE_H__ + + +void console_init(void); + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/context.h =================================================================== --- kernel/arch/mips32/include/context.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/context.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_CONTEXT_H__ +#define __mips32_CONTEXT_H__ + +#include +#include + +/* + * Put one item onto the stack to support get_stack_base() and align it up. + */ +#define SP_DELTA (0 + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)) + + +#ifndef __ASM__ + +#ifndef __mips32_TYPES_H__ +# include +#endif + +/* + * Only save registers that must be preserved across + * function calls. + */ +struct context { + uintptr_t sp; + uintptr_t pc; + + uint32_t s0; + uint32_t s1; + uint32_t s2; + uint32_t s3; + uint32_t s4; + uint32_t s5; + uint32_t s6; + uint32_t s7; + uint32_t s8; + uint32_t gp; + + ipl_t ipl; +}; + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/context_offset.h =================================================================== --- kernel/arch/mips32/include/context_offset.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/context_offset.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,52 @@ +/* This file is automatically generated by gencontext.c. */ +/* struct context */ +#define OFFSET_SP 0x0 +#define OFFSET_PC 0x4 +#define OFFSET_S0 0x8 +#define OFFSET_S1 0xc +#define OFFSET_S2 0x10 +#define OFFSET_S3 0x14 +#define OFFSET_S4 0x18 +#define OFFSET_S5 0x1c +#define OFFSET_S6 0x20 +#define OFFSET_S7 0x24 +#define OFFSET_S8 0x28 +#define OFFSET_GP 0x2c + + +/* struct register_dump */ +#define EOFFSET_AT 0x0 +#define EOFFSET_V0 0x4 +#define EOFFSET_V1 0x8 +#define EOFFSET_A0 0xc +#define EOFFSET_A1 0x10 +#define EOFFSET_A2 0x14 +#define EOFFSET_A3 0x18 +#define EOFFSET_T0 0x1c +#define EOFFSET_T1 0x20 +#define EOFFSET_T2 0x24 +#define EOFFSET_T3 0x28 +#define EOFFSET_T4 0x2c +#define EOFFSET_T5 0x30 +#define EOFFSET_T6 0x34 +#define EOFFSET_T7 0x38 +#define EOFFSET_S0 0x3c +#define EOFFSET_S1 0x40 +#define EOFFSET_S2 0x44 +#define EOFFSET_S3 0x48 +#define EOFFSET_S4 0x4c +#define EOFFSET_S5 0x50 +#define EOFFSET_S6 0x54 +#define EOFFSET_S7 0x58 +#define EOFFSET_T8 0x5c +#define EOFFSET_T9 0x60 +#define EOFFSET_GP 0x64 +#define EOFFSET_SP 0x68 +#define EOFFSET_S8 0x6c +#define EOFFSET_RA 0x70 +#define EOFFSET_LO 0x74 +#define EOFFSET_HI 0x78 +#define EOFFSET_STATUS 0x7c +#define EOFFSET_EPC 0x80 +#define EOFFSET_K1 0x84 +#define REGISTER_SPACE 136 Index: kernel/arch/mips32/include/cp0.h =================================================================== --- kernel/arch/mips32/include/cp0.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/cp0.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_CP0_H__ +#define __mips32_CP0_H__ + +#include +#include + +#define cp0_status_ie_enabled_bit (1<<0) +#define cp0_status_exl_exception_bit (1<<1) +#define cp0_status_erl_error_bit (1<<2) +#define cp0_status_um_bit (1<<4) +#define cp0_status_bev_bootstrap_bit (1<<22) +#define cp0_status_fpu_bit (1<<29) + +#define cp0_status_im_shift 8 +#define cp0_status_im_mask 0xff00 + +#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) +#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3) + +#define fpu_cop_id 1 + +/* + * Magic value for use in msim. + */ +#define cp0_compare_value 100000 + +#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) +#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) +#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it)))) +#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it)))) + +#define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \ + { \ + uint32_t retval; \ + asm("mfc0 %0, $" #reg : "=r"(retval)); \ + return retval; \ + } + +#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \ + { \ + asm("mtc0 %0, $" #reg : : "r"(val) ); \ + } + +GEN_READ_CP0(index, 0); +GEN_WRITE_CP0(index, 0); + +GEN_READ_CP0(random, 1); + +GEN_READ_CP0(entry_lo0, 2); +GEN_WRITE_CP0(entry_lo0, 2); + +GEN_READ_CP0(entry_lo1, 3); +GEN_WRITE_CP0(entry_lo1, 3); + +GEN_READ_CP0(context, 4); +GEN_WRITE_CP0(context, 4); + +GEN_READ_CP0(pagemask, 5); +GEN_WRITE_CP0(pagemask, 5); + +GEN_READ_CP0(wired, 6); +GEN_WRITE_CP0(wired, 6); + +GEN_READ_CP0(badvaddr, 8); + +GEN_READ_CP0(count, 9); +GEN_WRITE_CP0(count, 9); + +GEN_READ_CP0(entry_hi, 10); +GEN_WRITE_CP0(entry_hi, 10); + +GEN_READ_CP0(compare, 11); +GEN_WRITE_CP0(compare, 11); + +GEN_READ_CP0(status, 12); +GEN_WRITE_CP0(status, 12); + +GEN_READ_CP0(cause, 13); +GEN_WRITE_CP0(cause, 13); + +GEN_READ_CP0(epc, 14); +GEN_WRITE_CP0(epc, 14); + +GEN_READ_CP0(prid, 15); + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/cpu.h =================================================================== --- kernel/arch/mips32/include/cpu.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/cpu.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_CPU_H__ +#define __mips32_CPU_H__ + +#include + +struct cpu_arch { + uint32_t imp_num; + uint32_t rev_num; +}; + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/debug.h =================================================================== --- kernel/arch/mips32/include/debug.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/debug.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32debug + * @{ + */ +/** @file + */ + +#ifndef __mips32_DEBUG_H__ +#define __mips23_DEBUG_H__ + + + +/** simulator enters the trace mode */ +#define ___traceon() asm volatile ( "\t.word\t0x39\n"); +/** simulator leaves the trace mode */ +#define ___traceoff() asm volatile ( "\t.word\t0x3d\n"); +/** register dump */ +#define ___regview() asm volatile ( "\t.word\t0x37\n"); +/** halt the simulator */ +#define ___halt() asm volatile ( "\t.word\t0x28\n"); +/** simulator enters interactive mode */ +#define ___intmode() asm volatile ( "\t.word\t0x29\n"); + + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/debugger.h =================================================================== --- kernel/arch/mips32/include/debugger.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/debugger.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32debug + * @{ + */ +/** @file + */ + +#ifndef _mips32_DEBUGGER_H_ +#define _mips32_DEBUGGER_H_ + +#include +#include +#include + +#define BKPOINTS_MAX 10 + +#define BKPOINT_INPROG (1 << 0) /**< Breakpoint was shot */ +#define BKPOINT_ONESHOT (1 << 1) /**< One-time breakpoint,mandatory for j/b + instructions */ +#define BKPOINT_REINST (1 << 2) /**< Breakpoint is set on the next + instruction, so that it could be + reinstalled on the previous one */ +#define BKPOINT_FUNCCALL (1 << 3) /**< Call a predefined function */ + +typedef struct { + uintptr_t address; /**< Breakpoint address */ + unative_t instruction; /**< Original instruction */ + unative_t nextinstruction; /**< Original instruction following break */ + int flags; /**< Flags regarding breakpoint */ + count_t counter; + void (*bkfunc)(void *b, istate_t *istate); +} bpinfo_t; + +extern void debugger_init(void); +void debugger_bpoint(istate_t *istate); + +extern bpinfo_t breakpoints[BKPOINTS_MAX]; + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/drivers/arc.h =================================================================== --- kernel/arch/mips32/include/drivers/arc.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/drivers/arc.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,268 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_ARC_H__ +#define __mips32_ARC_H__ + +#include +#include + +#define ARC_BASE_ADDR 0x1000; +#define ARC_MAGIC 0x53435241 +/* Frame size used by ARC */ +#define ARC_FRAME 4096 + +typedef enum { + CmResourceTypeNull = 0, + CmResourceTypePort, + CmResourceTypeInterrupt, + CmResourceTypeMemory, + CmResourceTypeDma, + CmResourceTypeDeviceSpecific, + CmResourceTypeVendor, + CmResourceTypeProductName, + CmResourceTypeSerialNumber +}cm_resource_type; + +typedef struct { + uint8_t type; + uint8_t sharedisposition; + uint16_t flags; + union { + struct { + long long start; /* 64-bit phys address */ + unsigned long length; + }port; + struct { + unsigned long level; + unsigned long vector; + unsigned long reserved1; + }interrupt; + struct { + long long start; /* 64-bit phys address */ + unsigned long length; + }memory; + }u; +}__attribute__ ((packed)) cm_resource_descriptor; + +typedef struct { + uint16_t version; + uint16_t revision; + unsigned long count; + cm_resource_descriptor descr[1]; +}__attribute__ ((packed)) cm_resource_list; + +typedef enum { + SystemClass = 0, + ProcessorClass, + CacheClass, + AdapterClass, + ControllerClass, + PeripheralClass, + MemoryClass +} arc_component_class; + +typedef enum { + ARC_type = 0, + CPU_type, + FPU_type, + PrimaryICache, + PrimaryDCache, + SecondaryICache, + SecondaryDCache, + SecondaryCache, + Memory, /* Not in NT PROM */ + EISAAdapter, + TCAdapter, + SCSIAdapter, + DTIAdapter, + MultiFunctionAdapter, + DiskController, + TapeController, + CDROMController, + WORMController, + SerialController, + NetworkController, + DisplayController, + ParallelController, + PointerController, + KeyboardController, + AudioController, + OtherController, + DiskPeripheral, + FloppyDiskPeripheral, + TapePeripheral, + ModemPeripheral, + MonitorPeripheral, + PrinterPeripheral, + PointerPeripheral, + KeyboardPeripheral, + TerminalPeripheral, + LinePeripheral, + NetworkPeripheral, + OtherPeripheral, + XTalkAdapter, + PCIAdapter, + GIOAdapter, + TPUAdapter, + Anonymous +}arc_component_type; + +typedef enum { + Failed = 1, + ReadOnly = 2, + Removable = 4, + ConsoleIn = 8, + ConsoleOut = 16, + Input = 32, + Output = 64 +}arc_component_flags; + +typedef struct { + arc_component_class class; + arc_component_type type; + arc_component_flags flags; + uint16_t revision; + uint16_t version; + uint32_t key; + uint32_t affinitymask; + uint32_t configdatasize; + uint32_t identifier_len; + char *identifier; +} __attribute__ ((packed)) arc_component; + +typedef struct { + uint16_t year; + uint16_t month; + uint16_t day; + uint16_t hour; + uint16_t minutes; + uint16_t seconds; + uint16_t mseconds; +} __attribute__ ((packed)) arc_timeinfo; + +/* This is the SGI block structure, WinNT has it different */ +typedef enum { + ExceptionBlock, + SystemParameterBlock, + FreeContiguous, + FreeMemory, + BadMemory, + LoadedProgram, + FirmwareTemporary, + FirmwarePermanent +}arc_memorytype_t; + +typedef struct { + arc_memorytype_t type; + uint32_t basepage; /* *4096 = baseaddr */ + uint32_t basecount; +}arc_memdescriptor_t; + +typedef struct { + char vendorid[8]; + char prodid[8]; +}arc_sysid_t; + +typedef struct { + long (*load)(void); /* ... */ + long (*invoke)(uint32_t eaddr,uint32_t saddr,uint32_t argc,char **argv, + char **envp); + long (*execute)(char *path,uint32_t argc,char **argv,char **envp); + void (*halt)(void); + void (*powerdown)(void); + void (*restart)(void); + void (*reboot)(void); + void (*enterinteractivemode)(void); + long (*reserved)(void); +/* 10 */ + arc_component * (*getpeer)(arc_component *c); + arc_component * (*getchild)(arc_component *c); + arc_component * (*getparent)(arc_component *c); + long (*getconfigurationdata)(void *configdata, arc_component *c); + long (*addchild)(arc_component *c, arc_component *template, + void *configdata); + long (*deletecomponet)(arc_component *current); + long (*getcomponent)(char *path); + long (*saveconfiguration)(void); + arc_sysid_t (*getsystemid)(void); + arc_memdescriptor_t * (*getmemorydescriptor)(arc_memdescriptor_t *cur); +/* 20 */ + long (*reserved2)(void); + arc_timeinfo * (*gettime)(void); + uint32_t (*getrelativetime)(void); + long (*getdirectoryentry)(); + long (*open)(void); /* ... */ + long (*close)(uint32_t fileid); + long (*read)(uint32_t fileid,void *buf,uint32_t n,uint32_t *cnt); + long (*getreadstatus)(uint32_t fileid); + long (*write)(uint32_t fileid, void *buf,uint32_t n,uint32_t *cnt); + long (*seek)(void); /* ... */ +/* 30 */ + long (*mount)(void); /* ... */ + char * (*getenvironmentvariable)(char *name); + char * (*setenvironmentvariable)(char *name, char *value); + long (*getfileinformation)(void); /* ... */ + long (*setfileinformation)(uint32_t fileid,uint32_t attflags,uint32_t attmask); + void (*flushallcaches)(void); + long (*testunicodecharacter)(void); /* ... */ + long (*getdisplaystatus)(void); /* ... */ +} arc_func_vector_t; + +typedef struct { + uint32_t signature; + uint32_t length; + uint16_t version; + uint16_t revision; + void *restartblock; + void *debugblock; + void *gevector; + void *utlbmissvector; + uint32_t firmwarevectorlen; + arc_func_vector_t *firmwarevector; + uint32_t privvectorlen; + void *privvector; + uint32_t adaptercount; +}__attribute__ ((packed)) arc_sbp; + +extern int arc_init(void); +extern int arc_enabled(void); +void arc_frame_init(void); +void arc_console(void); + +#endif + + /** @} + */ + Index: kernel/arch/mips32/include/drivers/msim.h =================================================================== --- kernel/arch/mips32/include/drivers/msim.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/drivers/msim.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef _MSIM_H_ +#define _MSIM_H_ + +#include + +#define MSIM_VIDEORAM 0xB0000000 +/** Address of 'keyboard' device. */ +#define MSIM_KBD_ADDRESS 0xB0000000 +#define MSIM_KBD_IRQ 2 + +void msim_console(void); +void msim_kbd_release(void); +void msim_kbd_grab(void); + +#endif + + /** @} + */ + Index: kernel/arch/mips32/include/drivers/serial.h =================================================================== --- kernel/arch/mips32/include/drivers/serial.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/drivers/serial.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __DRV_SERIAL_H__ +#define __DRV_SERIAL_H__ + +#include + +#define SERIAL_MAX 4 +#define SERIAL_COM1 0x3f8 +#define SERIAL_COM1_IRQ 4 +#define SERIAL_COM2 0x2f8 +#define SERIAL_COM2_IRQ 3 + +#define P_WRITEB(where,what) (*((volatile char *) (0xB8000000+where))=what) +#define P_READB(where) (*((volatile char *)(0xB8000000+where))) + +#define SERIAL_READ(x) P_READB(x) +#define SERIAL_WRITE(x,c) P_WRITEB(x,c) +/* Interrupt enable register */ +#define SERIAL_READ_IER(x) (P_READB((x) + 1)) +#define SERIAL_WRITE_IER(x,c) (P_WRITEB((x)+1,c)) +/* Interrupt identification register */ +#define SERIAL_READ_IIR(x) (P_READB((x) + 2)) +/* Line status register */ +#define SERIAL_READ_LSR(x) (P_READB((x) + 5)) +#define TRANSMIT_EMPTY_BIT 5 + +typedef struct { + int port; + int irq; +}serial_t; + +void serial_console(void); +int serial_init(void); + +#endif + + /** @} + */ + Index: kernel/arch/mips32/include/elf.h =================================================================== --- kernel/arch/mips32/include/elf.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/elf.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2006 Sergey Bondari + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_ELF_H__ +#define __mips32_ELF_H__ + +#define ELF_MACHINE EM_MIPS + +#ifdef BIG_ENDIAN +# define ELF_DATA_ENCODING ELFDATA2MSB +#else +# define ELF_DATA_ENCODING ELFDATA2LSB +#endif + +#define ELF_CLASS ELFCLASS32 + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/exception.h =================================================================== --- kernel/arch/mips32/include/exception.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/exception.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_EXCEPTION_H__ +#define __mips32_EXCEPTION_H__ + +#ifndef __mips32_TYPES_H__ +# include +#endif + +#include +#include + +#define EXC_Int 0 +#define EXC_Mod 1 +#define EXC_TLBL 2 +#define EXC_TLBS 3 +#define EXC_AdEL 4 +#define EXC_AdES 5 +#define EXC_IBE 6 +#define EXC_DBE 7 +#define EXC_Sys 8 +#define EXC_Bp 9 +#define EXC_RI 10 +#define EXC_CpU 11 +#define EXC_Ov 12 +#define EXC_Tr 13 +#define EXC_VCEI 14 +#define EXC_FPE 15 +#define EXC_WATCH 23 +#define EXC_VCED 31 + +struct istate { + uint32_t at; + uint32_t v0; + uint32_t v1; + uint32_t a0; + uint32_t a1; + uint32_t a2; + uint32_t a3; + uint32_t t0; + uint32_t t1; + uint32_t t2; + uint32_t t3; + uint32_t t4; + uint32_t t5; + uint32_t t6; + uint32_t t7; + uint32_t s0; + uint32_t s1; + uint32_t s2; + uint32_t s3; + uint32_t s4; + uint32_t s5; + uint32_t s6; + uint32_t s7; + uint32_t t8; + uint32_t t9; + uint32_t gp; + uint32_t sp; + uint32_t s8; + uint32_t ra; + + uint32_t lo; + uint32_t hi; + + uint32_t status; /* cp0_status */ + uint32_t epc; /* cp0_epc */ + uint32_t k1; /* We use it as thread-local pointer */ +}; + +static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +{ + istate->epc = retaddr; +} + +/** Return true if exception happened while in userspace */ +static inline int istate_from_uspace(istate_t *istate) +{ + return istate->status & cp0_status_um_bit; +} +static inline unative_t istate_get_pc(istate_t *istate) +{ + return istate->epc; +} + +extern void exception(istate_t *istate); +extern void tlb_refill_entry(void); +extern void exception_entry(void); +extern void cache_error_entry(void); +extern void exception_init(void); + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/faddr.h =================================================================== --- kernel/arch/mips32/include/faddr.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/faddr.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_FADDR_H__ +#define __mips32_FADDR_H__ + +#include + +#define FADDR(fptr) ((uintptr_t) (fptr)) + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/fpu_context.h =================================================================== --- kernel/arch/mips32/include/fpu_context.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/fpu_context.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2005 Jakub Vana + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_FPU_CONTEXT_H__ +#define __mips32_FPU_CONTEXT_H__ + +#include + +#define FPU_CONTEXT_ALIGN sizeof(unative_t) + +struct fpu_context { + unative_t dregs[32]; + unative_t cregs[32]; +}; + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/interrupt.h =================================================================== --- kernel/arch/mips32/include/interrupt.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/interrupt.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32interrupt + * @{ + */ +/** @file + */ + +#ifndef __mips32_INTERRUPT_H__ +#define __mips32_INTERRUPT_H__ + +#include + +#define IVT_ITEMS 40 +#define INT_OFFSET 32 +#define IRQ_COUNT 8 + +#define int_register(it, name, handler) exc_register(((it)+INT_OFFSET),name,handler) + +#define IRQ2 2 +#define IRQ3 3 +#define IRQ7 7 + +#define TIMER_IRQ IRQ7 + +extern void interrupt_init(void); + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/memstr.h =================================================================== --- kernel/arch/mips32/include/memstr.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/memstr.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2005 Sergey Bondari + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_MEMSTR_H__ +#define __mips32_MEMSTR_H__ + +#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) + +extern void memsetw(uintptr_t dst, size_t cnt, uint16_t x); +extern void memsetb(uintptr_t dst, size_t cnt, uint8_t x); + +extern int memcmp(uintptr_t src, uintptr_t dst, int cnt); + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/mm/as.h =================================================================== --- kernel/arch/mips32/include/mm/as.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/mm/as.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32mm + * @{ + */ +/** @file + */ + +#ifndef __mips32_AS_H__ +#define __mips32_AS_H__ + +#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 + +#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x80000000 +#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffff +#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x00000000 +#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0x7fffffff + +#define USTACK_ADDRESS_ARCH (0x80000000-PAGE_SIZE) + +extern void as_arch_init(void); + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/mm/asid.h =================================================================== --- kernel/arch/mips32/include/mm/asid.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/mm/asid.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32mm + * @{ + */ +/** @file + */ + +#ifndef __mips32_ASID_H__ +#define __mips32_ASID_H__ + +#include + +#define ASID_MAX_ARCH 255 /* 2^8 - 1 */ + +typedef uint8_t asid_t; + +#endif + +/** @} + */ + Index: kernel/arch/mips32/include/mm/frame.h =================================================================== --- kernel/arch/mips32/include/mm/frame.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/mm/frame.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32mm + * @{ + */ +/** @file + */ + +#ifndef __mips32_FRAME_H__ +#define __mips32_FRAME_H__ + +#define FRAME_WIDTH 14 /* 16K */ +#define FRAME_SIZE (1< + +/* When this function is called, we do not have ARC initiated + * - provide some reasonable minimum and update it later + */ +#define get_memory_size() CONFIG_MEMORY_SIZE + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/mm/page.h =================================================================== --- kernel/arch/mips32/include/mm/page.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/mm/page.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32mm + * @{ + */ +/** @file + */ + +#ifndef __mips32_PAGE_H__ +#define __mips32_PAGE_H__ + +#include + +#define PAGE_WIDTH FRAME_WIDTH +#define PAGE_SIZE FRAME_SIZE + +#ifndef __ASM__ +# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000) +# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000) +#else +# define KA2PA(x) ((x) - 0x80000000) +# define PA2KA(x) ((x) + 0x80000000) +#endif + +#ifdef KERNEL + +/* + * Implementation of generic 4-level page table interface. + * NOTE: this implementation is under construction + * + * Page table layout: + * - 32-bit virtual addresses + * - Offset is 14 bits => pages are 16K long + * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long + * - PTE's replace EntryLo v (valid) bit with p (present) bit + * - PTE's use only one bit to distinguish between cacheable and uncacheable mappings + * - PTE's define soft_valid field to ensure there is at least one 1 bit even if the p bit is cleared + * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed) + * - PTL0 has 64 entries (6 bits) + * - PTL1 is not used + * - PTL2 is not used + * - PTL3 has 4096 entries (12 bits) + */ + +#define PTL0_ENTRIES_ARCH 64 +#define PTL1_ENTRIES_ARCH 0 +#define PTL2_ENTRIES_ARCH 0 +#define PTL3_ENTRIES_ARCH 4096 + +#define PTL0_INDEX_ARCH(vaddr) ((vaddr)>>26) +#define PTL1_INDEX_ARCH(vaddr) 0 +#define PTL2_INDEX_ARCH(vaddr) 0 +#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>14) & 0xfff) + +#define SET_PTL0_ADDRESS_ARCH(ptl0) + +#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].pfn<<12) +#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) +#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) +#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *)(ptl3))[(i)].pfn<<12) + +#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].pfn = (a)>>12) +#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) +#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) +#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].pfn = (a)>>12) + +#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i)) +#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT +#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT +#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i)) + +#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x)) +#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) +#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) +#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x)) + +#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) +#define PTE_PRESENT_ARCH(pte) ((pte)->p != 0) +#define PTE_GET_FRAME_ARCH(pte) ((pte)->pfn<<12) +#define PTE_WRITABLE_ARCH(pte) ((pte)->w != 0) +#define PTE_EXECUTABLE_ARCH(pte) 1 + +#ifndef __ASM__ + +#include +#include +#include +#include + +static inline int get_pt_flags(pte_t *pt, index_t i) +{ + pte_t *p = &pt[i]; + + return ( + (p->cacheable<p)<w)<g<cacheable = (flags & PAGE_CACHEABLE) != 0; + p->p = !(flags & PAGE_NOT_PRESENT); + p->g = (flags & PAGE_GLOBAL) != 0; + p->w = (flags & PAGE_WRITE) != 0; + + /* + * Ensure that valid entries have at least one bit set. + */ + p->soft_valid = 1; +} + +extern void page_arch_init(void); + +#endif /* __ASM__ */ + +#endif /* KERNEL */ + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/mm/tlb.h =================================================================== --- kernel/arch/mips32/include/mm/tlb.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/mm/tlb.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32mm + * @{ + */ +/** @file + */ + +#ifndef __mips32_TLB_H__ +#define __mips32_TLB_H__ + +#include +#include + +#ifdef TLBCNT +# define TLB_ENTRY_COUNT TLBCNT +#else +# define TLB_ENTRY_COUNT 48 +#endif + +#define TLB_WIRED 1 +#define TLB_KSTACK_WIRED_INDEX 0 + +#define TLB_PAGE_MASK_16K (0x3<<13) + +#define PAGE_UNCACHED 2 +#define PAGE_CACHEABLE_EXC_WRITE 5 + +typedef union entry_lo entry_lo_t; +typedef union entry_hi entry_hi_t; +typedef union page_mask page_mask_t; +typedef union index tlb_index_t; + +union entry_lo { + struct { +#ifdef BIG_ENDIAN + unsigned : 2; /* zero */ + unsigned pfn : 24; /* frame number */ + unsigned c : 3; /* cache coherency attribute */ + unsigned d : 1; /* dirty/write-protect bit */ + unsigned v : 1; /* valid bit */ + unsigned g : 1; /* global bit */ +#else + unsigned g : 1; /* global bit */ + unsigned v : 1; /* valid bit */ + unsigned d : 1; /* dirty/write-protect bit */ + unsigned c : 3; /* cache coherency attribute */ + unsigned pfn : 24; /* frame number */ + unsigned : 2; /* zero */ +#endif + } __attribute__ ((packed)); + uint32_t value; +}; + +/** Page Table Entry. */ +struct pte { + unsigned g : 1; /**< Global bit. */ + unsigned p : 1; /**< Present bit. */ + unsigned d : 1; /**< Dirty bit. */ + unsigned cacheable : 1; /**< Cacheable bit. */ + unsigned : 1; /**< Unused. */ + unsigned soft_valid : 1; /**< Valid content even if not present. */ + unsigned pfn : 24; /**< Physical frame number. */ + unsigned w : 1; /**< Page writable bit. */ + unsigned a : 1; /**< Accessed bit. */ +}; + +union entry_hi { + struct { +#ifdef BIG_ENDIAN + unsigned vpn2 : 19; + unsigned : 5; + unsigned asid : 8; +#else + unsigned asid : 8; + unsigned : 5; + unsigned vpn2 : 19; +#endif + } __attribute__ ((packed)); + uint32_t value; +}; + +union page_mask { + struct { +#ifdef BIG_ENDIAN + unsigned : 7; + unsigned mask : 12; + unsigned : 13; +#else + unsigned : 13; + unsigned mask : 12; + unsigned : 7; +#endif + } __attribute__ ((packed)); + uint32_t value; +}; + +union index { + struct { +#ifdef BIG_ENDIAN + unsigned p : 1; + unsigned : 27; + unsigned index : 4; +#else + unsigned index : 4; + unsigned : 27; + unsigned p : 1; +#endif + } __attribute__ ((packed)); + uint32_t value; +}; + +/** Probe TLB for Matching Entry + * + * Probe TLB for Matching Entry. + */ +static inline void tlbp(void) +{ + __asm__ volatile ("tlbp\n\t"); +} + + +/** Read Indexed TLB Entry + * + * Read Indexed TLB Entry. + */ +static inline void tlbr(void) +{ + __asm__ volatile ("tlbr\n\t"); +} + +/** Write Indexed TLB Entry + * + * Write Indexed TLB Entry. + */ +static inline void tlbwi(void) +{ + __asm__ volatile ("tlbwi\n\t"); +} + +/** Write Random TLB Entry + * + * Write Random TLB Entry. + */ +static inline void tlbwr(void) +{ + __asm__ volatile ("tlbwr\n\t"); +} + +#define tlb_invalidate(asid) tlb_invalidate_asid(asid) + +extern void tlb_invalid(istate_t *istate); +extern void tlb_refill(istate_t *istate); +extern void tlb_modified(istate_t *istate); + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/proc/task.h =================================================================== --- kernel/arch/mips32/include/proc/task.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/proc/task.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32proc + * @{ + */ +/** @file + */ + +#ifndef __mips32_TASK_H__ +#define __mips32_TASK_H__ + +typedef struct { +} task_arch_t; + +#define task_create_arch(t) +#define task_destroy_arch(t) + +#endif + + /** @} + */ + Index: kernel/arch/mips32/include/proc/thread.h =================================================================== --- kernel/arch/mips32/include/proc/thread.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/proc/thread.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32proc + * @{ + */ +/** @file + */ + +#ifndef __mips32_THREAD_H__ +#define __mips32_THREAD_H__ + +typedef struct { +} thread_arch_t; + +#define thread_create_arch(t) + +#endif + + /** @} + */ + Index: kernel/arch/mips32/include/stack.h =================================================================== --- kernel/arch/mips32/include/stack.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/stack.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2006 Josef Cejka + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_STACK_H__ +#define __mips32_STACK_H__ + +#define STACK_ITEM_SIZE 4 +#define STACK_ALIGNMENT 8 + +#endif + +/** @} + */ Index: kernel/arch/mips32/include/types.h =================================================================== --- kernel/arch/mips32/include/types.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/include/types.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#ifndef __mips32_TYPES_H__ +#define __mips32_TYPES_H__ + +#define NULL 0 + +typedef signed char int8_t; +typedef unsigned char uint8_t; + +typedef signed short int16_t; +typedef unsigned short uint16_t; + +typedef unsigned long uint32_t; +typedef signed long int32_t; + +typedef unsigned long long uint64_t; +typedef signed long long int64_t; + +typedef uint32_t uintptr_t; + +typedef uint32_t ipl_t; + +typedef uint32_t unative_t; +typedef int32_t native_t; + +typedef struct pte pte_t; + +typedef uint32_t pfn_t; + +#endif + +/** @} + */ Index: kernel/arch/mips32/src/asm.S =================================================================== --- kernel/arch/mips32/src/asm.S (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/asm.S (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,299 @@ +# +# Copyright (C) 2003-2004 Jakub Jermar +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +#include + +.text + +.macro cp0_read reg + mfc0 $2,\reg + j $31 + nop +.endm + +.macro cp0_write reg + mtc0 $4,\reg + j $31 + nop +.endm + +.set noat +.set noreorder +.set nomacro + +.global cpu_halt +cpu_halt: + j cpu_halt + nop + + +.global memsetb +memsetb: + j _memsetb + nop + + +.global memcpy +.global memcpy_from_uspace +.global memcpy_to_uspace +.global memcpy_from_uspace_failover_address +.global memcpy_to_uspace_failover_address +memcpy: +memcpy_from_uspace: +memcpy_to_uspace: + addiu $v0,$a1,3 + li $v1,-4 # 0xfffffffffffffffc + and $v0,$v0,$v1 + beq $a1,$v0,3f + move $t0,$a0 + +0: + beq $a2,$zero,2f + move $a3,$zero + +1: + addu $v0,$a1,$a3 + lbu $a0,0($v0) + addu $v1,$t0,$a3 + addiu $a3,$a3,1 + bne $a3,$a2,1b + sb $a0,0($v1) + +2: + jr $ra + move $v0,$a1 + +3: + addiu $v0,$a0,3 + and $v0,$v0,$v1 + bne $a0,$v0,0b + srl $t1,$a2,2 + + beq $t1,$zero,5f + move $a3,$zero + + move $a3,$zero + move $a0,$zero +4: + addu $v0,$a1,$a0 + lw $v1,0($v0) + addiu $a3,$a3,1 + addu $v0,$t0,$a0 + sw $v1,0($v0) + bne $a3,$t1,4b + addiu $a0,$a0,4 + +5: + andi $a2,$a2,0x3 + beq $a2,$zero,2b + nop + + sll $v0,$a3,2 + addu $t1,$v0,$t0 + move $a3,$zero + addu $t0,$v0,$a1 +6: + addu $v0,$t0,$a3 + lbu $a0,0($v0) + addu $v1,$t1,$a3 + addiu $a3,$a3,1 + bne $a3,$a2,6b + sb $a0,0($v1) + + jr $ra + move $v0,$a1 + +memcpy_from_uspace_failover_address: +memcpy_to_uspace_failover_address: + jr $ra + move $v0, $zero + + + +.macro fpu_gp_save reg ctx + mfc1 $t0,$\reg + sw $t0, \reg*4(\ctx) +.endm + +.macro fpu_gp_restore reg ctx + lw $t0, \reg*4(\ctx) + mtc1 $t0,$\reg +.endm + +.macro fpu_ct_save reg ctx + cfc1 $t0,$1 + sw $t0, (\reg+32)*4(\ctx) +.endm + +.macro fpu_ct_restore reg ctx + lw $t0, (\reg+32)*4(\ctx) + ctc1 $t0,$\reg +.endm + + +.global fpu_context_save +fpu_context_save: +#ifdef ARCH_HAS_FPU + fpu_gp_save 0,$a0 + fpu_gp_save 1,$a0 + fpu_gp_save 2,$a0 + fpu_gp_save 3,$a0 + fpu_gp_save 4,$a0 + fpu_gp_save 5,$a0 + fpu_gp_save 6,$a0 + fpu_gp_save 7,$a0 + fpu_gp_save 8,$a0 + fpu_gp_save 9,$a0 + fpu_gp_save 10,$a0 + fpu_gp_save 11,$a0 + fpu_gp_save 12,$a0 + fpu_gp_save 13,$a0 + fpu_gp_save 14,$a0 + fpu_gp_save 15,$a0 + fpu_gp_save 16,$a0 + fpu_gp_save 17,$a0 + fpu_gp_save 18,$a0 + fpu_gp_save 19,$a0 + fpu_gp_save 20,$a0 + fpu_gp_save 21,$a0 + fpu_gp_save 22,$a0 + fpu_gp_save 23,$a0 + fpu_gp_save 24,$a0 + fpu_gp_save 25,$a0 + fpu_gp_save 26,$a0 + fpu_gp_save 27,$a0 + fpu_gp_save 28,$a0 + fpu_gp_save 29,$a0 + fpu_gp_save 30,$a0 + fpu_gp_save 31,$a0 + + fpu_ct_save 1,$a0 + fpu_ct_save 2,$a0 + fpu_ct_save 3,$a0 + fpu_ct_save 4,$a0 + fpu_ct_save 5,$a0 + fpu_ct_save 6,$a0 + fpu_ct_save 7,$a0 + fpu_ct_save 8,$a0 + fpu_ct_save 9,$a0 + fpu_ct_save 10,$a0 + fpu_ct_save 11,$a0 + fpu_ct_save 12,$a0 + fpu_ct_save 13,$a0 + fpu_ct_save 14,$a0 + fpu_ct_save 15,$a0 + fpu_ct_save 16,$a0 + fpu_ct_save 17,$a0 + fpu_ct_save 18,$a0 + fpu_ct_save 19,$a0 + fpu_ct_save 20,$a0 + fpu_ct_save 21,$a0 + fpu_ct_save 22,$a0 + fpu_ct_save 23,$a0 + fpu_ct_save 24,$a0 + fpu_ct_save 25,$a0 + fpu_ct_save 26,$a0 + fpu_ct_save 27,$a0 + fpu_ct_save 28,$a0 + fpu_ct_save 29,$a0 + fpu_ct_save 30,$a0 + fpu_ct_save 31,$a0 +#endif + j $ra + nop + +.global fpu_context_restore +fpu_context_restore: +#ifdef ARCH_HAS_FPU + fpu_gp_restore 0,$a0 + fpu_gp_restore 1,$a0 + fpu_gp_restore 2,$a0 + fpu_gp_restore 3,$a0 + fpu_gp_restore 4,$a0 + fpu_gp_restore 5,$a0 + fpu_gp_restore 6,$a0 + fpu_gp_restore 7,$a0 + fpu_gp_restore 8,$a0 + fpu_gp_restore 9,$a0 + fpu_gp_restore 10,$a0 + fpu_gp_restore 11,$a0 + fpu_gp_restore 12,$a0 + fpu_gp_restore 13,$a0 + fpu_gp_restore 14,$a0 + fpu_gp_restore 15,$a0 + fpu_gp_restore 16,$a0 + fpu_gp_restore 17,$a0 + fpu_gp_restore 18,$a0 + fpu_gp_restore 19,$a0 + fpu_gp_restore 20,$a0 + fpu_gp_restore 21,$a0 + fpu_gp_restore 22,$a0 + fpu_gp_restore 23,$a0 + fpu_gp_restore 24,$a0 + fpu_gp_restore 25,$a0 + fpu_gp_restore 26,$a0 + fpu_gp_restore 27,$a0 + fpu_gp_restore 28,$a0 + fpu_gp_restore 29,$a0 + fpu_gp_restore 30,$a0 + fpu_gp_restore 31,$a0 + + fpu_ct_restore 1,$a0 + fpu_ct_restore 2,$a0 + fpu_ct_restore 3,$a0 + fpu_ct_restore 4,$a0 + fpu_ct_restore 5,$a0 + fpu_ct_restore 6,$a0 + fpu_ct_restore 7,$a0 + fpu_ct_restore 8,$a0 + fpu_ct_restore 9,$a0 + fpu_ct_restore 10,$a0 + fpu_ct_restore 11,$a0 + fpu_ct_restore 12,$a0 + fpu_ct_restore 13,$a0 + fpu_ct_restore 14,$a0 + fpu_ct_restore 15,$a0 + fpu_ct_restore 16,$a0 + fpu_ct_restore 17,$a0 + fpu_ct_restore 18,$a0 + fpu_ct_restore 19,$a0 + fpu_ct_restore 20,$a0 + fpu_ct_restore 21,$a0 + fpu_ct_restore 22,$a0 + fpu_ct_restore 23,$a0 + fpu_ct_restore 24,$a0 + fpu_ct_restore 25,$a0 + fpu_ct_restore 26,$a0 + fpu_ct_restore 27,$a0 + fpu_ct_restore 28,$a0 + fpu_ct_restore 29,$a0 + fpu_ct_restore 30,$a0 + fpu_ct_restore 31,$a0 +#endif + j $ra + nop Index: kernel/arch/mips32/src/cache.c =================================================================== --- kernel/arch/mips32/src/cache.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/cache.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#include +#include +#include +#include + +void cache_error(istate_t *istate) +{ + panic("cache_error exception (epc=%p)\n", istate->epc); +} + +/** @} + */ + Index: kernel/arch/mips32/src/console.c =================================================================== --- kernel/arch/mips32/src/console.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/console.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include + +void console_init(void) +{ + if (arc_enabled()) { + arc_console(); + } else if (serial_init()) { + serial_console(); + } else { + msim_console(); + } +} + +/** Acquire console back for kernel + * + */ +void arch_grab_console(void) +{ + msim_kbd_grab(); +} +/** Return console to userspace + * + */ +void arch_release_console(void) +{ + msim_kbd_release(); +} + + /** @} + */ + Index: kernel/arch/mips32/src/context.S =================================================================== --- kernel/arch/mips32/src/context.S (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/context.S (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,86 @@ +# +# Copyright (C) 2003-2004 Jakub Jermar +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +#include +#include + +.text + +.set noat +.set noreorder +.set nomacro + +.global context_save_arch +.global context_restore_arch + +.macro CONTEXT_STORE r + sw $s0,OFFSET_S0(\r) + sw $s1,OFFSET_S1(\r) + sw $s2,OFFSET_S2(\r) + sw $s3,OFFSET_S3(\r) + sw $s4,OFFSET_S4(\r) + sw $s5,OFFSET_S5(\r) + sw $s6,OFFSET_S6(\r) + sw $s7,OFFSET_S7(\r) + sw $s8,OFFSET_S8(\r) + sw $gp,OFFSET_GP(\r) + + sw $ra,OFFSET_PC(\r) + sw $sp,OFFSET_SP(\r) +.endm + +.macro CONTEXT_LOAD r + lw $s0,OFFSET_S0(\r) + lw $s1,OFFSET_S1(\r) + lw $s2,OFFSET_S2(\r) + lw $s3,OFFSET_S3(\r) + lw $s4,OFFSET_S4(\r) + lw $s5,OFFSET_S5(\r) + lw $s6,OFFSET_S6(\r) + lw $s7,OFFSET_S7(\r) + lw $s8,OFFSET_S8(\r) + lw $gp,OFFSET_GP(\r) + + lw $ra,OFFSET_PC(\r) + lw $sp,OFFSET_SP(\r) +.endm + + +context_save_arch: + CONTEXT_STORE $a0 + + # context_save returns 1 + j $31 + li $2, 1 + +context_restore_arch: + CONTEXT_LOAD $a0 + + # context_restore returns 0 + j $31 + xor $2, $2 Index: kernel/arch/mips32/src/cpu/cpu.c =================================================================== --- kernel/arch/mips32/src/cpu/cpu.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/cpu/cpu.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#include +#include + +#include + +#include + +#include +#include + +struct data_t { + char *vendor; + char *model; +}; + +static struct data_t imp_data[] = { + { "Invalid", "Invalid" }, /* 0x00 */ + { "MIPS", "R2000" }, /* 0x01 */ + { "MIPS", "R3000" }, /* 0x02 */ + { "MIPS", "R6000" }, /* 0x03 */ + { "MIPS", " R4000/R4400" }, /* 0x04 */ + { "LSI Logic", "R3000" }, /* 0x05 */ + { "MIPS", "R6000A" }, /* 0x06 */ + { "IDT", "3051/3052" }, /* 0x07 */ + { "Invalid", "Invalid" }, /* 0x08 */ + { "MIPS", "R10000/T5" }, /* 0x09 */ + { "MIPS", "R4200" }, /* 0x0a */ + { "Unknown", "Unknown" }, /* 0x0b */ + { "Unknown", "Unknown" }, /* 0x0c */ + { "Invalid", "Invalid" }, /* 0x0d */ + { "Invalid", "Invalid" }, /* 0x0e */ + { "Invalid", "Invalid" }, /* 0x0f */ + { "MIPS", "R8000" }, /* 0x10 */ + { "Invalid", "Invalid" }, /* 0x11 */ + { "Invalid", "Invalid" }, /* 0x12 */ + { "Invalid", "Invalid" }, /* 0x13 */ + { "Invalid", "Invalid" }, /* 0x14 */ + { "Invalid", "Invalid" }, /* 0x15 */ + { "Invalid", "Invalid" }, /* 0x16 */ + { "Invalid", "Invalid" }, /* 0x17 */ + { "Invalid", "Invalid" }, /* 0x18 */ + { "Invalid", "Invalid" }, /* 0x19 */ + { "Invalid", "Invalid" }, /* 0x1a */ + { "Invalid", "Invalid" }, /* 0x1b */ + { "Invalid", "Invalid" }, /* 0x1c */ + { "Invalid", "Invalid" }, /* 0x1d */ + { "Invalid", "Invalid" }, /* 0x1e */ + { "Invalid", "Invalid" }, /* 0x1f */ + { "QED", "R4600" }, /* 0x20 */ + { "Sony", "R3000" }, /* 0x21 */ + { "Toshiba", "R3000" }, /* 0x22 */ + { "NKK", "R3000" }, /* 0x23 */ + { NULL, NULL } +}; + +static struct data_t imp_data80[] = { + { "MIPS", "4Kc" }, /* 0x80 */ + {"Invalid","Invalid"}, /* 0x81 */ + {"Invalid","Invalid"}, /* 0x82 */ + {"MIPS","4Km & 4Kp"}, /* 0x83 */ + { NULL, NULL} +}; + +void cpu_arch_init(void) +{ +} + +void cpu_identify(void) +{ + CPU->arch.rev_num = cp0_prid_read() & 0xff; + CPU->arch.imp_num = (cp0_prid_read() >> 8) & 0xff; +} + +void cpu_print_report(cpu_t *m) +{ + struct data_t *data; + int i; + + if (m->arch.imp_num & 0x80) { + /* Count records */ + for (i=0;imp_data80[i].vendor;i++) + ; + if ((m->arch.imp_num & 0x7f) >= i) { + printf("imp=%d\n",m->arch.imp_num); + return; + } + data = &imp_data80[m->arch.imp_num & 0x7f]; + } else { + for (i=0;imp_data[i].vendor;i++) + ; + if (m->arch.imp_num >= i) { + printf("imp=%d\n",m->arch.imp_num); + return; + } + data = &imp_data[m->arch.imp_num]; + } + + printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n", + m->id, data->vendor, data->model, m->arch.rev_num >> 4, + m->arch.rev_num & 0xf, m->arch.imp_num); +} + +/** @} + */ Index: kernel/arch/mips32/src/ddi/ddi.c =================================================================== --- kernel/arch/mips32/src/ddi/ddi.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/ddi/ddi.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32ddi + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include + +/** Enable I/O space range for task. + * + * Interrupts are disabled and task is locked. + * + * @param task Task. + * @param ioaddr Startign I/O space address. + * @param size Size of the enabled I/O range. + * + * @return 0 on success or an error code from errno.h. + */ +int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) +{ + return 0; +} + + /** @} + */ + Index: kernel/arch/mips32/src/debugger.c =================================================================== --- kernel/arch/mips32/src/debugger.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/debugger.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,388 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32debug + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +bpinfo_t breakpoints[BKPOINTS_MAX]; +SPINLOCK_INITIALIZE(bkpoint_lock); + +static int cmd_print_breakpoints(cmd_arg_t *argv); +static cmd_info_t bkpts_info = { + .name = "bkpts", + .description = "Print breakpoint table.", + .func = cmd_print_breakpoints, + .argc = 0, +}; + +static int cmd_del_breakpoint(cmd_arg_t *argv); +static cmd_arg_t del_argv = { + .type = ARG_TYPE_INT +}; +static cmd_info_t delbkpt_info = { + .name = "delbkpt", + .description = "delbkpt - Delete breakpoint.", + .func = cmd_del_breakpoint, + .argc = 1, + .argv = &del_argv +}; + +static int cmd_add_breakpoint(cmd_arg_t *argv); +static cmd_arg_t add_argv = { + .type = ARG_TYPE_INT +}; +static cmd_info_t addbkpt_info = { + .name = "addbkpt", + .description = "addbkpt <&symbol> - new bkpoint. Break on J/Branch insts unsupported.", + .func = cmd_add_breakpoint, + .argc = 1, + .argv = &add_argv +}; + +static cmd_arg_t adde_argv[] = { + { .type = ARG_TYPE_INT }, + { .type = ARG_TYPE_INT } +}; +static cmd_info_t addbkpte_info = { + .name = "addbkpte", + .description = "addebkpte <&symbol> <&func> - new bkpoint. Call func(or Nothing if 0).", + .func = cmd_add_breakpoint, + .argc = 2, + .argv = adde_argv +}; + +static struct { + uint32_t andmask; + uint32_t value; +}jmpinstr[] = { + {0xf3ff0000, 0x41000000}, /* BCzF */ + {0xf3ff0000, 0x41020000}, /* BCzFL */ + {0xf3ff0000, 0x41010000}, /* BCzT */ + {0xf3ff0000, 0x41030000}, /* BCzTL */ + {0xfc000000, 0x10000000}, /* BEQ */ + {0xfc000000, 0x50000000}, /* BEQL */ + {0xfc1f0000, 0x04010000}, /* BEQL */ + {0xfc1f0000, 0x04110000}, /* BGEZAL */ + {0xfc1f0000, 0x04130000}, /* BGEZALL */ + {0xfc1f0000, 0x04030000}, /* BGEZL */ + {0xfc1f0000, 0x1c000000}, /* BGTZ */ + {0xfc1f0000, 0x5c000000}, /* BGTZL */ + {0xfc1f0000, 0x18000000}, /* BLEZ */ + {0xfc1f0000, 0x58000000}, /* BLEZL */ + {0xfc1f0000, 0x04000000}, /* BLTZ */ + {0xfc1f0000, 0x04100000}, /* BLTZAL */ + {0xfc1f0000, 0x04120000}, /* BLTZALL */ + {0xfc1f0000, 0x04020000}, /* BLTZL */ + {0xfc000000, 0x14000000}, /* BNE */ + {0xfc000000, 0x54000000}, /* BNEL */ + {0xfc000000, 0x08000000}, /* J */ + {0xfc000000, 0x0c000000}, /* JAL */ + {0xfc1f07ff, 0x00000009}, /* JALR */ + {0,0} /* EndOfTable */ +}; + +/** Test, if the given instruction is a jump or branch instruction + * + * @param instr Instruction code + * @return true - it is jump instruction, false otherwise + */ +static bool is_jump(unative_t instr) +{ + int i; + + for (i=0;jmpinstr[i].andmask;i++) { + if ((instr & jmpinstr[i].andmask) == jmpinstr[i].value) + return true; + } + + return false; +} + +/** Add new breakpoint to table */ +int cmd_add_breakpoint(cmd_arg_t *argv) +{ + bpinfo_t *cur = NULL; + ipl_t ipl; + int i; + + if (argv->intval & 0x3) { + printf("Not aligned instruction, forgot to use &symbol?\n"); + return 1; + } + ipl = interrupts_disable(); + spinlock_lock(&bkpoint_lock); + + /* Check, that the breakpoints do not conflict */ + for (i=0; iintval) { + printf("Duplicate breakpoint %d.\n", i); + spinlock_unlock(&bkpoints_lock); + return 0; + } else if (breakpoints[i].address == (uintptr_t)argv->intval + sizeof(unative_t) || \ + breakpoints[i].address == (uintptr_t)argv->intval - sizeof(unative_t)) { + printf("Adjacent breakpoints not supported, conflict with %d.\n", i); + spinlock_unlock(&bkpoints_lock); + return 0; + } + + } + + for (i=0; iaddress = (uintptr_t) argv->intval; + printf("Adding breakpoint on address: %p\n", argv->intval); + cur->instruction = ((unative_t *)cur->address)[0]; + cur->nextinstruction = ((unative_t *)cur->address)[1]; + if (argv == &add_argv) { + cur->flags = 0; + } else { /* We are add extended */ + cur->flags = BKPOINT_FUNCCALL; + cur->bkfunc = (void (*)(void *, istate_t *)) argv[1].intval; + } + if (is_jump(cur->instruction)) + cur->flags |= BKPOINT_ONESHOT; + cur->counter = 0; + + /* Set breakpoint */ + *((unative_t *)cur->address) = 0x0d; + + spinlock_unlock(&bkpoint_lock); + interrupts_restore(ipl); + + return 1; +} + + + +/** Remove breakpoint from table */ +int cmd_del_breakpoint(cmd_arg_t *argv) +{ + bpinfo_t *cur; + ipl_t ipl; + + if (argv->intval < 0 || argv->intval > BKPOINTS_MAX) { + printf("Invalid breakpoint number.\n"); + return 0; + } + ipl = interrupts_disable(); + spinlock_lock(&bkpoint_lock); + + cur = &breakpoints[argv->intval]; + if (!cur->address) { + printf("Breakpoint does not exist.\n"); + spinlock_unlock(&bkpoint_lock); + interrupts_restore(ipl); + return 0; + } + if ((cur->flags & BKPOINT_INPROG) && (cur->flags & BKPOINT_ONESHOT)) { + printf("Cannot remove one-shot breakpoint in-progress\n"); + spinlock_unlock(&bkpoint_lock); + interrupts_restore(ipl); + return 0; + } + ((uint32_t *)cur->address)[0] = cur->instruction; + ((uint32_t *)cur->address)[1] = cur->nextinstruction; + + cur->address = NULL; + + spinlock_unlock(&bkpoint_lock); + interrupts_restore(ipl); + return 1; +} + +/** Print table of active breakpoints */ +int cmd_print_breakpoints(cmd_arg_t *argv) +{ + int i; + char *symbol; + + printf("Breakpoint table.\n"); + for (i=0; i < BKPOINTS_MAX; i++) + if (breakpoints[i].address) { + symbol = get_symtab_entry(breakpoints[i].address); + printf("%d. %p in %s\n",i, + breakpoints[i].address, symbol); + printf(" Count(%d) ", breakpoints[i].counter); + if (breakpoints[i].flags & BKPOINT_INPROG) + printf("INPROG "); + if (breakpoints[i].flags & BKPOINT_ONESHOT) + printf("ONESHOT "); + if (breakpoints[i].flags & BKPOINT_FUNCCALL) + printf("FUNCCALL "); + printf("\n"); + } + return 1; +} + +/** Initialize debugger */ +void debugger_init() +{ + int i; + + for (i=0; iepc; + int i; + + /* test branch delay slot */ + if (cp0_cause_read() & 0x80000000) + panic("Breakpoint in branch delay slot not supported.\n"); + + spinlock_lock(&bkpoint_lock); + for (i=0; iflags & BKPOINT_REINST) { + /* Set breakpoint on first instruction */ + ((uint32_t *)cur->address)[0] = 0x0d; + /* Return back the second */ + ((uint32_t *)cur->address)[1] = cur->nextinstruction; + cur->flags &= ~BKPOINT_REINST; + spinlock_unlock(&bkpoint_lock); + return; + } + if (cur->flags & BKPOINT_INPROG) + printf("Warning: breakpoint recursion\n"); + + if (!(cur->flags & BKPOINT_FUNCCALL)) + printf("***Breakpoint %d: %p in %s.\n", i, + fireaddr, get_symtab_entry(istate->epc)); + + /* Return first instruction back */ + ((uint32_t *)cur->address)[0] = cur->instruction; + + if (! (cur->flags & BKPOINT_ONESHOT)) { + /* Set Breakpoint on next instruction */ + ((uint32_t *)cur->address)[1] = 0x0d; + cur->flags |= BKPOINT_REINST; + } + cur->flags |= BKPOINT_INPROG; + } else { + printf("***Breakpoint %p in %s.\n", fireaddr, + get_symtab_entry(fireaddr)); + /* Move on to next instruction */ + istate->epc += 4; + } + if (cur) + cur->counter++; + if (cur && (cur->flags & BKPOINT_FUNCCALL)) { + /* Allow zero bkfunc, just for counting */ + if (cur->bkfunc) + cur->bkfunc(cur, istate); + } else { + printf("***Type 'exit' to exit kconsole.\n"); + /* This disables all other processors - we are not SMP, + * actually this gets us to cpu_halt, if scheduler() is run + * - we generally do not want scheduler to be run from debug, + * so this is a good idea + */ + atomic_set(&haltstate,1); + spinlock_unlock(&bkpoint_lock); + + kconsole("debug"); + + spinlock_lock(&bkpoint_lock); + atomic_set(&haltstate,0); + } + if (cur && cur->address == fireaddr && (cur->flags & BKPOINT_INPROG)) { + /* Remove one-shot breakpoint */ + if ((cur->flags & BKPOINT_ONESHOT)) + cur->address = NULL; + /* Remove in-progress flag */ + cur->flags &= ~BKPOINT_INPROG; + } + spinlock_unlock(&bkpoint_lock); +} + + /** @} + */ + Index: kernel/arch/mips32/src/drivers/arc.c =================================================================== --- kernel/arch/mips32/src/drivers/arc.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/drivers/arc.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,413 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* This is a good joke, SGI HAS different types than NT bioses... */ +/* Here is the SGI type */ +static char *basetypes[] = { + "ExceptionBlock", + "SystemParameterBlock", + "FreeContiguous", + "FreeMemory", + "BadMemory", + "LoadedProgram", + "FirmwareTemporary", + "FirmwarePermanent" +}; + +static char *ctypes[] = { + "ARC_type", + "CPU_type", + "FPU_type", + "PrimaryICache", + "PrimaryDCache", + "SecondaryICache", + "SecondaryDCache", + "SecondaryCache", + "Memory", + "EISAAdapter", + "TCAdapter", + "SCSIAdapter", + "DTIAdapter", + "MultiFunctionAdapter", + "DiskController", + "TapeController", + "CDROMController", + "WORMController", + "SerialController", + "NetworkController", + "DisplayController", + "ParallelController", + "PointerController", + "KeyboardController", + "AudioController", + "OtherController", + "DiskPeripheral", + "FloppyDiskPeripheral", + "TapePeripheral", + "ModemPeripheral", + "MonitorPeripheral", + "PrinterPeripheral", + "PointerPeripheral", + "KeyboardPeripheral", + "TerminalPeripheral", + "OtherPeripheral", + "LinePeripheral", + "NetworkPeripheral" + "OtherPeripheral", + "XTalkAdapter", + "PCIAdapter", + "GIOAdapter", + "TPUAdapter", + "Anonymous" +}; + +static arc_sbp *sbp = (arc_sbp *)PA2KA(0x1000); +static arc_func_vector_t *arc_entry; + + +static void arc_putchar(char ch); + +/** Return true if ARC is available */ +int arc_enabled(void) +{ + return sbp != NULL; +} + + +/** Print configuration data that ARC reports about component */ +static void arc_print_confdata(arc_component *c) +{ + cm_resource_list *configdata; + int i; + + if (!c->configdatasize) + return; /* No configuration data */ + + configdata = malloc(c->configdatasize, 0); + + if (arc_entry->getconfigurationdata(configdata, c)) { + free(configdata); + return; + } + /* Does not seem to return meaningful data, don't use now */ + free(configdata); + return; + + for (i=0; i < configdata->count; i++) { + switch (configdata->descr[i].type) { + case CmResourceTypePort: + printf("Port: %p-size:%d ", + (uintptr_t)configdata->descr[i].u.port.start, + configdata->descr[i].u.port.length); + break; + case CmResourceTypeInterrupt: + printf("Irq: level(%d) vector(%d) ", + configdata->descr[i].u.interrupt.level, + configdata->descr[i].u.interrupt.vector); + break; + case CmResourceTypeMemory: + printf("Memory: %p-size:%d ", + (uintptr_t)configdata->descr[i].u.port.start, + configdata->descr[i].u.port.length); + break; + default: + break; + } + } + + free(configdata); +} + +/** Print information about component */ +static void arc_print_component(arc_component *c) +{ + int i; + + printf("%s: ",ctypes[c->type]); + for (i=0;i < c->identifier_len;i++) + printf("%c",c->identifier[i]); + + printf(" "); + arc_print_confdata(c); + printf("\n"); +} + +/** + * Read from ARC bios configuration data and print it + */ +static int cmd_arc_print_devices(cmd_arg_t *argv) +{ + arc_component *c,*next; + + c = arc_entry->getchild(NULL); + while (c) { + arc_print_component(c); + next = arc_entry->getchild(c); + while (!next) { + next = arc_entry->getpeer(c); + if (!next) + c = arc_entry->getparent(c); + if (!c) + return 0; + } + c = next; + } + return 1; +} +static cmd_info_t devlist_info = { + .name = "arcdevlist", + .description = "Print arc device list", + .func = cmd_arc_print_devices, + .argc = 0 +}; + + +/** Read from arc bios memory map and print it + * + */ +static int cmd_arc_print_memmap(cmd_arg_t *argv) +{ + arc_memdescriptor_t *desc; + + printf("Memory map:\n"); + + desc = arc_entry->getmemorydescriptor(NULL); + while (desc) { + printf("%s: %d(%p) (size: %dKB)\n",basetypes[desc->type], + desc->basepage * ARC_FRAME, + desc->basepage * ARC_FRAME, + desc->basecount*ARC_FRAME/1024); + desc = arc_entry->getmemorydescriptor(desc); + } + return 1; +} +static cmd_info_t memmap_info = { + .name = "arcmemmap", + .description = "Print arc memory map", + .func = cmd_arc_print_memmap, + .argc = 0 +}; + +/** Print charactor to console */ +static void arc_putchar(char ch) +{ + uint32_t cnt; + ipl_t ipl; + + /* TODO: Should be spinlock? */ + ipl = interrupts_disable(); + arc_entry->write(1, &ch, 1, &cnt); + interrupts_restore(ipl); + +} + +static int cmd_reboot(cmd_arg_t *argv) +{ + arc_entry->reboot(); + return 0; +} +static cmd_info_t reboot_info = { + .name = "reboot", + .description = "Reboot computer", + .func = cmd_reboot, + .argc = 0 +}; + +/** Initialize ARC structure + * + * @return 0 - ARC OK, -1 - ARC does not exist + */ +int arc_init(void) +{ + if (sbp->signature != ARC_MAGIC) { + sbp = NULL; + return -1; + } + arc_entry = sbp->firmwarevector; + + arc_putchar('A'); + arc_putchar('R'); + arc_putchar('C'); + arc_putchar('\n'); + + /* Add command for resetting the computer */ + cmd_initialize(&reboot_info); + cmd_register(&reboot_info); + cmd_initialize(&memmap_info); + cmd_register(&memmap_info); + cmd_initialize(&devlist_info); + cmd_register(&devlist_info); + + return 0; +} + +static bool kbd_polling_enabled; +static chardev_t console; + +/** Try to get character, return character or -1 if not available */ +static void arc_keyboard_poll(void) +{ + char ch; + uint32_t count; + long result; + + if (! kbd_polling_enabled) + return; + + if (arc_entry->getreadstatus(0)) + return; + result = arc_entry->read(0, &ch, 1, &count); + if (result || count!=1) { + return; + } + if (ch == '\r') + ch = '\n'; + if (ch == 0x7f) + ch = '\b'; + + chardev_push_character(&console, ch); +} + +static char arc_read(chardev_t *dev) +{ + char ch; + uint32_t count; + long result; + + result = arc_entry->read(0, &ch, 1, &count); + if (result || count!=1) { + printf("Error reading from ARC keyboard.\n"); + cpu_halt(); + } + if (ch == '\r') + return '\n'; + if (ch == 0x7f) + return '\b'; + return ch; +} + +static void arc_write(chardev_t *dev, const char ch) +{ + arc_putchar(ch); +} + +static void arc_enable(chardev_t *dev) +{ + kbd_polling_enabled = true; +} + +static void arc_disable(chardev_t *dev) +{ + kbd_polling_enabled = false; +} + +static chardev_operations_t arc_ops = { + .resume = arc_enable, + .suspend = arc_disable, + .write = arc_write, + .read = arc_read +}; + +iroutine old_timer; +/** Do polling on timer interrupt */ +static void timer_replace(int n, istate_t *istate) +{ + arc_keyboard_poll(); + old_timer(n, istate); + arc_keyboard_poll(); +} + +void arc_console(void) +{ + kbd_polling_enabled = true; + + chardev_initialize("arc_console", &console, &arc_ops); + old_timer = int_register(TIMER_IRQ, "arc_kb_poll", timer_replace); + stdin = &console; + stdout = &console; +} + +/* Initialize frame zones from ARC firmware. + * In the future we may use even the FirmwareTemporary regions, + * currently we use the FreeMemory (what about the LoadedProgram?) + */ +void arc_frame_init(void) +{ + arc_memdescriptor_t *desc; + int total = 0; + uintptr_t base; + size_t basesize; + + desc = arc_entry->getmemorydescriptor(NULL); + while (desc) { + if (desc->type == FreeMemory || + desc->type == FreeContiguous) { + base = desc->basepage*ARC_FRAME; + basesize = desc->basecount*ARC_FRAME; + + if (base % FRAME_SIZE ) { + basesize -= FRAME_SIZE - (base % FRAME_SIZE); + base = ALIGN_UP(base, FRAME_SIZE); + } + basesize = ALIGN_DOWN(basesize, FRAME_SIZE); + + total += basesize; + + zone_create(ADDR2PFN(base), SIZE2FRAMES(basesize), + ADDR2PFN(base), 0); + } + desc = arc_entry->getmemorydescriptor(desc); + } + + config.memory_size = total; +} + + + /** @} + */ + Index: kernel/arch/mips32/src/drivers/msim.c =================================================================== --- kernel/arch/mips32/src/drivers/msim.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/drivers/msim.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include + +static chardev_t console; + +static void msim_write(chardev_t *dev, const char ch); +static void msim_enable(chardev_t *dev); +static void msim_disable(chardev_t *dev); +static char msim_do_read(chardev_t *dev); + +static chardev_operations_t msim_ops = { + .resume = msim_enable, + .suspend = msim_disable, + .write = msim_write, + .read = msim_do_read, +}; + +/** Putchar that works with MSIM & gxemul */ +void msim_write(chardev_t *dev, const char ch) +{ + *((char *) MSIM_VIDEORAM) = ch; +} + +/* Called from getc(). */ +void msim_enable(chardev_t *dev) +{ + cp0_unmask_int(MSIM_KBD_IRQ); +} + +/* Called from getc(). */ +void msim_disable(chardev_t *dev) +{ + cp0_mask_int(MSIM_KBD_IRQ); +} + +#include +/** Read character using polling, assume interrupts disabled */ +static char msim_do_read(chardev_t *dev) +{ + char ch; + + while (1) { + ch = *((volatile char *) MSIM_KBD_ADDRESS); + if (ch) { + if (ch == '\r') + return '\n'; + if (ch == 0x7f) + return '\b'; + return ch; + } + } +} + +/** Process keyboard interrupt. */ +static void msim_interrupt(int n, istate_t *istate) +{ + char ch = 0; + + ch = *((char *) MSIM_KBD_ADDRESS); + if (ch =='\r') + ch = '\n'; + if (ch == 0x7f) + ch = '\b'; + chardev_push_character(&console, ch); +} + + +/* Return console object representing msim console */ +void msim_console(void) +{ + chardev_initialize("msim_console", &console, &msim_ops); + + int_register(MSIM_KBD_IRQ, "msim_kbd", msim_interrupt); + + cp0_unmask_int(MSIM_KBD_IRQ); + + stdin = &console; + stdout = &console; +} + +static iroutine oldvector; +void msim_kbd_grab(void) +{ + oldvector = int_register(MSIM_KBD_IRQ, "msim_kbd", msim_interrupt); +} +void msim_kbd_release(void) +{ + if (oldvector) + int_register(MSIM_KBD_IRQ, "user_interrupt", oldvector); +} + + /** @} + */ + Index: kernel/arch/mips32/src/drivers/serial.c =================================================================== --- kernel/arch/mips32/src/drivers/serial.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/drivers/serial.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2005 Ondrej Palkovsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include + +static chardev_t console; +static serial_t sconf[SERIAL_MAX]; +static bool kb_enabled; + +static void serial_write(chardev_t *d, const char ch) +{ + serial_t *sd = (serial_t *)d->data; + + if (ch == '\n') + serial_write(d, '\r'); + /* Wait until transmit buffer empty */ + while (! (SERIAL_READ_LSR(sd->port) & (1<port, ch); +} + +static void serial_enable(chardev_t *d) +{ + kb_enabled = true; +} + +static void serial_disable(chardev_t *d) +{ + kb_enabled = false; +} + +int serial_init(void) +{ + int i = 0; + if (SERIAL_READ_LSR(SERIAL_COM1) == 0x60) { + sconf[i].port = SERIAL_COM1; + sconf[i].irq = SERIAL_COM1_IRQ; + /* Enable interrupt on available data */ + i++; + } + return i; +} + +/** Read character from serial port, wait until available */ +static char serial_do_read(chardev_t *dev) +{ + serial_t *sd = (serial_t *)dev->data; + char ch; + + while (!(SERIAL_READ_LSR(sd->port) & 1)) + ; + ch = SERIAL_READ(sd->port); + + if (ch =='\r') + ch = '\n'; + return ch; +} + + +/** Process keyboard interrupt. Does not work in simics? */ +static void serial_interrupt(int n, void *stack) +{ + serial_t *sd = (serial_t *)console.data; + char ch; + + if (!(SERIAL_READ_LSR(sd->port) & 1)) + return; + ch = SERIAL_READ(sd->port); + + if (ch =='\r') + ch = '\n'; + chardev_push_character(&console, ch); +} + + + +static chardev_operations_t serial_ops = { + .resume = serial_enable, + .suspend = serial_disable, + .write = serial_write, + .read = serial_do_read +}; + +iroutine old_timer; +/** Do polling on timer interrupt */ +static void timer_replace(int n, istate_t *istate) +{ + old_timer(n, istate); + serial_interrupt(n, istate); +} + +void serial_console(void) +{ + serial_t *sd = &sconf[0]; + + + chardev_initialize("serial_console", &console, &serial_ops); + console.data = sd; + kb_enabled = true; + +// int_register(2, "serial_drvr", serial_interrupt); + /* I don't know why, but the serial interrupts simply + * don't work on simics + */ + old_timer = int_register(TIMER_IRQ, "serial_drvr_poll", timer_replace); + + stdin = &console; + stdout = &console; +} + + /** @} + */ + Index: kernel/arch/mips32/src/dummy.S =================================================================== --- kernel/arch/mips32/src/dummy.S (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/dummy.S (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,41 @@ +# +# Copyright (C) 2003-2004 Jakub Jermar +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +.text +.set noat + +.global calibrate_delay_loop +.global asm_delay_loop +.global dummy + +calibrate_delay_loop: +asm_delay_loop: + +dummy: + j $31 + nop Index: kernel/arch/mips32/src/exception.c =================================================================== --- kernel/arch/mips32/src/exception.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/exception.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup mips32 + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static char * exctable[] = { + "Interrupt", + "TLB Modified", + "TLB Invalid", + "TLB Invalid Store", + "Address Error - load/instr. fetch", + "Address Error - store", + "Bus Error - fetch instruction", + "Bus Error - data reference", + "Syscall", + "BreakPoint", + "Reserved Instruction", + "Coprocessor Unusable", + "Arithmetic Overflow", + "Trap", + "Virtual Coherency - instruction", + "Floating Point", + NULL, NULL, NULL, NULL, NULL, NULL, NULL, + "WatchHi/WatchLo", /* 23 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, + "Virtual Coherency - data", +}; + +static void print_regdump(istate_t *istate) +{ + char *pcsymbol = ""; + char *rasymbol = ""; + + char *s = get_symtab_entry(istate->epc); + if (s) + pcsymbol = s; + s = get_symtab_entry(istate->ra); + if (s) + rasymbol = s; + + printf("PC: %#x(%s) RA: %#x(%s), SP(%p)\n", istate->epc, pcsymbol, istate->ra, rasymbol, istate->sp); +} + +static void unhandled_exception(int n, istate_t *istate) +{ + fault_if_from_uspace(istate, "unhandled exception %s", exctable[n]); + + print_regdump(istate); + panic("unhandled exception %s\n", exctable[n]); +} + +static void reserved_instr_exception(int n, istate_t *istate) +{ + if (*((uint32_t *)istate->epc) == 0x7c03e83b) { + ASSERT(THREAD); + istate->epc += 4; + istate->v1 = istate->k1; + } else + unhandled_exception(n, istate); +} + +static void breakpoint_exception(int n, istate_t *istate) +{ +#ifdef CONFIG_DEBUG + debugger_bpoint(istate); +#else + /* it is necessary to not re-execute BREAK instruction after + returning from Exception handler + (see page 138 in R4000 Manual for more information) */ + istate->epc += 4; +#endif +} + +static void tlbmod_exception(int n, istate_t *istate) +{ + tlb_modified(istate); +} + +static void tlbinv_exception(int n, istate_t *istate) +{ + tlb_invalid(istate); +} + +#ifdef CONFIG_FPU_LAZY +static void cpuns_exception(int n, istate_t *istate) +{ + if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id) + scheduler_fpu_lazy_request(); + else { + fault_if_from_uspace(istate, "unhandled Coprocessor Unusable Exception"); + panic("unhandled Coprocessor Unusable Exception\n"); + } +} +#endif + +static void interrupt_exception(int n, istate_t *istate) +{ + uint32_t cause; + int i; + + /* decode interrupt number and process the interrupt */ + cause = (cp0_cause_read() >> 8) &0xff; + + for (i = 0; i < 8; i++) + if (cause & (1 << i)) + exc_dispatch(i+INT_OFFSET, istate); +} + +/** Handle syscall userspace call */ +static void syscall_exception(int n, istate_t *istate) +{ + panic("Syscall is handled through shortcut"); +} + +void exception_init(void) +{ + int i; + + /* Clear exception table */ + for (i=0;i < IVT_ITEMS; i++) + exc_register(i, "undef", (iroutine) unhandled_exception); + exc_register(EXC_Bp, "bkpoint", (iroutine) breakpoint_exception); + exc_register(EXC_RI, "resinstr", (iroutine) reserved_instr_exception); + exc_register(EXC_Mod, "tlb_mod", (iroutine) tlbmod_exception); + exc_register(EXC_TLBL, "tlbinvl", (iroutine) tlbinv_exception); + exc_register(EXC_TLBS, "tlbinvl", (iroutine) tlbinv_exception); + exc_register(EXC_Int, "interrupt", (iroutine) interrupt_exception); +#ifdef CONFIG_FPU_LAZY + exc_register(EXC_CpU, "cpunus", (iroutine) cpuns_exception); +#endif + exc_register(EXC_Sys, "syscall", (iroutine) syscall_exception); +} + +/** @} + */ Index: kernel/arch/mips32/src/fpu_context.c =================================================================== --- kernel/arch/mips32/src/fpu_context.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/fpu_context.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2005 Jakub Vana + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32 + * @{ + */ +/** @file + * + */ + +#include +#include +#include +#include + +void fpu_disable(void) +{ +#ifdef ARCH_HAS_FPU + cp0_status_write(cp0_status_read() & ~cp0_status_fpu_bit); +#endif +} + +void fpu_enable(void) +{ +#ifdef ARCH_HAS_FPU + cp0_status_write(cp0_status_read() | cp0_status_fpu_bit); +#endif +} + +void fpu_init() +{ + /* TODO: Zero all registers */ +} + + /** @} + */ + Index: kernel/arch/mips32/src/interrupt.c =================================================================== --- kernel/arch/mips32/src/interrupt.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/mips32/src/interrupt.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2003-2004 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup mips32interrupt + * @{ + */ +/** @file + */ + +#include +#include +#include +#include +#include +#include