Index: kernel/arch/ia64/Makefile.inc =================================================================== --- kernel/arch/ia64/Makefile.inc (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/Makefile.inc (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,86 @@ +# +# Copyright (C) 2005 Martin Decky +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +## Toolchain configuration +# + +BFD_NAME = elf64-little +BFD_ARCH = ia64-elf64 +BFD = elf64-ia64-little +TARGET = ia64-pc-linux-gnu +TOOLCHAIN_DIR = /usr/local/ia64/bin + +## Make some default assumptions +# + +INIT0_ADDRESS = 0xe000000000400000 +INIT0_SIZE = 0x100000 + +CFLAGS += -mconstant-gp -fno-unwind-tables -mfixed-range=f32-f127 +LFLAGS += -EL +AFLAGS += -mconstant-gp + +DEFS += -D__64_BITS__ -DINIT0_ADDRESS=$(INIT0_ADDRESS) -DINIT0_SIZE=$(INIT0_SIZE) + +## Compile with page hash table support. +# + +CONFIG_PAGE_HT = y +DEFS += -DCONFIG_PAGE_HT + +## Compile with support for address space identifiers. +# + +CONFIG_ASID = y +CONFIG_ASID_FIFO = y + + +## Compile with support for software integer division. +# + +CONFIG_SOFTINT = y + +ARCH_SOURCES = \ + arch/$(ARCH)/src/start.S \ + arch/$(ARCH)/src/asm.S \ + arch/$(ARCH)/src/dummy.s \ + arch/$(ARCH)/src/ia64.c \ + arch/$(ARCH)/src/fpu_context.c \ + arch/$(ARCH)/src/context.S \ + arch/$(ARCH)/src/ski/ski.c \ + arch/$(ARCH)/src/cpu/cpu.c \ + arch/$(ARCH)/src/ivt.S \ + arch/$(ARCH)/src/interrupt.c \ + arch/$(ARCH)/src/mm/as.c \ + arch/$(ARCH)/src/mm/frame.c \ + arch/$(ARCH)/src/mm/page.c \ + arch/$(ARCH)/src/mm/tlb.c \ + arch/$(ARCH)/src/mm/vhpt.c \ + arch/$(ARCH)/src/proc/scheduler.c \ + arch/$(ARCH)/src/ddi/ddi.c \ + arch/$(ARCH)/src/drivers/it.c Index: kernel/arch/ia64/_link.ld.in =================================================================== --- kernel/arch/ia64/_link.ld.in (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/_link.ld.in (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,46 @@ +/** IA-64 linker script + * + * It is ELF format, but its only section looks like this: + * kernel text + * kernel data + * + */ + +#define __ASM__ + +ENTRY(kernel_image_start) + +SECTIONS { + .image 0xe000000000100000: AT (0x0000000000100000) { + ktext_start = .; + *(K_TEXT_START); + *(.text) + ktext_end = .; + + kdata_start = .; + *(K_DATA_START) + *(.rodata .rodata.*) + *(.opd) + *(.data .data.*) + *(.got .got.*) + *(.sdata) + *(.sbss) + *(.scommon) + *(.bss) + *(COMMON); + + symbol_table = .; + *(symtab.*); /* Symbol table, must be LAST symbol!*/ + + kdata_end = .; + } + + /DISCARD/ : { + *(*); + } + + _hardcoded_ktext_size = ktext_end - ktext_start; + _hardcoded_kdata_size = kdata_end - kdata_start; + _hardcoded_load_address = 0xe000000000100000; + +} Index: kernel/arch/ia64/include/arch.h =================================================================== --- kernel/arch/ia64/include/arch.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/arch.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2005 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_ARCH_H__ +#define __ia64_ARCH_H__ + +#define LOADED_PROG_STACK_PAGES_NO 2 + +#include + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/arg.h =================================================================== --- kernel/arch/ia64/include/arg.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/arg.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_ARG_H__ +#define __ia64_ARG_H__ + +#include + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/asm.h =================================================================== --- kernel/arch/ia64/include/asm.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/asm.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,286 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_ASM_H__ +#define __ia64_ASM_H__ + +#include +#include +#include + +/** Return base address of current stack + * + * Return the base address of the current stack. + * The stack is assumed to be STACK_SIZE long. + * The stack must start on page boundary. + */ +static inline uintptr_t get_stack_base(void) +{ + uint64_t v; + + __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1))); + + return v; +} + +/** Return Processor State Register. + * + * @return PSR. + */ +static inline uint64_t psr_read(void) +{ + uint64_t v; + + __asm__ volatile ("mov %0 = psr\n" : "=r" (v)); + + return v; +} + +/** Read IVA (Interruption Vector Address). + * + * @return Return location of interruption vector table. + */ +static inline uint64_t iva_read(void) +{ + uint64_t v; + + __asm__ volatile ("mov %0 = cr.iva\n" : "=r" (v)); + + return v; +} + +/** Write IVA (Interruption Vector Address) register. + * + * @param v New location of interruption vector table. + */ +static inline void iva_write(uint64_t v) +{ + __asm__ volatile ("mov cr.iva = %0\n" : : "r" (v)); +} + + +/** Read IVR (External Interrupt Vector Register). + * + * @return Highest priority, pending, unmasked external interrupt vector. + */ +static inline uint64_t ivr_read(void) +{ + uint64_t v; + + __asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v)); + + return v; +} + +/** Write ITC (Interval Timer Counter) register. + * + * @param v New counter value. + */ +static inline void itc_write(uint64_t v) +{ + __asm__ volatile ("mov ar.itc = %0\n" : : "r" (v)); +} + +/** Read ITC (Interval Timer Counter) register. + * + * @return Current counter value. + */ +static inline uint64_t itc_read(void) +{ + uint64_t v; + + __asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v)); + + return v; +} + +/** Write ITM (Interval Timer Match) register. + * + * @param v New match value. + */ +static inline void itm_write(uint64_t v) +{ + __asm__ volatile ("mov cr.itm = %0\n" : : "r" (v)); +} + +/** Read ITM (Interval Timer Match) register. + * + * @return Match value. + */ +static inline uint64_t itm_read(void) +{ + uint64_t v; + + __asm__ volatile ("mov %0 = cr.itm\n" : "=r" (v)); + + return v; +} + +/** Read ITV (Interval Timer Vector) register. + * + * @return Current vector and mask bit. + */ +static inline uint64_t itv_read(void) +{ + uint64_t v; + + __asm__ volatile ("mov %0 = cr.itv\n" : "=r" (v)); + + return v; +} + +/** Write ITV (Interval Timer Vector) register. + * + * @param v New vector and mask bit. + */ +static inline void itv_write(uint64_t v) +{ + __asm__ volatile ("mov cr.itv = %0\n" : : "r" (v)); +} + +/** Write EOI (End Of Interrupt) register. + * + * @param v This value is ignored. + */ +static inline void eoi_write(uint64_t v) +{ + __asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v)); +} + +/** Read TPR (Task Priority Register). + * + * @return Current value of TPR. + */ +static inline uint64_t tpr_read(void) +{ + uint64_t v; + + __asm__ volatile ("mov %0 = cr.tpr\n" : "=r" (v)); + + return v; +} + +/** Write TPR (Task Priority Register). + * + * @param v New value of TPR. + */ +static inline void tpr_write(uint64_t v) +{ + __asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v)); +} + +/** Disable interrupts. + * + * Disable interrupts and return previous + * value of PSR. + * + * @return Old interrupt priority level. + */ +static ipl_t interrupts_disable(void) +{ + uint64_t v; + + __asm__ volatile ( + "mov %0 = psr\n" + "rsm %1\n" + : "=r" (v) + : "i" (PSR_I_MASK) + ); + + return (ipl_t) v; +} + +/** Enable interrupts. + * + * Enable interrupts and return previous + * value of PSR. + * + * @return Old interrupt priority level. + */ +static ipl_t interrupts_enable(void) +{ + uint64_t v; + + __asm__ volatile ( + "mov %0 = psr\n" + "ssm %1\n" + ";;\n" + "srlz.d\n" + : "=r" (v) + : "i" (PSR_I_MASK) + ); + + return (ipl_t) v; +} + +/** Restore interrupt priority level. + * + * Restore PSR. + * + * @param ipl Saved interrupt priority level. + */ +static inline void interrupts_restore(ipl_t ipl) +{ + if (ipl & PSR_I_MASK) + (void) interrupts_enable(); + else + (void) interrupts_disable(); +} + +/** Return interrupt priority level. + * + * @return PSR. + */ +static inline ipl_t interrupts_read(void) +{ + return (ipl_t) psr_read(); +} + +/** Disable protection key checking. */ +static inline void pk_disable(void) +{ + __asm__ volatile ("rsm %0\n" : : "i" (PSR_PK_MASK)); +} + +extern void cpu_halt(void); +extern void cpu_sleep(void); +extern void asm_delay_loop(uint32_t t); + +extern void switch_to_userspace(uintptr_t entry, uintptr_t sp, uintptr_t bsp, uintptr_t uspace_uarg, uint64_t ipsr, uint64_t rsc); + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/atomic.h =================================================================== --- kernel/arch/ia64/include/atomic.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/atomic.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_ATOMIC_H__ +#define __ia64_ATOMIC_H__ + +/** Atomic addition. + * + * @param val Atomic value. + * @param imm Value to add. + * + * @return Value before addition. + */ +static inline long atomic_add(atomic_t *val, int imm) +{ + long v; + + __asm__ volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (val->count) : "i" (imm)); + + return v; +} + +static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); } +static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); } + +static inline long atomic_preinc(atomic_t *val) { return atomic_add(val, 1) + 1; } +static inline long atomic_predec(atomic_t *val) { return atomic_add(val, -1) - 1; } + +static inline long atomic_postinc(atomic_t *val) { return atomic_add(val, 1); } +static inline long atomic_postdec(atomic_t *val) { return atomic_add(val, -1); } + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/barrier.h =================================================================== --- kernel/arch/ia64/include/barrier.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/barrier.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_BARRIER_H__ +#define __ia64_BARRIER_H__ + +/* + * TODO: Implement true IA-64 memory barriers for macros below. + */ +#define CS_ENTER_BARRIER() memory_barrier() +#define CS_LEAVE_BARRIER() memory_barrier() + +#define memory_barrier() __asm__ volatile ("mf\n" ::: "memory") +#define read_barrier() memory_barrier() +#define write_barrier() memory_barrier() + +#define srlz_i() __asm__ volatile (";; srlz.i ;;\n" ::: "memory") +#define srlz_d() __asm__ volatile (";; srlz.d\n" ::: "memory") + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/byteorder.h =================================================================== --- kernel/arch/ia64/include/byteorder.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/byteorder.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_BYTEORDER_H__ +#define __ia64_BYTEORDER_H__ + +/* IA-64 is little-endian */ +#define unative_t_le2host(n) (n) +#define uint64_t_le2host(n) (n) + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/context.h =================================================================== --- kernel/arch/ia64/include/context.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/context.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_CONTEXT_H__ +#define __ia64_CONTEXT_H__ + +#include +#include +#include +#include +#include + +/* + * context_save_arch() and context_restore_arch() are both leaf procedures. + * No need to allocate scratch area. + * + * One item is put onto the stack to support get_stack_base(). + */ +#define SP_DELTA (0+ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)) + +#ifdef context_set +#undef context_set +#endif + +/* RSE stack starts at the bottom of memory stack. */ +#define context_set(c, _pc, stack, size) \ + do { \ + (c)->pc = (uintptr_t) _pc; \ + (c)->bsp = ((uintptr_t) stack) + ALIGN_UP((size), REGISTER_STACK_ALIGNMENT); \ + (c)->ar_pfs &= PFM_MASK; \ + (c)->sp = ((uintptr_t) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - SP_DELTA; \ + } while (0); + +/* + * Only save registers that must be preserved across + * function calls. + */ +struct context { + + /* + * Application registers + */ + uint64_t ar_pfs; + uint64_t ar_unat_caller; + uint64_t ar_unat_callee; + uint64_t ar_rsc; + uintptr_t bsp; /* ar_bsp */ + uint64_t ar_rnat; + uint64_t ar_lc; + + /* + * General registers + */ + uint64_t r1; + uint64_t r4; + uint64_t r5; + uint64_t r6; + uint64_t r7; + uintptr_t sp; /* r12 */ + uint64_t r13; + + /* + * Branch registers + */ + uintptr_t pc; /* b0 */ + uint64_t b1; + uint64_t b2; + uint64_t b3; + uint64_t b4; + uint64_t b5; + + /* + * Predicate registers + */ + uint64_t pr; + + __r128 f2 __attribute__ ((aligned(16))); + __r128 f3; + __r128 f4; + __r128 f5; + + __r128 f16; + __r128 f17; + __r128 f18; + __r128 f19; + __r128 f20; + __r128 f21; + __r128 f22; + __r128 f23; + __r128 f24; + __r128 f25; + __r128 f26; + __r128 f27; + __r128 f28; + __r128 f29; + __r128 f30; + __r128 f31; + + ipl_t ipl; +}; + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/cpu.h =================================================================== --- kernel/arch/ia64/include/cpu.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/cpu.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_CPU_H__ +#define __ia64_CPU_H__ + +#include +#include +#include + +#define FAMILY_ITANIUM 0x7 +#define FAMILY_ITANIUM2 0x1f + +struct cpu_arch { + uint64_t cpuid0; + uint64_t cpuid1; + cpuid3_t cpuid3; +}; + +/** Read CPUID register. + * + * @param n CPUID register number. + * + * @return Value of CPUID[n] register. + */ +static inline uint64_t cpuid_read(int n) +{ + uint64_t v; + + __asm__ volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n)); + + return v; +} + +#endif + +/** @} + */ Index: kernel/arch/ia64/include/debug.h =================================================================== --- kernel/arch/ia64/include/debug.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/debug.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2005 + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64debug ia64 + * @ingroup debug + * @{ + */ +/** @file + */ + +#ifndef __ia64_DEBUG_H__ +#define __ia64_DEBUG_H__ + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/drivers/it.h =================================================================== --- kernel/arch/ia64/include/drivers/it.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/drivers/it.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_IT_H__ +#define __ia64_IT_H__ + +/* + * Unfortunately, Ski does not emulate PAL, + * so we can't read the real frequency ratios + * from firmware. + * + */ +#define IT_DELTA 100000 + +extern void it_init(void); +extern void it_interrupt(void); + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/elf.h =================================================================== --- kernel/arch/ia64/include/elf.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/elf.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2006 Sergey Bondari + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_ELF_H__ +#define __ia64_ELF_H__ + +#define ELF_MACHINE EM_IA_64 +#define ELF_DATA_ENCODING ELFDATA2LSB +#define ELF_CLASS ELFCLASS64 + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/faddr.h =================================================================== --- kernel/arch/ia64/include/faddr.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/faddr.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef KERN_ia64_FADDR_H_ +#define KERN_ia64_FADDR_H_ + +#include + +/** + * + * Calculate absolute address of function + * referenced by fptr pointer. + * + * @param f Function pointer. + * + */ +#define FADDR(f) (*((uintptr_t *)(f))); + +#endif + +/** @} + */ Index: kernel/arch/ia64/include/fpu_context.h =================================================================== --- kernel/arch/ia64/include/fpu_context.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/fpu_context.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2005 Jakub Vana + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_FPU_CONTEXT_H__ +#define __ia64_FPU_CONTEXT_H__ + +#define ARCH_HAS_FPU 1 +#define FPU_CONTEXT_ALIGN 16 + +#include + +#define FRS 96 + +struct fpu_context { + __r128 fr[FRS]; +}; + + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/interrupt.h =================================================================== --- kernel/arch/ia64/include/interrupt.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/interrupt.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64interrupt + * @{ + */ +/** @file + */ + +#ifndef __ia64_INTERRUPT_H__ +#define __ia64_INTERRUPT_H__ + +#include +#include +#include + +#define IRQ_COUNT 257 /* 256 NOT suppotred IRQS*//* TODO */ +#define IRQ_KBD 256 /* One simulated interrupt for ski simulator keyboard*/ + +/** External Interrupt vectors. */ +#define INTERRUPT_TIMER 0 +#define INTERRUPT_SPURIOUS 15 + +/** General Exception codes. */ +#define GE_ILLEGALOP 0 +#define GE_PRIVOP 1 +#define GE_PRIVREG 2 +#define GE_RESREGFLD 3 +#define GE_DISBLDISTRAN 4 +#define GE_ILLEGALDEP 8 + +#define EOI 0 /**< The actual value doesn't matter. */ + +struct istate { + __r128 f2; + __r128 f3; + __r128 f4; + __r128 f5; + __r128 f6; + __r128 f7; + __r128 f8; + __r128 f9; + __r128 f10; + __r128 f11; + __r128 f12; + __r128 f13; + __r128 f14; + __r128 f15; + __r128 f16; + __r128 f17; + __r128 f18; + __r128 f19; + __r128 f20; + __r128 f21; + __r128 f22; + __r128 f23; + __r128 f24; + __r128 f25; + __r128 f26; + __r128 f27; + __r128 f28; + __r128 f29; + __r128 f30; + __r128 f31; + + uintptr_t ar_bsp; + uintptr_t ar_bspstore; + uintptr_t ar_bspstore_new; + uint64_t ar_rnat; + uint64_t ar_ifs; + uint64_t ar_pfs; + uint64_t ar_rsc; + uintptr_t cr_ifa; + cr_isr_t cr_isr; + uintptr_t cr_iipa; + psr_t cr_ipsr; + uintptr_t cr_iip; + uint64_t pr; + uintptr_t sp; + + /* + * The following variables are defined only for break_instruction handler. + */ + uint64_t in0; + uint64_t in1; + uint64_t in2; + uint64_t in3; + uint64_t in4; +}; + +static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) +{ + istate->cr_iip = retaddr; + istate->cr_ipsr.ri = 0; /* return to instruction slot #0 */ +} + +static inline unative_t istate_get_pc(istate_t *istate) +{ + return istate->cr_iip; +} +#include +static inline int istate_from_uspace(istate_t *istate) +{ + return (istate->cr_iip)<0xe000000000000000ULL; +} + +extern void *ivt; + +extern void general_exception(uint64_t vector, istate_t *istate); +extern int break_instruction(uint64_t vector, istate_t *istate); +extern void universal_handler(uint64_t vector, istate_t *istate); +extern void nop_handler(uint64_t vector, istate_t *istate); +extern void external_interrupt(uint64_t vector, istate_t *istate); +extern void virtual_interrupt(uint64_t irq, void *param); +extern void disabled_fp_register(uint64_t vector, istate_t *istate); + + + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/memstr.h =================================================================== --- kernel/arch/ia64/include/memstr.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/memstr.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2005 Sergey Bondari + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_MEMSTR_H__ +#define __ia64_MEMSTR_H__ + +#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) + +extern void memsetw(uintptr_t dst, size_t cnt, uint16_t x); +extern void memsetb(uintptr_t dst, size_t cnt, uint8_t x); + +extern int memcmp(uintptr_t src, uintptr_t dst, int cnt); + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/mm/as.h =================================================================== --- kernel/arch/ia64/include/mm/as.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/mm/as.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64mm + * @{ + */ +/** @file + */ + +#ifndef __ia64_AS_H__ +#define __ia64_AS_H__ + +#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 + +#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0xe000000000000000ULL +#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffffULL +#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000ULL +#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0xdfffffffffffffffULL + +#define USTACK_ADDRESS_ARCH 0x0000000ff0000000ULL + +extern void as_arch_init(void); + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/mm/asid.h =================================================================== --- kernel/arch/ia64/include/mm/asid.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/mm/asid.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64mm + * @{ + */ +/** @file + */ + +#ifndef __ia64_ASID_H__ +#define __ia64_ASID_H__ + +#ifndef __ASM__ + +#include + +typedef uint16_t asid_t; +typedef uint32_t rid_t; + +#endif /* __ASM__ */ + +/** + * Number of ia64 RIDs (Region Identifiers) per kernel ASID. + * Note that some architectures may support more bits, + * but those extra bits are not used by the kernel. + */ +#define RIDS_PER_ASID 7 + +#define RID_MAX 262143 /* 2^18 - 1 */ +#define RID_KERNEL 0 +#define RID_INVALID 1 + +#define ASID2RID(asid, vrn) (((asid)>RIDS_PER_ASID)?(((asid)*RIDS_PER_ASID)+(vrn)):(asid)) +#define RID2ASID(rid) ((rid)/RIDS_PER_ASID) + +#define ASID_MAX_ARCH (RID_MAX/RIDS_PER_ASID) + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/mm/frame.h =================================================================== --- kernel/arch/ia64/include/mm/frame.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/mm/frame.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64mm + * @{ + */ +/** @file + */ + +#ifndef __ia64_FRAME_H__ +#define __ia64_FRAME_H__ + +#define FRAME_WIDTH 14 /* 16K */ +#define FRAME_SIZE (1< + +#define get_memory_size() (512*1024*1024) /* 512M */ + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/mm/page.h =================================================================== --- kernel/arch/ia64/include/mm/page.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/mm/page.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,283 @@ +/* + * Copyright (C) 2005 - 2006 Jakub Jermar + * Copyright (C) 2006 Jakub Vana + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup ia64mm + * @{ + */ +/** @file + */ + +#ifndef __ia64_PAGE_H__ +#define __ia64_PAGE_H__ + +#include + +#define PAGE_SIZE FRAME_SIZE +#define PAGE_WIDTH FRAME_WIDTH + + +#ifdef KERNEL + +/** Bit width of the TLB-locked portion of kernel address space. */ +#define KERNEL_PAGE_WIDTH 28 /* 256M */ + +#define PPN_SHIFT 12 + +#define VRN_SHIFT 61 +#define VRN_MASK (7LL << VRN_SHIFT) +#define VA2VRN(va) ((va)>>VRN_SHIFT) + +#ifdef __ASM__ +#define VRN_KERNEL 7 +#else +#define VRN_KERNEL 7LL +#endif + +#define REGION_REGISTERS 8 + +#define KA2PA(x) ((uintptr_t) (x-(VRN_KERNEL< +#include +#include +#include +#include +#include +#include + +struct vhpt_tag_info { + unsigned long long tag : 63; + unsigned ti : 1; +} __attribute__ ((packed)); + +union vhpt_tag { + struct vhpt_tag_info tag_info; + unsigned tag_word; +}; + +struct vhpt_entry_present { + /* Word 0 */ + unsigned p : 1; + unsigned : 1; + unsigned ma : 3; + unsigned a : 1; + unsigned d : 1; + unsigned pl : 2; + unsigned ar : 3; + unsigned long long ppn : 38; + unsigned : 2; + unsigned ed : 1; + unsigned ig1 : 11; + + /* Word 1 */ + unsigned : 2; + unsigned ps : 6; + unsigned key : 24; + unsigned : 32; + + /* Word 2 */ + union vhpt_tag tag; + + /* Word 3 */ + uint64_t ig3 : 64; +} __attribute__ ((packed)); + +struct vhpt_entry_not_present { + /* Word 0 */ + unsigned p : 1; + unsigned long long ig0 : 52; + unsigned ig1 : 11; + + /* Word 1 */ + unsigned : 2; + unsigned ps : 6; + unsigned long long ig2 : 56; + + /* Word 2 */ + union vhpt_tag tag; + + /* Word 3 */ + uint64_t ig3 : 64; +} __attribute__ ((packed)); + +typedef union vhpt_entry { + struct vhpt_entry_present present; + struct vhpt_entry_not_present not_present; + uint64_t word[4]; +} vhpt_entry_t; + +struct region_register_map { + unsigned ve : 1; + unsigned : 1; + unsigned ps : 6; + unsigned rid : 24; + unsigned : 32; +} __attribute__ ((packed)); + +typedef union region_register { + struct region_register_map map; + unsigned long long word; +} region_register; + +struct pta_register_map { + unsigned ve : 1; + unsigned : 1; + unsigned size : 6; + unsigned vf : 1; + unsigned : 6; + unsigned long long base : 49; +} __attribute__ ((packed)); + +typedef union pta_register { + struct pta_register_map map; + uint64_t word; +} pta_register; + +/** Return Translation Hashed Entry Address. + * + * VRN bits are used to read RID (ASID) from one + * of the eight region registers registers. + * + * @param va Virtual address including VRN bits. + * + * @return Address of the head of VHPT collision chain. + */ +static inline uint64_t thash(uint64_t va) +{ + uint64_t ret; + + __asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va)); + + return ret; +} + +/** Return Translation Hashed Entry Tag. + * + * VRN bits are used to read RID (ASID) from one + * of the eight region registers. + * + * @param va Virtual address including VRN bits. + * + * @return The unique tag for VPN and RID in the collision chain returned by thash(). + */ +static inline uint64_t ttag(uint64_t va) +{ + uint64_t ret; + + __asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va)); + + return ret; +} + +/** Read Region Register. + * + * @param i Region register index. + * + * @return Current contents of rr[i]. + */ +static inline uint64_t rr_read(index_t i) +{ + uint64_t ret; + ASSERT(i < REGION_REGISTERS); + __asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT)); + return ret; +} + +/** Write Region Register. + * + * @param i Region register index. + * @param v Value to be written to rr[i]. + */ +static inline void rr_write(index_t i, uint64_t v) +{ + ASSERT(i < REGION_REGISTERS); + __asm__ volatile ( + "mov rr[%0] = %1\n" + : + : "r" (i << VRN_SHIFT), "r" (v) + ); +} + +/** Read Page Table Register. + * + * @return Current value stored in PTA. + */ +static inline uint64_t pta_read(void) +{ + uint64_t ret; + + __asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret)); + + return ret; +} + +/** Write Page Table Register. + * + * @param v New value to be stored in PTA. + */ +static inline void pta_write(uint64_t v) +{ + __asm__ volatile ("mov cr.pta = %0\n" : : "r" (v)); +} + +extern void page_arch_init(void); + +extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid); +extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v); +extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags); + +#endif /* __ASM__ */ + +#endif /* KERNEL */ + +#endif + +/** @} + */ Index: kernel/arch/ia64/include/mm/tlb.h =================================================================== --- kernel/arch/ia64/include/mm/tlb.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/mm/tlb.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64mm + * @{ + */ +/** @file + */ + +#ifndef __ia64_TLB_H__ +#define __ia64_TLB_H__ + +#define tlb_arch_init() +#define tlb_print() + +#include +#include +#include +#include +#include + +/** Data and instruction Translation Register indices. */ +#define DTR_KERNEL 0 +#define ITR_KERNEL 0 +#define DTR_KSTACK1 1 +#define DTR_KSTACK2 2 + +/** Portion of TLB insertion format data structure. */ +union tlb_entry { + uint64_t word[2]; + struct { + /* Word 0 */ + unsigned p : 1; /**< Present. */ + unsigned : 1; + unsigned ma : 3; /**< Memory attribute. */ + unsigned a : 1; /**< Accessed. */ + unsigned d : 1; /**< Dirty. */ + unsigned pl : 2; /**< Privilege level. */ + unsigned ar : 3; /**< Access rights. */ + unsigned long long ppn : 38; /**< Physical Page Number, a.k.a. PFN. */ + unsigned : 2; + unsigned ed : 1; + unsigned ig1 : 11; + + /* Word 1 */ + unsigned : 2; + unsigned ps : 6; /**< Page size will be 2^ps. */ + unsigned key : 24; /**< Protection key, unused. */ + unsigned : 32; + } __attribute__ ((packed)); +} __attribute__ ((packed)); +typedef union tlb_entry tlb_entry_t; + +extern void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc); +extern void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry); +extern void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry); + +extern void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr); +extern void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr); +extern void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr); + +extern void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr); +extern void dtr_purge(uintptr_t page, count_t width); + +extern void dtc_pte_copy(pte_t *t); +extern void itc_pte_copy(pte_t *t); + +extern void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate); +extern void alternate_data_tlb_fault(uint64_t vector, istate_t *istate); +extern void data_nested_tlb_fault(uint64_t vector, istate_t *istate); +extern void data_dirty_bit_fault(uint64_t vector, istate_t *istate); +extern void instruction_access_bit_fault(uint64_t vector, istate_t *istate); +extern void data_access_bit_fault(uint64_t vector, istate_t *istate); +extern void page_not_present(uint64_t vector, istate_t *istate); + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/mm/vhpt.h =================================================================== --- kernel/arch/ia64/include/mm/vhpt.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/mm/vhpt.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,64 @@ +/* +* Copyright (C) 2006 Jakub Vana +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the distribution. +* - The name of the author may not be used to endorse or promote products +* derived from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64mm + * @{ + */ +/** @file +*/ + + +#ifndef __ia64_VHPT_H__ +#define __ia64_VHPT_H__ + +#include +#include + +uintptr_t vhpt_set_up(void); + +static inline vhpt_entry_t tlb_entry_t2vhpt_entry_t(tlb_entry_t tentry) +{ + vhpt_entry_t ventry; + + ventry.word[0]=tentry.word[0]; + ventry.word[1]=tentry.word[1]; + + return ventry; +} + +void vhpt_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry); +void vhpt_invalidate_all(void); +void vhpt_invalidate_asid(asid_t asid); + + +#endif + + + /** @} + */ + Index: kernel/arch/ia64/include/pal/pal.h =================================================================== --- kernel/arch/ia64/include/pal/pal.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/pal/pal.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_PAL_H__ +#define __ia64_PAL_H__ + +#define PAL_OK 0 /**< Call completed without error. */ +#define PAL_UNIMPL -1 /**< Unimplemented procedure. */ +#define PAL_INVARG -2 /**< Invalid argument. */ +#define PAL_ERR -3 /**< Can not compete call without error. */ + +/** These are the indices for PAL_PROC. */ +#define PAL_CACHE_FLUSH 1 +#define PAL_CACHE_INFO 2 +#define PAL_CACHE_INIT 3 +#define PAL_CACHE_PROT_INFO 38 +#define PAL_CACHE_SHARED_INFO 43 +#define PAL_CACHE_SUMMARY 4 + +#define PAL_MEM_ATTRIB 5 +#define PAL_PREFETCH_VISIBILITY 41 +#define PAL_PTCE_INFO 6 +#define PAL_VM_INFO 7 +#define PAL_VM_PAGE_SIZE 34 +#define PAL_VM_SUMMARY 8 +#define PAL_VM_TR_READ 261 + +#define PAL_BUS_GET_FEATURES 9 +#define PAL_BUS_SET_FEATURES 10 +#define PAL_DEBUG_INFO 11 +#define PAL_FIXED_ADDR 12 +#define PAL_FREQ_BASE 13 +#define PAL_FREQ_RATIOS 14 +#define PAL_LOGICAL_TO_PHYSICAL 42 +#define PAL_PERF_MON_INFO 15 +#define PAL_PLATFORM_ADDR 16 +#define PAL_PROC_GET_FEATURES 17 +#define PAL_PROC_SET_FEATURES 18 +#define PAL_REGISTER_INFO 39 +#define PAL_RSE_INFO 19 +#define PAL_VERSION 20 + +#define PAL_MC_CLEAR_LOG 21 +#define PAL_MC_DRAIN 22 +#define PAL_MC_DYNAMIC_STATE 24 +#define PAL_MC_ERROR_INFO 25 +#define PAL_MC_EXPECTED 23 +#define PAL_MC_REGISTER_MEM 27 +#define PAL_MC_RESUME 26 + +#define PAL_HALT 28 +#define PAL_HALT_INFO 257 +#define PAL_HALT_LIGHT 29 + +#define PAL_CACHE_LINE_INIT 31 +#define PAL_CACHE_READ 259 +#define PAL_CACHE_WRITE 260 +#define PAL_TEST_INFO 37 +#define PAL_TEST_PROC 258 + +#define PAL_COPY_INFO 30 +#define PAL_COPY_PAL 256 +#define PAL_ENTER_IA_32_ENV 33 +#define PAL_PMI_ENTRYPOINT 32 + +/* + Ski PTCE data +*/ +#define PAL_PTCE_INFO_BASE() (0x100000000LL) +#define PAL_PTCE_INFO_COUNT1() (2) +#define PAL_PTCE_INFO_COUNT2() (3) +#define PAL_PTCE_INFO_STRIDE1() (0x10000000) +#define PAL_PTCE_INFO_STRIDE2() (0x2000) + + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/proc/task.h =================================================================== --- kernel/arch/ia64/include/proc/task.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/proc/task.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64proc + * @{ + */ +/** @file + */ + +#ifndef __ia64_TASK_H__ +#define __ia64_TASK_H__ + +typedef struct { +} task_arch_t; + +#define task_create_arch(t) +#define task_destroy_arch(t) + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/proc/thread.h =================================================================== --- kernel/arch/ia64/include/proc/thread.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/proc/thread.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64proc + * @{ + */ +/** @file + */ + +#ifndef __ia64_THREAD_H__ +#define __ia64_THREAD_H__ + +typedef struct { +} thread_arch_t; + +#define thread_create_arch(t) + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/register.h =================================================================== --- kernel/arch/ia64/include/register.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/register.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,279 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_REGISTER_H__ +#define __ia64_REGISTER_H__ + +#define CR_IVR_MASK 0xf +#define PSR_IC_MASK 0x2000 +#define PSR_I_MASK 0x4000 +#define PSR_PK_MASK 0x8000 + +#define PSR_DT_MASK (1<<17) +#define PSR_RT_MASK (1<<27) + +#define PSR_DFL_MASK (1<<18) +#define PSR_DFH_MASK (1<<19) + +#define PSR_IT_MASK 0x0000001000000000 + +#define PSR_CPL_SHIFT 32 +#define PSR_CPL_MASK_SHIFTED 3 + +#define PFM_MASK (~0x3fffffffff) + +#define RSC_MODE_MASK 3 +#define RSC_PL_MASK 12 + +/** Application registers. */ +#define AR_KR0 0 +#define AR_KR1 1 +#define AR_KR2 2 +#define AR_KR3 3 +#define AR_KR4 4 +#define AR_KR5 5 +#define AR_KR6 6 +#define AR_KR7 7 +/* AR 8-15 reserved */ +#define AR_RSC 16 +#define AR_BSP 17 +#define AR_BSPSTORE 18 +#define AR_RNAT 19 +/* AR 20 reserved */ +#define AR_FCR 21 +/* AR 22-23 reserved */ +#define AR_EFLAG 24 +#define AR_CSD 25 +#define AR_SSD 26 +#define AR_CFLG 27 +#define AR_FSR 28 +#define AR_FIR 29 +#define AR_FDR 30 +/* AR 31 reserved */ +#define AR_CCV 32 +/* AR 33-35 reserved */ +#define AR_UNAT 36 +/* AR 37-39 reserved */ +#define AR_FPSR 40 +/* AR 41-43 reserved */ +#define AR_ITC 44 +/* AR 45-47 reserved */ +/* AR 48-63 ignored */ +#define AR_PFS 64 +#define AR_LC 65 +#define AR_EC 66 +/* AR 67-111 reserved */ +/* AR 112-127 ignored */ + +/** Control registers. */ +#define CR_DCR 0 +#define CR_ITM 1 +#define CR_IVA 2 +/* CR3-CR7 reserved */ +#define CR_PTA 8 +/* CR9-CR15 reserved */ +#define CR_IPSR 16 +#define CR_ISR 17 +/* CR18 reserved */ +#define CR_IIP 19 +#define CR_IFA 20 +#define CR_ITIR 21 +#define CR_IIPA 22 +#define CR_IFS 23 +#define CR_IIM 24 +#define CR_IHA 25 +/* CR26-CR63 reserved */ +#define CR_LID 64 +#define CR_IVR 65 +#define CR_TPR 66 +#define CR_EOI 67 +#define CR_IRR0 68 +#define CR_IRR1 69 +#define CR_IRR2 70 +#define CR_IRR3 71 +#define CR_ITV 72 +#define CR_PMV 73 +#define CR_CMCV 74 +/* CR75-CR79 reserved */ +#define CR_LRR0 80 +#define CR_LRR1 81 +/* CR82-CR127 reserved */ + +#ifndef __ASM__ + +#include + +/** Processor Status Register. */ +union psr { + uint64_t value; + struct { + unsigned : 1; + unsigned be : 1; /**< Big-Endian data accesses. */ + unsigned up : 1; /**< User Performance monitor enable. */ + unsigned ac : 1; /**< Alignment Check. */ + unsigned mfl : 1; /**< Lower floating-point register written. */ + unsigned mfh : 1; /**< Upper floating-point register written. */ + unsigned : 7; + unsigned ic : 1; /**< Interruption Collection. */ + unsigned i : 1; /**< Interrupt Bit. */ + unsigned pk : 1; /**< Protection Key enable. */ + unsigned : 1; + unsigned dt : 1; /**< Data address Translation. */ + unsigned dfl : 1; /**< Disabled Floating-point Low register set. */ + unsigned dfh : 1; /**< Disabled Floating-point High register set. */ + unsigned sp : 1; /**< Secure Performance monitors. */ + unsigned pp : 1; /**< Privileged Performance monitor enable. */ + unsigned di : 1; /**< Disable Instruction set transition. */ + unsigned si : 1; /**< Secure Interval timer. */ + unsigned db : 1; /**< Debug Breakpoint fault. */ + unsigned lp : 1; /**< Lower Privilege transfer trap. */ + unsigned tb : 1; /**< Taken Branch trap. */ + unsigned rt : 1; /**< Register Stack Translation. */ + unsigned : 4; + unsigned cpl : 2; /**< Current Privilege Level. */ + unsigned is : 1; /**< Instruction Set. */ + unsigned mc : 1; /**< Machine Check abort mask. */ + unsigned it : 1; /**< Instruction address Translation. */ + unsigned id : 1; /**< Instruction Debug fault disable. */ + unsigned da : 1; /**< Disable Data Access and Dirty-bit faults. */ + unsigned dd : 1; /**< Data Debug fault disable. */ + unsigned ss : 1; /**< Single Step enable. */ + unsigned ri : 2; /**< Restart Instruction. */ + unsigned ed : 1; /**< Exception Deferral. */ + unsigned bn : 1; /**< Register Bank. */ + unsigned ia : 1; /**< Disable Instruction Access-bit faults. */ + } __attribute__ ((packed)); +}; +typedef union psr psr_t; + +/** Register Stack Configuration Register */ +union rsc { + uint64_t value; + struct { + unsigned mode : 2; + unsigned pl : 2; /**< Privilege Level. */ + unsigned be : 1; /**< Big-endian. */ + unsigned : 11; + unsigned loadrs : 14; + } __attribute__ ((packed)); +}; +typedef union rsc rsc_t; + +/** External Interrupt Vector Register */ +union cr_ivr { + uint8_t vector; + uint64_t value; +}; + +typedef union cr_ivr cr_ivr_t; + +/** Task Priority Register */ +union cr_tpr { + struct { + unsigned : 4; + unsigned mic: 4; /**< Mask Interrupt Class. */ + unsigned : 8; + unsigned mmi: 1; /**< Mask Maskable Interrupts. */ + } __attribute__ ((packed)); + uint64_t value; +}; + +typedef union cr_tpr cr_tpr_t; + +/** Interval Timer Vector */ +union cr_itv { + struct { + unsigned vector : 8; + unsigned : 4; + unsigned : 1; + unsigned : 3; + unsigned m : 1; /**< Mask. */ + } __attribute__ ((packed)); + uint64_t value; +}; + +typedef union cr_itv cr_itv_t; + +/** Interruption Status Register */ +union cr_isr { + struct { + union { + /** General Exception code field structuring. */ + struct { + unsigned ge_na : 4; + unsigned ge_code : 4; + } __attribute__ ((packed)); + uint16_t code; + }; + uint8_t vector; + unsigned : 8; + unsigned x : 1; /**< Execute exception. */ + unsigned w : 1; /**< Write exception. */ + unsigned r : 1; /**< Read exception. */ + unsigned na : 1; /**< Non-access exception. */ + unsigned sp : 1; /**< Speculative load exception. */ + unsigned rs : 1; /**< Register stack. */ + unsigned ir : 1; /**< Incomplete Register frame. */ + unsigned ni : 1; /**< Nested Interruption. */ + unsigned so : 1; /**< IA-32 Supervisor Override. */ + unsigned ei : 2; /**< Excepting Instruction. */ + unsigned ed : 1; /**< Exception Deferral. */ + unsigned : 20; + } __attribute__ ((packed)); + uint64_t value; +}; + +typedef union cr_isr cr_isr_t; + +/** CPUID Register 3 */ +union cpuid3 { + struct { + uint8_t number; + uint8_t revision; + uint8_t model; + uint8_t family; + uint8_t archrev; + } __attribute__ ((packed)); + uint64_t value; +}; + +typedef union cpuid3 cpuid3_t; + +#endif /* !__ASM__ */ + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/ski/ski.h =================================================================== --- kernel/arch/ia64/include/ski/ski.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/ski/ski.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __SKI_H__ +#define __SKI_H__ + +#include +#include + +#define SKI_INIT_CONSOLE 20 +#define SKI_GETCHAR 21 +#define SKI_PUTCHAR 31 + +extern void ski_init_console(void); +extern void ski_set_console_sysinfo(void); +extern void poll_keyboard(void); + +extern chardev_t ski_uconsole; +extern int kbd_uspace; + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/smp/atomic.h =================================================================== --- kernel/arch/ia64/include/smp/atomic.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/smp/atomic.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,4 @@ + + /** @} + */ + Index: kernel/arch/ia64/include/stack.h =================================================================== --- kernel/arch/ia64/include/stack.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/stack.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __ia64_STACK_H__ +#define __ia64_STACK_H__ + +#define STACK_ITEM_SIZE 8 +#define STACK_ALIGNMENT 16 +#define STACK_SCRATCH_AREA_SIZE 16 +#define REGISTER_STACK_ALIGNMENT 8 + +#endif + + /** @} + */ + Index: kernel/arch/ia64/include/types.h =================================================================== --- kernel/arch/ia64/include/types.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/include/types.h (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#ifndef __TYPES_H__ +#define __TYPES_H__ + +#define NULL 0 + +typedef signed char int8_t; +typedef signed short int int16_t; +typedef signed int int32_t; +typedef signed long int64_t; + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef unsigned long uint64_t; + +typedef unsigned char __r8; /* Reserve byte */ +typedef unsigned short __r16; +typedef unsigned int __r32; +typedef unsigned long __r64; +typedef struct __r128 { + __r64 lo; + __r64 hi; +} __r128; + +typedef uint64_t uintptr_t; +typedef uint64_t pfn_t; + +typedef uint64_t ipl_t; + +typedef uint64_t unative_t; +typedef int64_t native_t; + +typedef struct pte pte_t; + +#endif + +/** @} + */ + Index: kernel/arch/ia64/src/asm.S =================================================================== --- kernel/arch/ia64/src/asm.S (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/src/asm.S (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,184 @@ +# +# Copyright (C) 2005 Jakub Jermar +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +#include + +.text + +/** Copy memory from/to userspace. + * + * This memcpy() has been taken from the assembler output of + * the generic _memcpy() and modified to have the failover part. + * + * @param in0 Destination address. + * @param in1 Source address. + * @param in2 Number of byte to copy. + */ +.global memcpy +.global memcpy_from_uspace +.global memcpy_to_uspace +.global memcpy_from_uspace_failover_address +.global memcpy_to_uspace_failover_address +memcpy: +memcpy_from_uspace: +memcpy_to_uspace: + alloc loc0 = ar.pfs, 3, 1, 0, 0 + + adds r14 = 7, in1 + mov r2 = ar.lc + mov r8 = in1 ;; + and r14 = -8, r14 ;; + cmp.ne p6, p7 = r14, in1 +(p7) br.cond.dpnt 3f ;; +0: + cmp.ne p6, p7 = 0, in2 +(p7) br.cond.dpnt 2f ;; +(p6) adds r14 = -1, in2 +(p6) mov r16 = r0 +(p6) mov r17 = r0 ;; +(p6) mov ar.lc = r14 +1: + add r14 = r16, r8 + add r15 = r16, in0 + adds r17 = 1, r17 ;; + ld1 r14 = [r14] + mov r16 = r17 ;; + st1 [r15] = r14 + br.cloop.sptk.few 1b ;; +2: + mov ar.lc = r2 + + mov ar.pfs = loc0 + br.ret.sptk.many rp +3: + adds r14 = 7, in0 ;; + and r14 = -8, r14 ;; + cmp.eq p6, p7 = r14, in0 +(p7) br.cond.dptk 0b + shr.u r18 = in2, 3 ;; + cmp.ne p6, p7 = 0, r18 +(p7) br.cond.dpnt 5f ;; +(p6) adds r14 = -1, r18 +(p6) mov r16 = r0 +(p6) mov r17 = r0 ;; +(p6) mov ar.lc = r14 +4: + shladd r14 = r16, 3, r0 + adds r16 = 1, r17 ;; + add r15 = r8, r14 + add r14 = in0, r14 + mov r17 = r16 ;; + ld8 r15 = [r15] ;; + st8 [r14] = r15 + br.cloop.sptk.few 4b +5: + and r15 = 7, in2 + shladd r14 = r18, 3, r0 + mov r16 = r0 + mov r18 = r0 ;; + cmp.eq p6, p7 = 0, r15 + add in0 = r14, in0 + adds r15 = -1, r15 + add r17 = r14, r8 +(p6) br.cond.dpnt 2b ;; + mov ar.lc = r15 +6: + add r14 = r16, r17 + add r15 = r16, in0 + adds r16 = 1, r18 ;; + ld1 r14 = [r14] + mov r18 = r16 ;; + st1 [r15] = r14 + br.cloop.sptk.few 6b ;; + mov ar.lc = r2 + + mov ar.pfs = loc0 + br.ret.sptk.many rp + +memcpy_from_uspace_failover_address: +memcpy_to_uspace_failover_address: + mov r8 = r0 /* return 0 on failure */ + mov ar.pfs = loc0 + br.ret.sptk.many rp + +.global memsetb +memsetb: + br _memsetb + +.global cpu_halt +cpu_halt: + br cpu_halt + +.global panic_printf +panic_printf: + { + br.call.sptk.many b0=printf + } + br halt + +/** Switch to userspace - low level code. + * + * @param in0 Userspace entry point address. + * @param in1 Userspace stack pointer address. + * @param in2 Userspace register stack pointer address. + * @param in3 Userspace address of thread uspace_arg_t structure. + * @param in4 Value to be stored in IPSR. + * @param in5 Value to be stored in RSC. + */ +.global switch_to_userspace +switch_to_userspace: + alloc loc0 = ar.pfs, 6, 3, 0, 0 + rsm (PSR_IC_MASK | PSR_I_MASK) /* disable interruption collection and interrupts */ + srlz.d ;; + srlz.i ;; + + mov cr.ipsr = in4 + mov cr.iip = in0 + mov r12 = in1 + + xor r1 = r1, r1 + + mov loc1 = cr.ifs + movl loc2 = PFM_MASK ;; + and loc1 = loc2, loc1 ;; + mov cr.ifs = loc1 ;; /* prevent decrementing BSP by rfi */ + + invala + + mov loc1 = ar.rsc ;; + and loc1 = ~3, loc1 ;; + mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */ + + flushrs ;; + + mov ar.bspstore = in2 ;; + mov ar.rsc = in5 ;; + + mov r8 = in3 + + rfi ;; Index: kernel/arch/ia64/src/context.S =================================================================== --- kernel/arch/ia64/src/context.S (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/src/context.S (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,246 @@ +# +# Copyright (C) 2005 Jakub Jermar +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +.text + +.global context_save_arch +.global context_restore_arch + +context_save_arch: + alloc loc0 = ar.pfs, 1, 8, 0, 0 + mov loc1 = ar.unat ;; + /* loc2 */ + mov loc3 = ar.rsc + + .auto + + /* + * Flush dirty registers to backing store. + * After this ar.bsp and ar.bspstore are equal. + */ + flushrs + mov loc4 = ar.bsp + + /* + * Put RSE to enforced lazy mode. + * So that ar.rnat can be read. + */ + and loc5 = ~3, loc3 + mov ar.rsc = loc5 + mov loc5 = ar.rnat + + .explicit + + mov loc6 = ar.lc + + /* + * Save application registers + */ + st8 [in0] = loc0, 8 ;; /* save ar.pfs */ + st8 [in0] = loc1, 8 ;; /* save ar.unat (caller) */ + mov loc2 = in0 ;; + add in0 = 8, in0 ;; /* skip ar.unat (callee) */ + st8 [in0] = loc3, 8 ;; /* save ar.rsc */ + st8 [in0] = loc4, 8 ;; /* save ar.bsp */ + st8 [in0] = loc5, 8 ;; /* save ar.rnat */ + st8 [in0] = loc6, 8 ;; /* save ar.lc */ + + /* + * Save general registers including NaT bits + */ + st8.spill [in0] = r1, 8 ;; + st8.spill [in0] = r4, 8 ;; + st8.spill [in0] = r5, 8 ;; + st8.spill [in0] = r6, 8 ;; + st8.spill [in0] = r7, 8 ;; + st8.spill [in0] = r12, 8 ;; /* save sp */ + st8.spill [in0] = r13, 8 ;; + + mov loc3 = ar.unat ;; + st8 [loc2] = loc3 /* save ar.unat (callee) */ + + /* + * Save branch registers + */ + mov loc2 = b0 ;; + st8 [in0] = loc2, 8 /* save pc */ + mov loc3 = b1 ;; + st8 [in0] = loc3, 8 + mov loc4 = b2 ;; + st8 [in0] = loc4, 8 + mov loc5 = b3 ;; + st8 [in0] = loc5, 8 + mov loc6 = b4 ;; + st8 [in0] = loc6, 8 + mov loc7 = b5 ;; + st8 [in0] = loc7, 8 + + /* + * Save predicate registers + */ + mov loc2 = pr ;; + st8 [in0] = loc2, 16;; /* Next fpu registers should be spilled to 16B aligned address */ + + /* + * Save floating-point registers. + */ + stf.spill [in0] = f2, 16 ;; + stf.spill [in0] = f3, 16 ;; + stf.spill [in0] = f4, 16 ;; + stf.spill [in0] = f5, 16 ;; + + stf.spill [in0] = f16, 16 ;; + stf.spill [in0] = f17, 16 ;; + stf.spill [in0] = f18, 16 ;; + stf.spill [in0] = f19, 16 ;; + stf.spill [in0] = f20, 16 ;; + stf.spill [in0] = f21, 16 ;; + stf.spill [in0] = f22, 16 ;; + stf.spill [in0] = f23, 16 ;; + stf.spill [in0] = f24, 16 ;; + stf.spill [in0] = f25, 16 ;; + stf.spill [in0] = f26, 16 ;; + stf.spill [in0] = f27, 16 ;; + stf.spill [in0] = f28, 16 ;; + stf.spill [in0] = f29, 16 ;; + stf.spill [in0] = f30, 16 ;; + stf.spill [in0] = f31, 16 ;; + + mov ar.unat = loc1 + + add r8 = r0, r0, 1 /* context_save returns 1 */ + br.ret.sptk.many b0 + +context_restore_arch: + alloc loc0 = ar.pfs, 1, 9, 0, 0 ;; + + ld8 loc0 = [in0], 8 ;; /* load ar.pfs */ + ld8 loc1 = [in0], 8 ;; /* load ar.unat (caller) */ + ld8 loc2 = [in0], 8 ;; /* load ar.unat (callee) */ + ld8 loc3 = [in0], 8 ;; /* load ar.rsc */ + ld8 loc4 = [in0], 8 ;; /* load ar.bsp */ + ld8 loc5 = [in0], 8 ;; /* load ar.rnat */ + ld8 loc6 = [in0], 8 ;; /* load ar.lc */ + + .auto + + /* + * Invalidate the ALAT + */ + invala + + /* + * Put RSE to enforced lazy mode. + * So that ar.bspstore and ar.rnat can be written. + */ + movl loc8 = ~3 + and loc8 = loc3, loc8 + mov ar.rsc = loc8 + + /* + * Flush dirty registers to backing store. + * We do this because we want the following move + * to ar.bspstore to assign the same value to ar.bsp. + */ + flushrs + + /* + * Restore application registers + */ + mov ar.bspstore = loc4 /* rse.bspload = ar.bsp = ar.bspstore = loc4 */ + mov ar.rnat = loc5 + mov ar.pfs = loc0 + mov ar.rsc = loc3 + + .explicit + + mov ar.unat = loc2 ;; + mov ar.lc = loc6 + + /* + * Restore general registers including NaT bits + */ + ld8.fill r1 = [in0], 8 ;; + ld8.fill r4 = [in0], 8 ;; + ld8.fill r5 = [in0], 8 ;; + ld8.fill r6 = [in0], 8 ;; + ld8.fill r7 = [in0], 8 ;; + ld8.fill r12 = [in0], 8 ;; /* restore sp */ + ld8.fill r13 = [in0], 8 ;; + + /* + * Restore branch registers + */ + ld8 loc2 = [in0], 8 ;; /* restore pc */ + mov b0 = loc2 + ld8 loc3 = [in0], 8 ;; + mov b1 = loc3 + ld8 loc4 = [in0], 8 ;; + mov b2 = loc4 + ld8 loc5 = [in0], 8 ;; + mov b3 = loc5 + ld8 loc6 = [in0], 8 ;; + mov b4 = loc6 + ld8 loc7 = [in0], 8 ;; + mov b5 = loc7 + + /* + * Restore predicate registers + */ + ld8 loc2 = [in0], 16 ;; + mov pr = loc2, ~0 + + /* + * Restore floating-point registers. + */ + ldf.fill f2 = [in0], 16 ;; + ldf.fill f3 = [in0], 16 ;; + ldf.fill f4 = [in0], 16 ;; + ldf.fill f5 = [in0], 16 ;; + + ldf.fill f16 = [in0], 16 ;; + ldf.fill f17 = [in0], 16 ;; + ldf.fill f18 = [in0], 16 ;; + ldf.fill f19 = [in0], 16 ;; + ldf.fill f20 = [in0], 16 ;; + ldf.fill f21 = [in0], 16 ;; + ldf.fill f22 = [in0], 16 ;; + ldf.fill f23 = [in0], 16 ;; + ldf.fill f24 = [in0], 16 ;; + ldf.fill f25 = [in0], 16 ;; + ldf.fill f26 = [in0], 16 ;; + ldf.fill f27 = [in0], 16 ;; + ldf.fill f28 = [in0], 16 ;; + ldf.fill f29 = [in0], 16 ;; + ldf.fill f30 = [in0], 16 ;; + ldf.fill f31 = [in0], 16 ;; + + mov ar.unat = loc1 + + mov r8 = r0 /* context_restore returns 0 */ + br.ret.sptk.many b0 Index: kernel/arch/ia64/src/cpu/cpu.c =================================================================== --- kernel/arch/ia64/src/cpu/cpu.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/src/cpu/cpu.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup ia64 + * @{ + */ +/** @file + */ + +#include +#include +#include +#include + +void cpu_arch_init(void) +{ +} + +void cpu_identify(void) +{ + CPU->arch.cpuid0 = cpuid_read(0); + CPU->arch.cpuid1 = cpuid_read(1); + CPU->arch.cpuid3.value = cpuid_read(3); +} + +void cpu_print_report(cpu_t *m) +{ + char *family_str; + char vendor[2*sizeof(uint64_t)+1]; + + *((uint64_t *) &vendor[0*sizeof(uint64_t)]) = CPU->arch.cpuid0; + *((uint64_t *) &vendor[1*sizeof(uint64_t)]) = CPU->arch.cpuid1; + vendor[sizeof(vendor)-1] = '\0'; + + switch(m->arch.cpuid3.family) { + case FAMILY_ITANIUM: + family_str = "Itanium"; + break; + case FAMILY_ITANIUM2: + family_str = "Itanium 2"; + break; + default: + family_str = "Unknown"; + break; + } + + printf("cpu%d: %s (%s), archrev=%d, model=%d, revision=%d\n", CPU->id, family_str, vendor, CPU->arch.cpuid3.archrev, CPU->arch.cpuid3.model, CPU->arch.cpuid3.revision); +} + +/** @} + */ Index: kernel/arch/ia64/src/ddi/ddi.c =================================================================== --- kernel/arch/ia64/src/ddi/ddi.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/src/ddi/ddi.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup ia64ddi + * @{ + */ +/** @file + */ + +#include +#include +#include +#include + +/** Enable I/O space range for task. + * + * Interrupts are disabled and task is locked. + * + * @param task Task. + * @param ioaddr Startign I/O space address. + * @param size Size of the enabled I/O range. + * + * @return 0 on success or an error code from errno.h. + */ +int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) +{ + return 0; +} + +/** @} + */ Index: kernel/arch/ia64/src/drivers/it.c =================================================================== --- kernel/arch/ia64/src/drivers/it.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) +++ kernel/arch/ia64/src/drivers/it.c (revision 1167520724b9b526c27b67f2d4bc447ef626240c) @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + /** @addtogroup ia64 + * @{ + */ +/** @file + */ + +/** Interval Timer driver. */ + +#include +#include +#include +#include +#include +#include +#include