Index: arch/ia64/include/context.h
===================================================================
--- arch/ia64/include/context.h	(revision e4ddfa83a2097ca2ae503744193865ee77f1ca47)
+++ arch/ia64/include/context.h	(revision 1065603efb7bcf9b443a20c1bfea32b1545909c0)
@@ -98,5 +98,5 @@
 	
 	ipl_t ipl;
-} __attribute__ ((packed));
+};
 
 #endif
Index: arch/ia64/include/interrupt.h
===================================================================
--- arch/ia64/include/interrupt.h	(revision e4ddfa83a2097ca2ae503744193865ee77f1ca47)
+++ arch/ia64/include/interrupt.h	(revision 1065603efb7bcf9b443a20c1bfea32b1545909c0)
@@ -72,5 +72,5 @@
 	__u64 in3;
 	__u64 in4;
-} __attribute__ ((packed));
+};
 
 extern void *ivt;
Index: arch/ia64/src/asm.S
===================================================================
--- arch/ia64/src/asm.S	(revision e4ddfa83a2097ca2ae503744193865ee77f1ca47)
+++ arch/ia64/src/asm.S	(revision 1065603efb7bcf9b443a20c1bfea32b1545909c0)
@@ -61,5 +61,5 @@
 switch_to_userspace:
 	alloc loc0 = ar.pfs, 5, 3, 0, 0
-	rsm (PSR_IC_MASK | PSR_I_MASK)		/* disable interruption collection  and interrupts */
+	rsm (PSR_IC_MASK | PSR_I_MASK)		/* disable interruption collection and interrupts */
 	srlz.d ;;
 	srlz.i ;;
Index: arch/ia64/src/fpu_context.c
===================================================================
--- arch/ia64/src/fpu_context.c	(revision e4ddfa83a2097ca2ae503744193865ee77f1ca47)
+++ arch/ia64/src/fpu_context.c	(revision 1065603efb7bcf9b443a20c1bfea32b1545909c0)
@@ -29,6 +29,8 @@
 
 #include <fpu_context.h>
+#include <print.h>
 
 void fpu_context_save(fpu_context_t *fctx){
+		return;
 		asm volatile(
 			"stf.spill [%2]=f2,0x80\n"
@@ -187,5 +189,5 @@
 void fpu_context_restore(fpu_context_t *fctx)
 {
-
+		return;
 		asm volatile(
 			"ldf.fill f2=[%2],0x80\n"
Index: arch/ia64/src/ia64.c
===================================================================
--- arch/ia64/src/ia64.c	(revision e4ddfa83a2097ca2ae503744193865ee77f1ca47)
+++ arch/ia64/src/ia64.c	(revision 1065603efb7bcf9b443a20c1bfea32b1545909c0)
@@ -78,4 +78,5 @@
 	psr.ic = true;
 	psr.ri = 0;				/* start with instruction #0 */
+	psr.bn = 1;				/* start in bank 0 */
 
 	__asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
Index: arch/ia64/src/ivt.S
===================================================================
--- arch/ia64/src/ivt.S	(revision e4ddfa83a2097ca2ae503744193865ee77f1ca47)
+++ arch/ia64/src/ivt.S	(revision 1065603efb7bcf9b443a20c1bfea32b1545909c0)
@@ -316,5 +316,5 @@
 	mov loc46 = r31
 
-	/*preserve Floating point status register*/
+	/* preserve Floating point status register */
 	mov loc47 = ar.fpsr
     
@@ -376,6 +376,5 @@
 	mov r31 = loc46
 	
-
-	/*restore Floating point status register*/
+	/* restore Floating point status register */
 	mov ar.fpsr = loc47
 	
Index: arch/ia64/src/mm/tlb.c
===================================================================
--- arch/ia64/src/mm/tlb.c	(revision e4ddfa83a2097ca2ae503744193865ee77f1ca47)
+++ arch/ia64/src/mm/tlb.c	(revision 1065603efb7bcf9b443a20c1bfea32b1545909c0)
@@ -43,40 +43,37 @@
 #include <typedefs.h>
 #include <panic.h>
+#include <print.h>
 #include <arch.h>
-
-
 
 /** Invalidate all TLB entries. */
 void tlb_invalidate_all(void)
 {
+		ipl_t ipl;
 		__address adr;
-		__u32 count1,count2,stride1,stride2;
+		__u32 count1, count2, stride1, stride2;
 		
 		int i,j;
 		
-		adr=PAL_PTCE_INFO_BASE();
-		count1=PAL_PTCE_INFO_COUNT1();
-		count2=PAL_PTCE_INFO_COUNT2();
-		stride1=PAL_PTCE_INFO_STRIDE1();
-		stride2=PAL_PTCE_INFO_STRIDE2();
+		adr = PAL_PTCE_INFO_BASE();
+		count1 = PAL_PTCE_INFO_COUNT1();
+		count2 = PAL_PTCE_INFO_COUNT2();
+		stride1 = PAL_PTCE_INFO_STRIDE1();
+		stride2 = PAL_PTCE_INFO_STRIDE2();
 		
-		interrupts_disable();
-
-		for(i=0;i<count1;i++)
-		{
-			for(j=0;j<count2;j++)
-			{
-				asm volatile
-				(
-					"ptc.e %0;;"
+		ipl = interrupts_disable();
+
+		for(i = 0; i < count1; i++) {
+			for(j = 0; j < count2; j++) {
+				__asm__ volatile (
+					"ptc.e %0 ;;"
 					:
-					:"r" (adr)
+					: "r" (adr)
 				);
-				adr+=stride2;
+				adr += stride2;
 			}
-			adr+=stride1;
+			adr += stride1;
 		}
 
-		interrupts_enable();
+		interrupts_restore(ipl);
 
 		srlz_d();
@@ -90,5 +87,4 @@
 void tlb_invalidate_asid(asid_t asid)
 {
-	/* TODO */
 	tlb_invalidate_all();
 }
@@ -97,13 +93,11 @@
 void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
 {
-
-
 	region_register rr;
 	bool restore_rr = false;
-	int b=0;
-	int c=cnt;
+	int b = 0;
+	int c = cnt;
 
 	__address va;
-	va=page;
+	va = page;
 
 	rr.word = rr_read(VA2VRN(va));
@@ -122,80 +116,61 @@
 	}
 	
-	while(c>>=1)	b++;
-	b>>=1;
+	while(c >>= 1)
+		b++;
+	b >>= 1;
 	__u64 ps;
 	
-	switch(b)
-	{
+	switch (b) {
 		case 0: /*cnt 1-3*/
-		{
-			ps=PAGE_WIDTH;
-			break;
-		}
+			ps = PAGE_WIDTH;
+			break;
 		case 1: /*cnt 4-15*/
-		{
 			/*cnt=((cnt-1)/4)+1;*/
-			ps=PAGE_WIDTH+2;
-			va&=~((1<<ps)-1);
-			break;
-		}
+			ps = PAGE_WIDTH+2;
+			va &= ~((1<<ps)-1);
+			break;
 		case 2: /*cnt 16-63*/
-		{
 			/*cnt=((cnt-1)/16)+1;*/
-			ps=PAGE_WIDTH+4;
-			va&=~((1<<ps)-1);
-			break;
-		}
+			ps = PAGE_WIDTH+4;
+			va &= ~((1<<ps)-1);
+			break;
 		case 3: /*cnt 64-255*/
-		{
 			/*cnt=((cnt-1)/64)+1;*/
-			ps=PAGE_WIDTH+6;
-			va&=~((1<<ps)-1);
-			break;
-		}
+			ps = PAGE_WIDTH+6;
+			va &= ~((1<<ps)-1);
+			break;
 		case 4: /*cnt 256-1023*/
-		{
 			/*cnt=((cnt-1)/256)+1;*/
-			ps=PAGE_WIDTH+8;
-			va&=~((1<<ps)-1);
-			break;
-		}
+			ps = PAGE_WIDTH+8;
+			va &= ~((1<<ps)-1);
+			break;
 		case 5: /*cnt 1024-4095*/
-		{
 			/*cnt=((cnt-1)/1024)+1;*/
-			ps=PAGE_WIDTH+10;
-			va&=~((1<<ps)-1);
-			break;
-		}
+			ps = PAGE_WIDTH+10;
+			va &= ~((1<<ps)-1);
+			break;
 		case 6: /*cnt 4096-16383*/
-		{
 			/*cnt=((cnt-1)/4096)+1;*/
-			ps=PAGE_WIDTH+12;
-			va&=~((1<<ps)-1);
-			break;
-		}
+			ps = PAGE_WIDTH+12;
+			va &= ~((1<<ps)-1);
+			break;
 		case 7: /*cnt 16384-65535*/
 		case 8: /*cnt 65536-(256K-1)*/
-		{
 			/*cnt=((cnt-1)/16384)+1;*/
-			ps=PAGE_WIDTH+14;
-			va&=~((1<<ps)-1);
-			break;
-		}
+			ps = PAGE_WIDTH+14;
+			va &= ~((1<<ps)-1);
+			break;
 		default:
-		{
 			/*cnt=((cnt-1)/(16384*16))+1;*/
 			ps=PAGE_WIDTH+18;
 			va&=~((1<<ps)-1);
 			break;
-		}
 	}
 	/*cnt+=(page!=va);*/
-	for(;va<(page+cnt*(PAGE_SIZE));va+=(1<<ps))	{
-		__asm__ volatile 
-		(
+	for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps))	{
+		__asm__ volatile (
 			"ptc.l %0,%1;;"
 			:
-			: "r"(va), "r"(ps<<2)
+			: "r" (va), "r" (ps<<2)
 		);
 	}
@@ -203,5 +178,4 @@
 	srlz_i();
 	
-	
 	if (restore_rr) {
 		rr_write(VA2VRN(va), rr.word);
@@ -209,6 +183,4 @@
 		srlz_i();
 	}
-
-
 }
 
@@ -507,5 +479,5 @@
 		 */
 		if (!as_page_fault(va)) {
-			panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid);
+			panic("%s: va=%P, rid=%d, iip=%P\n", __FUNCTION__, va, rid, istate->cr_iip);
 		}
 	}
@@ -613,5 +585,5 @@
 	} else {
 		if (!as_page_fault(va)) {
-			panic("%s: va=%P, rid=%d\n", __FUNCTION__, istate->cr_ifa, rr.map.rid);
+			panic("%s: va=%P, rid=%d\n", __FUNCTION__, va, rr.map.rid);
 		}
 	}
Index: arch/ia64/src/proc/scheduler.c
===================================================================
--- arch/ia64/src/proc/scheduler.c	(revision e4ddfa83a2097ca2ae503744193865ee77f1ca47)
+++ arch/ia64/src/proc/scheduler.c	(revision 1065603efb7bcf9b443a20c1bfea32b1545909c0)
@@ -63,6 +63,5 @@
 		"bsw.1\n"
 		:
-		: /*"r" (((__address) THREAD->kstack) + ALIGN_UP(sizeof(the_t), REGISTER_STACK_ALIGNMENT)),*/
-		  "r" (&THREAD->kstack[THREAD_STACK_SIZE]),
+		: "r" (&THREAD->kstack[THREAD_STACK_SIZE]),
 		  "r" (&THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA])
 		);
Index: arch/ia64/src/start.S
===================================================================
--- arch/ia64/src/start.S	(revision e4ddfa83a2097ca2ae503744193865ee77f1ca47)
+++ arch/ia64/src/start.S	(revision 1065603efb7bcf9b443a20c1bfea32b1545909c0)
@@ -93,5 +93,4 @@
 	 */
 
-
 	# switch to register bank 1
 	bsw.1