Index: uspace/lib/c/arch/ia64/Makefile.inc =================================================================== --- uspace/lib/c/arch/ia64/Makefile.inc (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/lib/c/arch/ia64/Makefile.inc (revision 105d8d64febd9f6d4257fc2be7aafd3278e7f5f7) @@ -39,5 +39,6 @@ ARCH_AUTOGENS_AG = \ - arch/$(UARCH)/include/libarch/istate_struct.ag + arch/$(UARCH)/include/libarch/istate_struct.ag \ + arch/$(UARCH)/include/libarch/fibril_context.ag .PRECIOUS: arch/$(UARCH)/src/entry.o Index: uspace/lib/c/arch/ia64/include/libarch/fibril.h =================================================================== --- uspace/lib/c/arch/ia64/include/libarch/fibril.h (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/lib/c/arch/ia64/include/libarch/fibril.h (revision 105d8d64febd9f6d4257fc2be7aafd3278e7f5f7) @@ -40,4 +40,5 @@ #include #include +#include /* @@ -64,71 +65,4 @@ } while (0) -/* - * Only save registers that must be preserved across - * function calls. - */ -typedef struct context { - - /* - * Application registers - */ - uint64_t ar_pfs; - uint64_t ar_unat_caller; - uint64_t ar_unat_callee; - uint64_t ar_rsc; - uint64_t bsp; /* ar_bsp */ - uint64_t ar_rnat; - uint64_t ar_lc; - - /* - * General registers - */ - uint64_t r1; - uint64_t r4; - uint64_t r5; - uint64_t r6; - uint64_t r7; - uint64_t sp; /* r12 */ - uint64_t tp; /* r13 */ - - /* - * Branch registers - */ - uint64_t pc; /* b0 */ - uint64_t b1; - uint64_t b2; - uint64_t b3; - uint64_t b4; - uint64_t b5; - - /* - * Predicate registers - */ - uint64_t pr; - - uint128_t f2 __attribute__ ((aligned(16))); - uint128_t f3; - uint128_t f4; - uint128_t f5; - - uint128_t f16; - uint128_t f17; - uint128_t f18; - uint128_t f19; - uint128_t f20; - uint128_t f21; - uint128_t f22; - uint128_t f23; - uint128_t f24; - uint128_t f25; - uint128_t f26; - uint128_t f27; - uint128_t f28; - uint128_t f29; - uint128_t f30; - uint128_t f31; - -} context_t; - static inline uintptr_t context_get_fp(context_t *ctx) { Index: uspace/lib/c/arch/ia64/include/libarch/fibril_context.ag =================================================================== --- uspace/lib/c/arch/ia64/include/libarch/fibril_context.ag (revision 105d8d64febd9f6d4257fc2be7aafd3278e7f5f7) +++ uspace/lib/c/arch/ia64/include/libarch/fibril_context.ag (revision 105d8d64febd9f6d4257fc2be7aafd3278e7f5f7) @@ -0,0 +1,232 @@ +# Copyright (c) 2014 Jakub Jermar +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +{ + name : context, + + includes : [ + { + include : + } + ], + + # + # Only save registers that must be preserved across function calls. + # + members : [ + # + # Application registers + # + { + name : ar_pfs, + type : uint64_t + }, + { + name : ar_unat_caller, + type : uint64_t + }, + { + name : ar_unat_callee, + type : uint64_t + }, + { + name : ar_rsc, + type : uint64_t + }, + { + # ar_bsp + name : bsp, + type : uint64_t + }, + { + name : ar_rnat, + type : uint64_t + }, + { + name : ar_lc, + type : uint64_t + }, + + + # + # General registers + # + { + name : r1, + type : uint64_t + }, + { + name : r4, + type : uint64_t + }, + { + name : r5, + type : uint64_t + }, + { + name : r6, + type : uint64_t + }, + { + name : r7, + type : uint64_t + }, + { + # r12 + name : sp, + type : uint64_t + }, + { + # r13 + name : tp, + type : uint64_t + }, + + + # + # Branch registers + # + { + # b0 + name : pc, + type : uint64_t + }, + { + name : b1, + type : uint64_t + }, + { + name : b2, + type : uint64_t + }, + { + name : b3, + type : uint64_t + }, + { + name : b4, + type : uint64_t + }, + { + name : b5, + type : uint64_t + }, + + + # + # Predicate registers + # + { + name : pr, + type : uint64_t + }, + + { + name : f2, + type : uint128_t + }, + { + name : f3, + type : uint128_t + }, + { + name : f4, + type : uint128_t + }, + { + name : f5, + type : uint128_t + }, + + { + name : f16, + type : uint128_t + }, + { + name : f17, + type : uint128_t + }, + { + name : f18, + type : uint128_t + }, + { + name : f19, + type : uint128_t + }, + { + name : f20, + type : uint128_t + }, + { + name : f21, + type : uint128_t + }, + { + name : f22, + type : uint128_t + }, + { + name : f23, + type : uint128_t + }, + { + name : f24, + type : uint128_t + }, + { + name : f25, + type : uint128_t + }, + { + name : f26, + type : uint128_t + }, + { + name : f27, + type : uint128_t + }, + { + name : f28, + type : uint128_t + }, + { + name : f29, + type : uint128_t + }, + { + name : f30, + type : uint128_t + }, + { + name : f31, + type : uint128_t + } + + ] +} + Index: uspace/lib/c/arch/ia64/src/fibril.S =================================================================== --- uspace/lib/c/arch/ia64/src/fibril.S (revision f3831afcf933f2b3baefc871e81f1735fa29f5a9) +++ uspace/lib/c/arch/ia64/src/fibril.S (revision 105d8d64febd9f6d4257fc2be7aafd3278e7f5f7) @@ -27,4 +27,6 @@ # +#include + .text @@ -33,7 +35,6 @@ context_save: - alloc loc0 = ar.pfs, 1, 8, 0, 0 - mov loc1 = ar.unat ;; - /* loc2 */ + alloc loc0 = ar.pfs, 1, 49, 0, 0 + mov loc1 = ar.unat ;; mov loc3 = ar.rsc @@ -58,93 +59,185 @@ mov loc6 = ar.lc + + add loc8 = CONTEXT_OFFSET_AR_PFS, in0 + add loc9 = CONTEXT_OFFSET_AR_UNAT_CALLER, in0 + add loc10 = CONTEXT_OFFSET_AR_UNAT_CALLEE, in0 + add loc11 = CONTEXT_OFFSET_AR_RSC, in0 + add loc12 = CONTEXT_OFFSET_BSP, in0 + add loc13 = CONTEXT_OFFSET_AR_RNAT, in0 + add loc14 = CONTEXT_OFFSET_AR_LC, in0 + + add loc15 = CONTEXT_OFFSET_R1, in0 + add loc16 = CONTEXT_OFFSET_R4, in0 + add loc17 = CONTEXT_OFFSET_R5, in0 + add loc18 = CONTEXT_OFFSET_R6, in0 + add loc19 = CONTEXT_OFFSET_R7, in0 + add loc20 = CONTEXT_OFFSET_SP, in0 + add loc21 = CONTEXT_OFFSET_TP, in0 + + add loc22 = CONTEXT_OFFSET_PC, in0 + add loc23 = CONTEXT_OFFSET_B1, in0 + add loc24 = CONTEXT_OFFSET_B2, in0 + add loc25 = CONTEXT_OFFSET_B3, in0 + add loc26 = CONTEXT_OFFSET_B4, in0 + add loc27 = CONTEXT_OFFSET_B5, in0 + + add loc28 = CONTEXT_OFFSET_PR, in0 + + add loc29 = CONTEXT_OFFSET_F2, in0 + add loc30 = CONTEXT_OFFSET_F3, in0 + add loc31 = CONTEXT_OFFSET_F4, in0 + add loc32 = CONTEXT_OFFSET_F5, in0 + + add loc33 = CONTEXT_OFFSET_F16, in0 + add loc34 = CONTEXT_OFFSET_F17, in0 + add loc35 = CONTEXT_OFFSET_F18, in0 + add loc36 = CONTEXT_OFFSET_F19, in0 + add loc37 = CONTEXT_OFFSET_F20, in0 + add loc38 = CONTEXT_OFFSET_F21, in0 + add loc39 = CONTEXT_OFFSET_F22, in0 + add loc40 = CONTEXT_OFFSET_F23, in0 + add loc41 = CONTEXT_OFFSET_F24, in0 + add loc42 = CONTEXT_OFFSET_F25, in0 + add loc43 = CONTEXT_OFFSET_F26, in0 + add loc44 = CONTEXT_OFFSET_F27, in0 + add loc45 = CONTEXT_OFFSET_F28, in0 + add loc46 = CONTEXT_OFFSET_F29, in0 + add loc47 = CONTEXT_OFFSET_F30, in0 + add loc48 = CONTEXT_OFFSET_F31, in0 ;; + + /* + * Save general registers including NaT bits + */ + st8.spill [loc15] = r1 ;; + st8.spill [loc16] = r4 ;; + st8.spill [loc17] = r5 ;; + st8.spill [loc18] = r6 ;; + st8.spill [loc19] = r7 ;; + st8.spill [loc20] = r12 ;; /* save sp */ + st8.spill [loc21] = r13 ;; /* save tp */ + + mov loc2 = ar.unat /* * Save application registers */ - st8 [in0] = loc0, 8 ;; /* save ar.pfs */ - st8 [in0] = loc1, 8 ;; /* save ar.unat (caller) */ - mov loc2 = in0 ;; - add in0 = 8, in0 ;; /* skip ar.unat (callee) */ - st8 [in0] = loc3, 8 ;; /* save ar.rsc */ - st8 [in0] = loc4, 8 ;; /* save ar.bsp */ - st8 [in0] = loc5, 8 ;; /* save ar.rnat */ - st8 [in0] = loc6, 8 ;; /* save ar.lc */ - - /* - * Save general registers including NaT bits - */ - st8.spill [in0] = r1, 8 ;; - st8.spill [in0] = r4, 8 ;; - st8.spill [in0] = r5, 8 ;; - st8.spill [in0] = r6, 8 ;; - st8.spill [in0] = r7, 8 ;; - st8.spill [in0] = r12, 8 ;; /* save sp */ - st8.spill [in0] = r13, 8 ;; /* save tp */ - - mov loc3 = ar.unat ;; - st8 [loc2] = loc3 /* save ar.unat (callee) */ + st8 [loc8] = loc0 /* save ar.pfs */ + st8 [loc9] = loc1 ;; /* save ar.unat (caller) */ + st8 [loc10] = loc2 /* save ar.unat (callee) */ + st8 [loc11] = loc3 /* save ar.rsc */ + st8 [loc12] = loc4 /* save ar.bsp */ + st8 [loc13] = loc5 /* save ar.rnat */ + st8 [loc14] = loc6 ;; /* save ar.lc */ /* * Save branch registers */ - mov loc2 = b0 ;; - st8 [in0] = loc2, 8 /* save pc */ - mov loc3 = b1 ;; - st8 [in0] = loc3, 8 - mov loc4 = b2 ;; - st8 [in0] = loc4, 8 - mov loc5 = b3 ;; - st8 [in0] = loc5, 8 - mov loc6 = b4 ;; - st8 [in0] = loc6, 8 - mov loc7 = b5 ;; - st8 [in0] = loc7, 8 + mov loc2 = b0 + mov loc3 = b1 + mov loc4 = b2 + mov loc5 = b3 + mov loc6 = b4 + mov loc7 = b5 ;; + st8 [loc22] = loc2 /* save pc */ + st8 [loc23] = loc3 + st8 [loc24] = loc4 + st8 [loc25] = loc5 + st8 [loc26] = loc6 + st8 [loc27] = loc7 ;; /* * Save predicate registers */ - mov loc2 = pr ;; - st8 [in0] = loc2, 16;; /* Next fpu registers should be spilled to 16B aligned address */ + mov loc2 = pr ;; + st8 [loc28] = loc2 /* * Save floating-point registers. */ - stf.spill [in0] = f2, 16 ;; - stf.spill [in0] = f3, 16 ;; - stf.spill [in0] = f4, 16 ;; - stf.spill [in0] = f5, 16 ;; - - stf.spill [in0] = f16, 16 ;; - stf.spill [in0] = f17, 16 ;; - stf.spill [in0] = f18, 16 ;; - stf.spill [in0] = f19, 16 ;; - stf.spill [in0] = f20, 16 ;; - stf.spill [in0] = f21, 16 ;; - stf.spill [in0] = f22, 16 ;; - stf.spill [in0] = f23, 16 ;; - stf.spill [in0] = f24, 16 ;; - stf.spill [in0] = f25, 16 ;; - stf.spill [in0] = f26, 16 ;; - stf.spill [in0] = f27, 16 ;; - stf.spill [in0] = f28, 16 ;; - stf.spill [in0] = f29, 16 ;; - stf.spill [in0] = f30, 16 ;; - stf.spill [in0] = f31, 16 ;; + stf.spill [loc29] = f2 + stf.spill [loc30] = f3 + stf.spill [loc31] = f4 + stf.spill [loc32] = f5 + + stf.spill [loc33] = f16 + stf.spill [loc34] = f17 + stf.spill [loc35] = f18 + stf.spill [loc36] = f19 + stf.spill [loc37] = f20 + stf.spill [loc38] = f21 + stf.spill [loc39] = f22 + stf.spill [loc40] = f23 + stf.spill [loc41] = f24 + stf.spill [loc42] = f25 + stf.spill [loc43] = f26 + stf.spill [loc44] = f27 + stf.spill [loc45] = f28 + stf.spill [loc46] = f29 + stf.spill [loc47] = f30 + stf.spill [loc48] = f31 mov ar.unat = loc1 - add r8 = r0, r0, 1 /* context_save returns 1 */ + add r8 = r0, r0, 1 /* context_save returns 1 */ br.ret.sptk.many b0 context_restore: - alloc loc0 = ar.pfs, 1, 9, 0, 0 ;; - - ld8 loc0 = [in0], 8 ;; /* load ar.pfs */ - ld8 loc1 = [in0], 8 ;; /* load ar.unat (caller) */ - ld8 loc2 = [in0], 8 ;; /* load ar.unat (callee) */ - ld8 loc3 = [in0], 8 ;; /* load ar.rsc */ - ld8 loc4 = [in0], 8 ;; /* load ar.bsp */ - ld8 loc5 = [in0], 8 ;; /* load ar.rnat */ - ld8 loc6 = [in0], 8 ;; /* load ar.lc */ + alloc loc0 = ar.pfs, 1, 50, 0, 0 ;; + + add loc9 = CONTEXT_OFFSET_AR_PFS, in0 + add loc10 = CONTEXT_OFFSET_AR_UNAT_CALLER, in0 + add loc11 = CONTEXT_OFFSET_AR_UNAT_CALLEE, in0 + add loc12 = CONTEXT_OFFSET_AR_RSC, in0 + add loc13 = CONTEXT_OFFSET_BSP, in0 + add loc14 = CONTEXT_OFFSET_AR_RNAT, in0 + add loc15 = CONTEXT_OFFSET_AR_LC, in0 + + add loc16 = CONTEXT_OFFSET_R1, in0 + add loc17 = CONTEXT_OFFSET_R4, in0 + add loc18 = CONTEXT_OFFSET_R5, in0 + add loc19 = CONTEXT_OFFSET_R6, in0 + add loc20 = CONTEXT_OFFSET_R7, in0 + add loc21 = CONTEXT_OFFSET_SP, in0 + add loc22 = CONTEXT_OFFSET_TP, in0 + + add loc23 = CONTEXT_OFFSET_PC, in0 + add loc24 = CONTEXT_OFFSET_B1, in0 + add loc25 = CONTEXT_OFFSET_B2, in0 + add loc26 = CONTEXT_OFFSET_B3, in0 + add loc27 = CONTEXT_OFFSET_B4, in0 + add loc28 = CONTEXT_OFFSET_B5, in0 + + add loc29 = CONTEXT_OFFSET_PR, in0 + + add loc30 = CONTEXT_OFFSET_F2, in0 + add loc31 = CONTEXT_OFFSET_F3, in0 + add loc32 = CONTEXT_OFFSET_F4, in0 + add loc33 = CONTEXT_OFFSET_F5, in0 + + add loc34 = CONTEXT_OFFSET_F16, in0 + add loc35 = CONTEXT_OFFSET_F17, in0 + add loc36 = CONTEXT_OFFSET_F18, in0 + add loc37 = CONTEXT_OFFSET_F19, in0 + add loc38 = CONTEXT_OFFSET_F20, in0 + add loc39 = CONTEXT_OFFSET_F21, in0 + add loc40 = CONTEXT_OFFSET_F22, in0 + add loc41 = CONTEXT_OFFSET_F23, in0 + add loc42 = CONTEXT_OFFSET_F24, in0 + add loc43 = CONTEXT_OFFSET_F25, in0 + add loc44 = CONTEXT_OFFSET_F26, in0 + add loc45 = CONTEXT_OFFSET_F27, in0 + add loc46 = CONTEXT_OFFSET_F28, in0 + add loc47 = CONTEXT_OFFSET_F29, in0 + add loc48 = CONTEXT_OFFSET_F30, in0 + add loc49 = CONTEXT_OFFSET_F31, in0 ;; + + ld8 loc0 = [loc9] /* load ar.pfs */ + ld8 loc1 = [loc10] /* load ar.unat (caller) */ + ld8 loc2 = [loc11] /* load ar.unat (callee) */ + ld8 loc3 = [loc12] /* load ar.rsc */ + ld8 loc4 = [loc13] /* load ar.bsp */ + ld8 loc5 = [loc14] /* load ar.rnat */ + ld8 loc6 = [loc15] /* load ar.lc */ .auto @@ -180,5 +273,5 @@ .explicit - mov ar.unat = loc2 ;; + mov ar.unat = loc2 ;; mov ar.lc = loc6 @@ -186,32 +279,32 @@ * Restore general registers including NaT bits */ - ld8.fill r1 = [in0], 8 ;; - ld8.fill r4 = [in0], 8 ;; - ld8.fill r5 = [in0], 8 ;; - ld8.fill r6 = [in0], 8 ;; - ld8.fill r7 = [in0], 8 ;; - ld8.fill r12 = [in0], 8 ;; /* restore sp */ - ld8.fill r13 = [in0], 8 ;; + ld8.fill r1 = [loc16] ;; + ld8.fill r4 = [loc17] ;; + ld8.fill r5 = [loc18] ;; + ld8.fill r6 = [loc19] ;; + ld8.fill r7 = [loc20] ;; + ld8.fill r12 = [loc21] ;; /* restore sp */ + ld8.fill r13 = [loc22] ;; /* * Restore branch registers */ - ld8 loc2 = [in0], 8 ;; /* restore pc */ + ld8 loc2 = [loc23] /* restore pc */ + ld8 loc3 = [loc24] + ld8 loc4 = [loc25] + ld8 loc5 = [loc26] + ld8 loc6 = [loc27] + ld8 loc7 = [loc28] ;; mov b0 = loc2 - ld8 loc3 = [in0], 8 ;; mov b1 = loc3 - ld8 loc4 = [in0], 8 ;; mov b2 = loc4 - ld8 loc5 = [in0], 8 ;; mov b3 = loc5 - ld8 loc6 = [in0], 8 ;; mov b4 = loc6 - ld8 loc7 = [in0], 8 ;; - mov b5 = loc7 + mov b5 = loc7 ;; /* * Restore predicate registers */ - ld8 loc2 = [in0], 16 ;; + ld8 loc2 = [loc29] ;; mov pr = loc2, ~0 @@ -219,25 +312,25 @@ * Restore floating-point registers. */ - ldf.fill f2 = [in0], 16 ;; - ldf.fill f3 = [in0], 16 ;; - ldf.fill f4 = [in0], 16 ;; - ldf.fill f5 = [in0], 16 ;; - - ldf.fill f16 = [in0], 16 ;; - ldf.fill f17 = [in0], 16 ;; - ldf.fill f18 = [in0], 16 ;; - ldf.fill f19 = [in0], 16 ;; - ldf.fill f20 = [in0], 16 ;; - ldf.fill f21 = [in0], 16 ;; - ldf.fill f22 = [in0], 16 ;; - ldf.fill f23 = [in0], 16 ;; - ldf.fill f24 = [in0], 16 ;; - ldf.fill f25 = [in0], 16 ;; - ldf.fill f26 = [in0], 16 ;; - ldf.fill f27 = [in0], 16 ;; - ldf.fill f28 = [in0], 16 ;; - ldf.fill f29 = [in0], 16 ;; - ldf.fill f30 = [in0], 16 ;; - ldf.fill f31 = [in0], 16 ;; + ldf.fill f2 = [loc30] + ldf.fill f3 = [loc31] + ldf.fill f4 = [loc32] + ldf.fill f5 = [loc33] + + ldf.fill f16 = [loc34] + ldf.fill f17 = [loc35] + ldf.fill f18 = [loc36] + ldf.fill f19 = [loc37] + ldf.fill f20 = [loc38] + ldf.fill f21 = [loc39] + ldf.fill f22 = [loc40] + ldf.fill f23 = [loc41] + ldf.fill f24 = [loc42] + ldf.fill f25 = [loc43] + ldf.fill f26 = [loc44] + ldf.fill f27 = [loc45] + ldf.fill f28 = [loc46] + ldf.fill f29 = [loc47] + ldf.fill f30 = [loc48] + ldf.fill f31 = [loc49] mov ar.unat = loc1