Index: kernel/arch/abs32le/include/arch/mm/frame.h
===================================================================
--- kernel/arch/abs32le/include/arch/mm/frame.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/abs32le/include/arch/mm/frame.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -39,4 +39,6 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0
+
 #include <typedefs.h>
 
Index: kernel/arch/abs32le/include/arch/mm/page.h
===================================================================
--- kernel/arch/abs32le/include/arch/mm/page.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/abs32le/include/arch/mm/page.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -57,8 +57,8 @@
 
 /* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH  ONE_FRAME
-#define PTL1_SIZE_ARCH  0
-#define PTL2_SIZE_ARCH  0
-#define PTL3_SIZE_ARCH  ONE_FRAME
+#define PTL0_FRAMES_ARCH  1
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating indices for each level. */
Index: kernel/arch/amd64/include/arch/mm/frame.h
===================================================================
--- kernel/arch/amd64/include/arch/mm/frame.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/amd64/include/arch/mm/frame.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -39,4 +39,6 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0x1000
+
 #ifndef __ASM__
 
Index: kernel/arch/amd64/include/arch/mm/page.h
===================================================================
--- kernel/arch/amd64/include/arch/mm/page.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/amd64/include/arch/mm/page.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -61,8 +61,8 @@
 
 /* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH  ONE_FRAME
-#define PTL1_SIZE_ARCH  ONE_FRAME
-#define PTL2_SIZE_ARCH  ONE_FRAME
-#define PTL3_SIZE_ARCH  ONE_FRAME
+#define PTL0_FRAMES_ARCH  1
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating indices into page tables in each level. */
Index: kernel/arch/amd64/src/ddi/ddi.c
===================================================================
--- kernel/arch/amd64/src/ddi/ddi.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/amd64/src/ddi/ddi.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -68,13 +68,13 @@
 		 */
 		
-		void *store = malloc(bitmap_size(elements, 0), FRAME_ATOMIC);
+		void *store = malloc(bitmap_size(elements), FRAME_ATOMIC);
 		if (!store)
 			return ENOMEM;
 		
 		bitmap_t oldiomap;
-		bitmap_initialize(&oldiomap, task->arch.iomap.elements, 0,
+		bitmap_initialize(&oldiomap, task->arch.iomap.elements,
 		    task->arch.iomap.bits);
 		
-		bitmap_initialize(&task->arch.iomap, elements, 0, store);
+		bitmap_initialize(&task->arch.iomap, elements, store);
 		
 		/*
@@ -129,5 +129,5 @@
 		
 		bitmap_t iomap;
-		bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8, 0,
+		bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8,
 		    CPU->arch.tss->iomap);
 		bitmap_copy(&iomap, &TASK->arch.iomap, elements);
@@ -157,5 +157,5 @@
 	
 	descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base;
-	size_t size = bitmap_size(elements, 0);
+	size_t size = bitmap_size(elements);
 	gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + size);
 	gdtr_load(&cpugdtr);
Index: kernel/arch/amd64/src/proc/task.c
===================================================================
--- kernel/arch/amd64/src/proc/task.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/amd64/src/proc/task.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -46,5 +46,5 @@
 {
 	task->arch.iomapver = 0;
-	bitmap_initialize(&task->arch.iomap, 0, 0, NULL);
+	bitmap_initialize(&task->arch.iomap, 0, NULL);
 }
 
Index: kernel/arch/arm32/include/arch/mm/frame.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/frame.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/arm32/include/arch/mm/frame.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -39,4 +39,6 @@
 #define FRAME_WIDTH  12  /* 4KB frames */
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
+
+#define FRAME_LOWPRIO  0
 
 #ifndef __ASM__
Index: kernel/arch/arm32/include/arch/mm/page.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/arm32/include/arch/mm/page.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -73,8 +73,8 @@
 
 /* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH          FOUR_FRAMES
-#define PTL1_SIZE_ARCH          0
-#define PTL2_SIZE_ARCH          0
-#define PTL3_SIZE_ARCH          ONE_FRAME
+#define PTL0_FRAMES_ARCH  4
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating indices into page tables for each level. */
Index: kernel/arch/arm32/include/arch/mm/page_armv4.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv4.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/arm32/include/arch/mm/page_armv4.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -48,5 +48,5 @@
 	(((pte_t *) (pte))->l0.descriptor_type != 0)
 #define PTE_GET_FRAME_ARCH(pte) \
-	(((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
+	(((uintptr_t) ((pte_t *) (pte))->l1.frame_base_addr) << FRAME_WIDTH)
 #define PTE_WRITABLE_ARCH(pte) \
 	(((pte_t *) (pte))->l1.access_permission_0 == PTE_AP_USER_RW_KERNEL_RW)
Index: kernel/arch/arm32/include/arch/mm/page_armv6.h
===================================================================
--- kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/arm32/include/arch/mm/page_armv6.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -48,5 +48,5 @@
 	(((pte_t *) (pte))->l0.descriptor_type != 0)
 #define PTE_GET_FRAME_ARCH(pte) \
-	(((pte_t *) (pte))->l1.frame_base_addr << FRAME_WIDTH)
+	(((uintptr_t) ((pte_t *) (pte))->l1.frame_base_addr) << FRAME_WIDTH)
 #define PTE_WRITABLE_ARCH(pte) \
 	(((pte_t *) (pte))->l1.access_permission_1 != PTE_AP1_RO)
Index: kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c
===================================================================
--- kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/arm32/src/mach/beagleboardxm/beagleboardxm.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -60,5 +60,5 @@
 
 static struct beagleboard {
-	amdm37x_irc_regs_t *irc_addr;
+	omap_irc_regs_t *irc_addr;
 	omap_uart_t uart;
 	amdm37x_gpt_t timer;
@@ -103,5 +103,5 @@
 	    PAGE_NOT_CACHEABLE);
 	ASSERT(beagleboard.irc_addr);
-	amdm37x_irc_init(beagleboard.irc_addr);
+	omap_irc_init(beagleboard.irc_addr);
 
 	/* Initialize timer. Use timer1, because it is in WKUP power domain
@@ -123,5 +123,5 @@
 
 	/* Enable timer interrupt */
-	amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ);
+	omap_irc_enable(beagleboard.irc_addr, AMDM37x_GPT1_IRQ);
 
 	/* Start timer here */
@@ -147,5 +147,5 @@
 static void bbxm_irq_exception(unsigned int exc_no, istate_t *istate)
 {
-	const unsigned inum = amdm37x_irc_inum_get(beagleboard.irc_addr);
+	const unsigned inum = omap_irc_inum_get(beagleboard.irc_addr);
 
 	irq_t *irq = irq_dispatch_and_lock(inum);
@@ -161,5 +161,5 @@
 	/** amdm37x manual ch. 12.5.2 (p. 2428) places irc ack at the end
 	 * of ISR. DO this to avoid strange behavior. */
-	amdm37x_irc_irq_ack(beagleboard.irc_addr);
+	omap_irc_irq_ack(beagleboard.irc_addr);
 }
 
@@ -188,5 +188,5 @@
 		indev_t *srln = srln_wire(srln_instance, sink);
 		omap_uart_input_wire(&beagleboard.uart, srln);
-		amdm37x_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ);
+		omap_irc_enable(beagleboard.irc_addr, AMDM37x_UART3_IRQ);
 	}
 #endif
Index: kernel/arch/arm32/src/mach/beaglebone/beaglebone.c
===================================================================
--- kernel/arch/arm32/src/mach/beaglebone/beaglebone.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/arm32/src/mach/beaglebone/beaglebone.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -63,5 +63,5 @@
 
 static struct beaglebone {
-	am335x_irc_regs_t *irc_addr;
+	omap_irc_regs_t *irc_addr;
 	am335x_cm_per_regs_t *cm_per_addr;
 	am335x_cm_dpll_regs_t *cm_dpll_addr;
@@ -104,5 +104,5 @@
 
 	/* Initialize the interrupt controller */
-	am335x_irc_init(bbone.irc_addr);
+	omap_irc_init(bbone.irc_addr);
 }
 
@@ -153,5 +153,5 @@
 	}
 	/* Enable the interrupt */
-	am335x_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ);
+	omap_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ);
 	/* Start the timer */
 	am335x_timer_start(&bbone.timer);
@@ -176,5 +176,5 @@
 static void bbone_irq_exception(unsigned int exc_no, istate_t *istate)
 {
-	const unsigned inum = am335x_irc_inum_get(bbone.irc_addr);
+	const unsigned inum = omap_irc_inum_get(bbone.irc_addr);
 
 	irq_t *irq = irq_dispatch_and_lock(inum);
@@ -187,5 +187,5 @@
 	}
 
-	am335x_irc_irq_ack(bbone.irc_addr);
+	omap_irc_irq_ack(bbone.irc_addr);
 }
 
@@ -214,5 +214,5 @@
 		indev_t *srln = srln_wire(srln_instance, sink);
 		omap_uart_input_wire(&bbone.uart, srln);
-		am335x_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ);
+		omap_irc_enable(bbone.irc_addr, AM335x_UART0_IRQ);
 	}
 #endif
Index: kernel/arch/arm32/src/mm/frame.c
===================================================================
--- kernel/arch/arm32/src/mm/frame.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/arm32/src/mm/frame.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -88,7 +88,6 @@
 void boot_page_table_free(void)
 {
-	unsigned int i;
-	for (i = 0; i < BOOT_PAGE_TABLE_SIZE_IN_FRAMES; i++)
-		frame_free(i * FRAME_SIZE + BOOT_PAGE_TABLE_ADDRESS);
+	frame_free(BOOT_PAGE_TABLE_ADDRESS,
+	    BOOT_PAGE_TABLE_SIZE_IN_FRAMES);
 }
 
Index: kernel/arch/arm32/src/mm/page.c
===================================================================
--- kernel/arch/arm32/src/mm/page.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/arm32/src/mm/page.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -69,5 +69,5 @@
 #ifdef HIGH_EXCEPTION_VECTORS
 	/* Create mapping for exception table at high offset */
-	uintptr_t ev_frame = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_NONE);
+	uintptr_t ev_frame = frame_alloc(1, FRAME_NONE, 0);
 	page_mapping_insert(AS_KERNEL, EXC_BASE_ADDRESS, ev_frame, flags);
 #else
Index: kernel/arch/arm32/src/ras.c
===================================================================
--- kernel/arch/arm32/src/ras.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/arm32/src/ras.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -51,13 +51,12 @@
 void ras_init(void)
 {
-	uintptr_t frame;
-
-	frame = (uintptr_t) frame_alloc(ONE_FRAME,
-	    FRAME_ATOMIC | FRAME_HIGHMEM);
+	uintptr_t frame =
+	    frame_alloc(1, FRAME_ATOMIC | FRAME_HIGHMEM, 0);
 	if (!frame)
-		frame = (uintptr_t) frame_alloc(ONE_FRAME, FRAME_LOWMEM);
+		frame = frame_alloc(1, FRAME_LOWMEM, 0);
+	
 	ras_page = (uintptr_t *) km_map(frame,
 	    PAGE_SIZE, PAGE_READ | PAGE_WRITE | PAGE_USER | PAGE_CACHEABLE);
-
+	
 	memsetb(ras_page, PAGE_SIZE, 0); 
 	ras_page[RAS_START] = 0;
Index: kernel/arch/ia32/include/arch/mm/frame.h
===================================================================
--- kernel/arch/ia32/include/arch/mm/frame.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/ia32/include/arch/mm/frame.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -39,4 +39,6 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0x1000
+
 #ifndef __ASM__
 
Index: kernel/arch/ia32/include/arch/mm/page.h
===================================================================
--- kernel/arch/ia32/include/arch/mm/page.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/ia32/include/arch/mm/page.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -66,8 +66,8 @@
 
 /* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH  ONE_FRAME
-#define PTL1_SIZE_ARCH  0
-#define PTL2_SIZE_ARCH  0
-#define PTL3_SIZE_ARCH  ONE_FRAME
+#define PTL0_FRAMES_ARCH  1
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating indices for each level. */
Index: kernel/arch/ia32/src/ddi/ddi.c
===================================================================
--- kernel/arch/ia32/src/ddi/ddi.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/ia32/src/ddi/ddi.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -68,13 +68,13 @@
 		 */
 		
-		void *store = malloc(bitmap_size(elements, 0), FRAME_ATOMIC);
+		void *store = malloc(bitmap_size(elements), FRAME_ATOMIC);
 		if (!store)
 			return ENOMEM;
 		
 		bitmap_t oldiomap;
-		bitmap_initialize(&oldiomap, task->arch.iomap.elements, 0,
+		bitmap_initialize(&oldiomap, task->arch.iomap.elements,
 		    task->arch.iomap.bits);
 		
-		bitmap_initialize(&task->arch.iomap, elements, 0, store);
+		bitmap_initialize(&task->arch.iomap, elements, store);
 		
 		/*
@@ -129,5 +129,5 @@
 		
 		bitmap_t iomap;
-		bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8, 0,
+		bitmap_initialize(&iomap, TSS_IOMAP_SIZE * 8,
 		    CPU->arch.tss->iomap);
 		bitmap_copy(&iomap, &TASK->arch.iomap, elements);
@@ -157,5 +157,5 @@
 	
 	descriptor_t *gdt_p = (descriptor_t *) cpugdtr.base;
-	size_t size = bitmap_size(elements, 0);
+	size_t size = bitmap_size(elements);
 	gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + size);
 	gdtr_load(&cpugdtr);
Index: kernel/arch/ia32/src/mm/frame.c
===================================================================
--- kernel/arch/ia32/src/mm/frame.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/ia32/src/mm/frame.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -47,5 +47,4 @@
 
 #define PHYSMEM_LIMIT32  UINT64_C(0x100000000)
-#define PHYSMEM_LIMIT_DMA   UINT64_C(0x1000000)
 
 size_t hardcoded_unmapped_ktext_size = 0;
@@ -92,26 +91,11 @@
 				else
 					conf = minconf;
-
-				if ((pfn * PAGE_SIZE) < PHYSMEM_LIMIT_DMA) {
-					size_t dma_count = min(
-					    PHYSMEM_LIMIT_DMA / PAGE_SIZE - pfn,
-					    count);
-					zone_create(pfn, dma_count, conf,
-					    ZONE_AVAILABLE | ZONE_DMA);
-					count -= dma_count;
-					pfn += dma_count;
-				}
-
-				conf = pfn;
-				if (count) {
-					zone_create(pfn, count, conf,
-					    ZONE_AVAILABLE | ZONE_LOWMEM);
-				}
+				zone_create(pfn, count, conf,
+				    ZONE_AVAILABLE | ZONE_LOWMEM);
 			} else {
 				conf = zone_external_conf_alloc(count);
-				if (conf != 0) {
+				if (conf != 0)
 					zone_create(pfn, count, conf,
 					    ZONE_AVAILABLE | ZONE_HIGHMEM);
-				}
 			}
 		} else if ((e820table[i].type == MEMMAP_MEMORY_ACPI) ||
Index: kernel/arch/ia32/src/proc/task.c
===================================================================
--- kernel/arch/ia32/src/proc/task.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/ia32/src/proc/task.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -46,5 +46,5 @@
 {
 	task->arch.iomapver = 0;
-	bitmap_initialize(&task->arch.iomap, 0, 0, NULL);
+	bitmap_initialize(&task->arch.iomap, 0, NULL);
 }
 
Index: kernel/arch/ia64/include/arch/mm/frame.h
===================================================================
--- kernel/arch/ia64/include/arch/mm/frame.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/ia64/include/arch/mm/frame.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -39,4 +39,6 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0
+
 #ifndef __ASM__
 
Index: kernel/arch/ia64/src/ddi/ddi.c
===================================================================
--- kernel/arch/ia64/src/ddi/ddi.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/ia64/src/ddi/ddi.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -1,5 +1,5 @@
 /*
  * Copyright (c) 2006 Jakub Jermar
- * Copyright (c) 2008 Jakub vana
+ * Copyright (c) 2008 Jakub Vana
  * All rights reserved.
  *
@@ -60,9 +60,9 @@
 			return ENOMEM;
 		
-		void *store = malloc(bitmap_size(IO_MEMMAP_PAGES, 0), 0);
+		void *store = malloc(bitmap_size(IO_MEMMAP_PAGES), 0);
 		if (store == NULL)
 			return ENOMEM;
 		
-		bitmap_initialize(task->arch.iomap, IO_MEMMAP_PAGES, 0, store);
+		bitmap_initialize(task->arch.iomap, IO_MEMMAP_PAGES, store);
 		bitmap_clear_range(task->arch.iomap, 0, IO_MEMMAP_PAGES);
 	}
Index: kernel/arch/ia64/src/mm/vhpt.c
===================================================================
--- kernel/arch/ia64/src/mm/vhpt.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/ia64/src/mm/vhpt.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -42,8 +42,10 @@
 uintptr_t vhpt_set_up(void)
 {
-	vhpt_base = frame_alloc(VHPT_WIDTH - FRAME_WIDTH,
-	    FRAME_KA | FRAME_ATOMIC);
-	if (!vhpt_base)
+	uintptr_t vhpt_frame =
+	    frame_alloc(SIZE2FRAMES(VHPT_SIZE), FRAME_ATOMIC, 0);
+	if (!vhpt_frame)
 		panic("Kernel configured with VHPT but no memory for table.");
+	
+	vhpt_base = (vhpt_entry_t *) PA2KA(vhpt_frame);
 	vhpt_invalidate_all();
 	return (uintptr_t) vhpt_base;
@@ -82,5 +84,5 @@
 void vhpt_invalidate_all()
 {
-	memsetb(vhpt_base, 1 << VHPT_WIDTH, 0);
+	memsetb(vhpt_base, VHPT_SIZE, 0);
 }
 
Index: kernel/arch/mips32/include/arch/asm.h
===================================================================
--- kernel/arch/mips32/include/arch/asm.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/mips32/include/arch/asm.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -42,12 +42,5 @@
 NO_TRACE static inline void cpu_sleep(void)
 {
-	/*
-	 * Unfortunatelly most of the simulators do not support
-	 *
-	 * asm volatile (
-	 *     "wait"
-	 * );
-	 *
-	 */
+	asm volatile ("wait");
 }
 
Index: kernel/arch/mips32/include/arch/mm/frame.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/frame.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/mips32/include/arch/mm/frame.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -39,4 +39,6 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0
+
 #ifndef __ASM__
 
Index: kernel/arch/mips32/include/arch/mm/page.h
===================================================================
--- kernel/arch/mips32/include/arch/mm/page.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/mips32/include/arch/mm/page.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup mips32mm	
+/** @addtogroup mips32mm
  * @{
  */
@@ -70,27 +70,27 @@
  * - PTL3 has 4096 entries (12 bits)
  */
- 
+
 /* Macros describing number of entries in each level. */
-#define PTL0_ENTRIES_ARCH	64
-#define PTL1_ENTRIES_ARCH	0
-#define PTL2_ENTRIES_ARCH	0
-#define PTL3_ENTRIES_ARCH	4096
+#define PTL0_ENTRIES_ARCH  64
+#define PTL1_ENTRIES_ARCH  0
+#define PTL2_ENTRIES_ARCH  0
+#define PTL3_ENTRIES_ARCH  4096
 
 /* Macros describing size of page tables in each level. */
-#define PTL0_SIZE_ARCH		ONE_FRAME
-#define PTL1_SIZE_ARCH		0
-#define PTL2_SIZE_ARCH		0
-#define PTL3_SIZE_ARCH		ONE_FRAME
+#define PTL0_FRAMES_ARCH  1
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating entry indices for each level. */
-#define PTL0_INDEX_ARCH(vaddr)	((vaddr) >> 26) 
-#define PTL1_INDEX_ARCH(vaddr)	0
-#define PTL2_INDEX_ARCH(vaddr)	0
-#define PTL3_INDEX_ARCH(vaddr)	(((vaddr) >> 14) & 0xfff)
+#define PTL0_INDEX_ARCH(vaddr)  ((vaddr) >> 26)
+#define PTL1_INDEX_ARCH(vaddr)  0
+#define PTL2_INDEX_ARCH(vaddr)  0
+#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 14) & 0xfff)
 
 /* Set accessor for PTL0 address. */
 #define SET_PTL0_ADDRESS_ARCH(ptl0)
 
-/* Get PTE address accessors for each level. */ 
+/* Get PTE address accessors for each level. */
 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
 	(((pte_t *) (ptl0))[(i)].pfn << 12)
@@ -196,5 +196,4 @@
 	p->p = 1;
 }
-	
 
 extern void page_arch_init(void);
Index: kernel/arch/mips32/src/mach/malta/malta.c
===================================================================
--- kernel/arch/mips32/src/mach/malta/malta.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/mips32/src/mach/malta/malta.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -103,4 +103,5 @@
 void malta_input_init(void)
 {
+	(void) stdin_wire();
 }
 
Index: kernel/arch/mips32/src/mm/tlb.c
===================================================================
--- kernel/arch/mips32/src/mm/tlb.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/mips32/src/mm/tlb.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -48,14 +48,16 @@
 #include <symtab.h>
 
-#define PFN_SHIFT	12
-#define VPN_SHIFT	12
-#define ADDR2VPN(a)	((a) >> VPN_SHIFT)
-#define ADDR2VPN2(a)	(ADDR2VPN((a)) >> 1)
-#define VPN2ADDR(vpn)	((vpn) << VPN_SHIFT)
-#define VPN22ADDR(vpn2)	(VPN2ADDR(vpn2) << 1)
-#define PFN2ADDR(pfn)	((pfn) << PFN_SHIFT)
-
-#define BANK_SELECT_BIT(a)	(((a) >> PAGE_WIDTH) & 1) 
-	
+#define PFN_SHIFT  12
+#define VPN_SHIFT  12
+
+#define ADDR2HI_VPN(a)   ((a) >> VPN_SHIFT)
+#define ADDR2HI_VPN2(a)  (ADDR2HI_VPN((a)) >> 1)
+
+#define HI_VPN2ADDR(vpn)    ((vpn) << VPN_SHIFT)
+#define HI_VPN22ADDR(vpn2)  (HI_VPN2ADDR(vpn2) << 1)
+
+#define LO_PFN2ADDR(pfn)  ((pfn) << PFN_SHIFT)
+
+#define BANK_SELECT_BIT(a)  (((a) >> PAGE_WIDTH) & 1)
 
 /** Initialize TLB.
@@ -266,5 +268,5 @@
 {
 	hi->value = 0;
-	hi->vpn2 = ADDR2VPN2(ALIGN_DOWN(addr, PAGE_SIZE));
+	hi->vpn2 = ADDR2HI_VPN2(ALIGN_DOWN(addr, PAGE_SIZE));
 	hi->asid = asid;
 }
@@ -295,8 +297,8 @@
 		
 		printf("%-4u %-6u %0#10x %-#6x  %1u%1u%1u%1u  %0#10x\n",
-		    i, hi.asid, VPN22ADDR(hi.vpn2), mask.mask,
-		    lo0.g, lo0.v, lo0.d, lo0.c, PFN2ADDR(lo0.pfn));
+		    i, hi.asid, HI_VPN22ADDR(hi.vpn2), mask.mask,
+		    lo0.g, lo0.v, lo0.d, lo0.c, LO_PFN2ADDR(lo0.pfn));
 		printf("                               %1u%1u%1u%1u  %0#10x\n",
-		    lo1.g, lo1.v, lo1.d, lo1.c, PFN2ADDR(lo1.pfn));
+		    lo1.g, lo1.v, lo1.d, lo1.c, LO_PFN2ADDR(lo1.pfn));
 	}
 	
Index: kernel/arch/mips64/include/arch/mm/frame.h
===================================================================
--- kernel/arch/mips64/include/arch/mm/frame.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/mips64/include/arch/mm/frame.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -39,4 +39,6 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0
+
 #ifndef __ASM__
 
Index: kernel/arch/ppc32/include/arch/mm/frame.h
===================================================================
--- kernel/arch/ppc32/include/arch/mm/frame.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/ppc32/include/arch/mm/frame.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -39,4 +39,6 @@
 #define FRAME_SIZE   (1 << FRAME_WIDTH)
 
+#define FRAME_LOWPRIO  0
+
 #ifndef __ASM__
 
Index: kernel/arch/ppc32/include/arch/mm/page.h
===================================================================
--- kernel/arch/ppc32/include/arch/mm/page.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/ppc32/include/arch/mm/page.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -70,8 +70,8 @@
 
 /* Page table sizes for each level. */
-#define PTL0_SIZE_ARCH  ONE_FRAME
-#define PTL1_SIZE_ARCH  0
-#define PTL2_SIZE_ARCH  0
-#define PTL3_SIZE_ARCH  ONE_FRAME
+#define PTL0_FRAMES_ARCH  1
+#define PTL1_FRAMES_ARCH  1
+#define PTL2_FRAMES_ARCH  1
+#define PTL3_FRAMES_ARCH  1
 
 /* Macros calculating indices into page tables on each level. */
Index: kernel/arch/sparc64/include/arch/mm/sun4u/frame.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4u/frame.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/sparc64/include/arch/mm/sun4u/frame.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -41,6 +41,6 @@
  * Therefore, the kernel uses 8K only internally on the TLB and TSB levels.
  */
-#define MMU_FRAME_WIDTH		13	/* 8K */
-#define MMU_FRAME_SIZE		(1 << MMU_FRAME_WIDTH)
+#define MMU_FRAME_WIDTH  13  /* 8K */
+#define MMU_FRAME_SIZE   (1 << MMU_FRAME_WIDTH)
 
 /*
@@ -49,6 +49,8 @@
  * each 16K page with a pair of adjacent 8K pages.
  */
-#define FRAME_WIDTH		14	/* 16K */
-#define FRAME_SIZE		(1 << FRAME_WIDTH)
+#define FRAME_WIDTH  14  /* 16K */
+#define FRAME_SIZE   (1 << FRAME_WIDTH)
+
+#define FRAME_LOWPRIO  0
 
 #ifndef __ASM__
Index: kernel/arch/sparc64/include/arch/mm/sun4v/frame.h
===================================================================
--- kernel/arch/sparc64/include/arch/mm/sun4v/frame.h	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/sparc64/include/arch/mm/sun4v/frame.h	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -27,5 +27,5 @@
  */
 
-/** @addtogroup sparc64mm	
+/** @addtogroup sparc64mm
  * @{
  */
@@ -36,9 +36,11 @@
 #define KERN_sparc64_sun4v_FRAME_H_
 
-#define MMU_FRAME_WIDTH		13	/* 8K */
-#define MMU_FRAME_SIZE		(1 << MMU_FRAME_WIDTH)
+#define MMU_FRAME_WIDTH  13  /* 8K */
+#define MMU_FRAME_SIZE   (1 << MMU_FRAME_WIDTH)
 
-#define FRAME_WIDTH		13
-#define FRAME_SIZE		(1 << FRAME_WIDTH)
+#define FRAME_WIDTH  13
+#define FRAME_SIZE   (1 << FRAME_WIDTH)
+
+#define FRAME_LOWPRIO  0
 
 #endif
Index: kernel/arch/sparc64/src/mm/sun4u/as.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4u/as.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/sparc64/src/mm/sun4u/as.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -63,40 +63,30 @@
 {
 #ifdef CONFIG_TSB
-	/*
-	 * The order must be calculated with respect to the emulated
-	 * 16K page size.
-	 *
-	 */
-	uint8_t order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
-	    sizeof(tsb_entry_t)) >> FRAME_WIDTH);
-	
-	uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA);
-	
-	if (!tsb)
+	uintptr_t tsb_phys =
+	    frame_alloc(SIZE2FRAMES((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
+	    sizeof(tsb_entry_t)), flags, 0);
+	if (!tsb_phys)
 		return -1;
 	
-	as->arch.itsb = (tsb_entry_t *) tsb;
-	as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
+	tsb_entry_t *tsb = (tsb_entry_t *) PA2KA(tsb_phys);
+	
+	as->arch.itsb = tsb;
+	as->arch.dtsb = tsb + ITSB_ENTRY_COUNT;
+	
+	memsetb(as->arch.itsb, (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
+	    sizeof(tsb_entry_t), 0);
+#endif
+	
+	return 0;
+}
+
+int as_destructor_arch(as_t *as)
+{
+#ifdef CONFIG_TSB
+	size_t frames = SIZE2FRAMES((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
 	    sizeof(tsb_entry_t));
-	
-	memsetb(as->arch.itsb,
-	    (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);
-#endif
-	
-	return 0;
-}
-
-int as_destructor_arch(as_t *as)
-{
-#ifdef CONFIG_TSB
-	/*
-	 * The count must be calculated with respect to the emualted 16K page
-	 * size.
-	 */
-	size_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
-	    sizeof(tsb_entry_t)) >> FRAME_WIDTH;
-	frame_free(KA2PA((uintptr_t) as->arch.itsb));
-	
-	return cnt;
+	frame_free(KA2PA((uintptr_t) as->arch.itsb), frames);
+	
+	return frames;
 #else
 	return 0;
Index: kernel/arch/sparc64/src/mm/sun4v/as.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4v/as.c	(revision f7a33dea6c14aefebb1d11fcaf8d904947793cad)
+++ kernel/arch/sparc64/src/mm/sun4v/as.c	(revision 0e183dd9fab1317745c3e4240ae7febea5010586)
@@ -66,9 +66,7 @@
 {
 #ifdef CONFIG_TSB
-	uint8_t order = fnzb32(
-		(TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH);
-	
-	uintptr_t tsb = (uintptr_t) frame_alloc(order, flags);
-	
+	uintptr_t tsb =
+	    frame_alloc(SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t)),
+	    flags, 0);
 	if (!tsb)
 		return -1;
@@ -92,8 +90,8 @@
 {
 #ifdef CONFIG_TSB
-	size_t cnt = (TSB_ENTRY_COUNT * sizeof(tsb_entry_t)) >> FRAME_WIDTH;
-	frame_free((uintptr_t) as->arch.tsb_description.tsb_base);
+	size_t frames = SIZE2FRAMES(TSB_ENTRY_COUNT * sizeof(tsb_entry_t));
+	frame_free(as->arch.tsb_description.tsb_base, frames);
 	
-	return cnt;
+	return frames;
 #else
 	return 0;