Index: kernel/arch/abs32le/include/arch/asm.h
===================================================================
--- kernel/arch/abs32le/include/arch/asm.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/abs32le/include/arch/asm.h	(revision 0c793e2e9c4358a2bb2521d35eb36b273cf0283b)
@@ -50,5 +50,5 @@
 	   low-power mode) without any possibility of exitting
 	   this function. */
-	
+
 	while (true);
 }
@@ -137,5 +137,5 @@
 	 * The return value stores the previous interrupt level.
 	 */
-	
+
 	return 0;
 }
@@ -151,5 +151,5 @@
 	 * The return value stores the previous interrupt level.
 	 */
-	
+
 	return 0;
 }
@@ -169,5 +169,5 @@
 	 * level.
 	 */
-	
+
 	return 0;
 }
@@ -179,5 +179,5 @@
 	 * disabled.
 	 */
-	
+
 	return false;
 }
@@ -192,5 +192,5 @@
 	 * address space.
 	 */
-	
+
 	return 0;
 }
Index: kernel/arch/abs32le/include/arch/atomic.h
===================================================================
--- kernel/arch/abs32le/include/arch/atomic.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/abs32le/include/arch/atomic.h	(revision 0c793e2e9c4358a2bb2521d35eb36b273cf0283b)
@@ -49,5 +49,5 @@
 	/* On real hardware the increment has to be done
 	   as an atomic action. */
-	
+
 	val->count++;
 }
@@ -60,5 +60,5 @@
 	/* On real hardware the decrement has to be done
 	   as an atomic action. */
-	
+
 	val->count--;
 }
@@ -72,7 +72,7 @@
 	   value and the increment have to be done as a single
 	   atomic action. */
-	
+
 	atomic_count_t prev = val->count;
-	
+
 	val->count++;
 	return prev;
@@ -87,7 +87,7 @@
 	   value and the decrement have to be done as a single
 	   atomic action. */
-	
+
 	atomic_count_t prev = val->count;
-	
+
 	val->count--;
 	return prev;
@@ -104,5 +104,5 @@
 	   value and storing 1 have to be done as a single
 	   atomic action. */
-	
+
 	atomic_count_t prev = val->count;
 	val->count = 1;
Index: kernel/arch/abs32le/include/arch/istate.h
===================================================================
--- kernel/arch/abs32le/include/arch/istate.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/abs32le/include/arch/istate.h	(revision 0c793e2e9c4358a2bb2521d35eb36b273cf0283b)
@@ -67,5 +67,5 @@
 	/* On real hardware this checks whether the interrupted
 	   context originated from user space. */
-	
+
 	return !(istate->ip & UINT32_C(0x80000000));
 }
@@ -76,5 +76,5 @@
 {
 	/* On real hardware this sets the instruction pointer. */
-	
+
 	istate->ip = retaddr;
 }
@@ -84,5 +84,5 @@
 {
 	/* On real hardware this returns the instruction pointer. */
-	
+
 	return istate->ip;
 }
@@ -92,5 +92,5 @@
 {
 	/* On real hardware this returns the frame pointer. */
-	
+
 	return istate->fp;
 }
Index: kernel/arch/abs32le/include/arch/mm/page.h
===================================================================
--- kernel/arch/abs32le/include/arch/mm/page.h	(revision 1b20da07baaa3e3c424f62c927274e676e4295cd)
+++ kernel/arch/abs32le/include/arch/mm/page.h	(revision 0c793e2e9c4358a2bb2521d35eb36b273cf0283b)
@@ -140,5 +140,5 @@
 	unsigned int pat : 1;
 	unsigned int global : 1;
-	
+
 	/** Valid content even if the present bit is not set. */
 	unsigned int soft_valid : 1;
@@ -151,5 +151,5 @@
 {
 	pte_t *p = &pt[i];
-	
+
 	return (
 	    ((unsigned int) (!p->page_cache_disable) << PAGE_CACHEABLE_SHIFT) |
@@ -168,5 +168,5 @@
 {
 	pte_t *p = &pt[i];
-	
+
 	p->page_cache_disable = !(flags & PAGE_CACHEABLE);
 	p->present = !(flags & PAGE_NOT_PRESENT);
@@ -174,5 +174,5 @@
 	p->writeable = (flags & PAGE_WRITE) != 0;
 	p->global = (flags & PAGE_GLOBAL) != 0;
-	
+
 	/*
 	 * Ensure that there is at least one bit set even if the present bit is