Changeset 0c40fd5 in mainline for kernel/arch/arm32/include/arch/cp15.h

Timestamp:

2013-08-07T18:38:44Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ae5fb7c8

Parents:

8ff767b

Message:

arm32: Fix pagetables in cacheable memory.

Set memory attributes in TTBR0/1

File:

• kernel/arch/arm32/include/arch/cp15.h (modified) (1 diff)

kernel/arch/arm32/include/arch/cp15.h

@@ -301 +301 @@
 
 /* Memory protection and control registers */
+enum {
+        TTBR_ADDR_MASK = 0xffffff80,
+        TTBR_NOS_FLAG = 1 << 5,
+        TTBR_RGN_MASK = 0x3 << 3,
+        TTBR_RGN_NO_CACHE = 0x0 << 3,
+        TTBR_RGN_WBWA_CACHE = 0x1 << 3,
+        TTBR_RGN_WT_CACHE = 0x2 << 3,
+        TTBR_RGN_WB_CACHE = 0x3 << 3,
+        TTBR_S_FLAG = 1 << 1,
+        TTBR_C_FLAG = 1 << 0,
+};
 CONTROL_REG_GEN_READ(TTBR0, c2, 0, c0, 0);
 CONTROL_REG_GEN_WRITE(TTBR0, c2, 0, c0, 0);