Changeset 0c12dfe in mainline
- Timestamp:
- 2012-11-20T12:57:46Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 9c0eba6
- Parents:
- 68338c6
- Location:
- uspace/drv/infrastructure/rootamdm37x
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/infrastructure/rootamdm37x/cm/mpu.h
r68338c6 r0c12dfe 87 87 88 88 const ioport32_t clkstst; 89 #define MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTI CE_FLAG (1 << 0)89 #define MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG (1 << 0) 90 90 91 91 } mpu_cm_regs_t; -
uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c
r68338c6 r0c12dfe 155 155 156 156 /* Current MPU frequency. */ 157 if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTI CE_FLAG) {157 if (pio_read_32(&mpu->clkstst) & MPU_CM_CLKSTST_CLKACTIVITY_MPU_ACTIVE_FLAG) { 158 158 if (pio_read_32(&mpu->idlest_pll) & MPU_CM_IDLEST_PLL_ST_MPU_CLK_LOCKED_FLAG) { 159 159 /* DPLL active and locked */ … … 224 224 * we can probably turn this off entirely (DSS is still non-functional). 225 225 */ 226 /* Set DPLL4 to automatic to save power */226 /* Set DPLL4 to automatic to save power */ 227 227 pio_change_32(&device->cm.clocks->autoidle_pll, 228 228 CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC, … … 234 234 */ 235 235 // TODO setup DPLL5 236 /* Set DPLL5 to automatic */236 /* Set DPLL5 to automatic to save power */ 237 237 pio_change_32(&device->cm.clocks->autoidle2_pll, 238 238 CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_AUTOMATIC,
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