Index: kernel/arch/abs32le/include/types.h
===================================================================
--- kernel/arch/abs32le/include/types.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/abs32le/include/types.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -46,5 +46,5 @@
 typedef uint32_t ipl_t;
 
-typedef uint32_t unative_t;
+typedef uint32_t sysarg_t;
 typedef int32_t native_t;
 typedef uint32_t atomic_count_t;
@@ -57,6 +57,6 @@
 
 #define PRIdn  PRId32  /**< Format for native_t. */
-#define PRIun  PRIu32  /**< Format for unative_t. */
-#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
+#define PRIun  PRIu32  /**< Format for sysarg_t. */
+#define PRIxn  PRIx32  /**< Format for hexadecimal sysarg_t. */
 #define PRIua  PRIu32  /**< Format for atomic_count_t. */
 
Index: kernel/arch/abs32le/src/abs32le.c
===================================================================
--- kernel/arch/abs32le/src/abs32le.c	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/abs32le/src/abs32le.c	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -86,5 +86,5 @@
 }
 
-unative_t sys_tls_set(unative_t addr)
+sysarg_t sys_tls_set(sysarg_t addr)
 {
 	return EOK;
Index: kernel/arch/amd64/include/asm.h
===================================================================
--- kernel/arch/amd64/include/asm.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/amd64/include/asm.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -304,5 +304,5 @@
 }
 
-NO_TRACE static inline unative_t read_msr(uint32_t msr)
+NO_TRACE static inline sysarg_t read_msr(uint32_t msr)
 {
 	uint32_t ax, dx;
@@ -343,5 +343,5 @@
 	asm volatile (
 		"invlpg %[addr]\n"
-		:: [addr] "m" (*((unative_t *) addr))
+		:: [addr] "m" (*((sysarg_t *) addr))
 	);
 }
@@ -398,7 +398,7 @@
 }
 
-#define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \
+#define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \
 	{ \
-		unative_t res; \
+		sysarg_t res; \
 		asm volatile ( \
 			"movq %%" #reg ", %[res]" \
@@ -408,5 +408,5 @@
 	}
 
-#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \
+#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
 	{ \
 		asm volatile ( \
Index: kernel/arch/amd64/include/proc/thread.h
===================================================================
--- kernel/arch/amd64/include/proc/thread.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/amd64/include/proc/thread.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -41,5 +41,5 @@
 
 typedef struct {
-	unative_t tls;
+	sysarg_t tls;
 	/** User and kernel RSP for syscalls. */
 	uint64_t syscall_rsp[2];
Index: kernel/arch/amd64/include/types.h
===================================================================
--- kernel/arch/amd64/include/types.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/amd64/include/types.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -43,5 +43,5 @@
 typedef uint64_t ipl_t;
 
-typedef uint64_t unative_t;
+typedef uint64_t sysarg_t;
 typedef int64_t native_t;
 typedef uint64_t atomic_count_t;
@@ -54,6 +54,6 @@
 
 #define PRIdn  PRId64  /**< Format for native_t. */
-#define PRIun  PRIu64  /**< Format for unative_t. */
-#define PRIxn  PRIx64  /**< Format for hexadecimal unative_t. */
+#define PRIun  PRIu64  /**< Format for sysarg_t. */
+#define PRIxn  PRIx64  /**< Format for hexadecimal sysarg_t. */
 #define PRIua  PRIu64  /**< Format for atomic_count_t. */
 
Index: kernel/arch/amd64/src/amd64.c
===================================================================
--- kernel/arch/amd64/src/amd64.c	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/amd64/src/amd64.c	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -256,5 +256,5 @@
  * we need not to go to CPL0 to read it.
  */
-unative_t sys_tls_set(unative_t addr)
+sysarg_t sys_tls_set(sysarg_t addr)
 {
 	THREAD->arch.tls = addr;
Index: kernel/arch/amd64/src/debugger.c
===================================================================
--- kernel/arch/amd64/src/debugger.c	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/amd64/src/debugger.c	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -125,5 +125,5 @@
 	
 	/* Disable breakpoint in DR7 */
-	unative_t dr7 = read_dr7();
+	sysarg_t dr7 = read_dr7();
 	dr7 &= ~(0x02U << (curidx * 2));
 	
@@ -152,15 +152,15 @@
 		if (!(flags & BKPOINT_INSTR)) {
 #ifdef __32_BITS__
-			dr7 |= ((unative_t) 0x03U) << (18 + 4 * curidx);
+			dr7 |= ((sysarg_t) 0x03U) << (18 + 4 * curidx);
 #endif
 			
 #ifdef __64_BITS__
-			dr7 |= ((unative_t) 0x02U) << (18 + 4 * curidx);
+			dr7 |= ((sysarg_t) 0x02U) << (18 + 4 * curidx);
 #endif
 			
 			if ((flags & BKPOINT_WRITE))
-				dr7 |= ((unative_t) 0x01U) << (16 + 4 * curidx);
+				dr7 |= ((sysarg_t) 0x01U) << (16 + 4 * curidx);
 			else if ((flags & BKPOINT_READ_WRITE))
-				dr7 |= ((unative_t) 0x03U) << (16 + 4 * curidx);
+				dr7 |= ((sysarg_t) 0x03U) << (16 + 4 * curidx);
 		}
 		
@@ -227,5 +227,5 @@
 	if (!(breakpoints[slot].flags & BKPOINT_INSTR)) {
 		if ((breakpoints[slot].flags & BKPOINT_CHECK_ZERO)) {
-			if (*((unative_t *) breakpoints[slot].address) != 0)
+			if (*((sysarg_t *) breakpoints[slot].address) != 0)
 				return;
 			
@@ -234,5 +234,5 @@
 		} else {
 			printf("Data watchpoint - new data: %#" PRIxn "\n",
-			    *((unative_t *) breakpoints[slot].address));
+			    *((sysarg_t *) breakpoints[slot].address));
 		}
 	}
@@ -279,5 +279,5 @@
 #endif
 	
-	unative_t dr6 = read_dr6();
+	sysarg_t dr6 = read_dr6();
 	
 	unsigned int i;
@@ -384,5 +384,5 @@
 int cmd_del_breakpoint(cmd_arg_t *argv)
 {
-	unative_t bpno = argv->intval;
+	sysarg_t bpno = argv->intval;
 	if (bpno > BKPOINTS_MAX) {
 		printf("Invalid breakpoint number.\n");
Index: kernel/arch/arm32/include/types.h
===================================================================
--- kernel/arch/arm32/include/types.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/arm32/include/types.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -50,5 +50,5 @@
 typedef uint32_t ipl_t;
 
-typedef uint32_t unative_t;
+typedef uint32_t sysarg_t;
 typedef int32_t native_t;
 typedef uint32_t atomic_count_t;
@@ -61,6 +61,6 @@
 
 #define PRIdn  PRId32  /**< Format for native_t. */
-#define PRIun  PRIu32  /**< Format for unative_t. */
-#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
+#define PRIun  PRIu32  /**< Format for sysarg_t. */
+#define PRIxn  PRIx32  /**< Format for hexadecimal sysarg_t. */
 #define PRIua  PRIu32  /**< Format for atomic_count_t. */
 
Index: kernel/arch/arm32/src/mach/testarm/testarm.c
===================================================================
--- kernel/arch/arm32/src/mach/testarm/testarm.c	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/arm32/src/mach/testarm/testarm.c	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -123,5 +123,5 @@
 	sysinfo_set_item_val("kbd", NULL, true);
 	sysinfo_set_item_val("kbd.inr", NULL, GXEMUL_KBD_IRQ);
-	sysinfo_set_item_val("kbd.address.virtual", NULL, (unative_t) gxemul_kbd);
+	sysinfo_set_item_val("kbd.address.virtual", NULL, (sysarg_t) gxemul_kbd);
 #endif
 }
Index: kernel/arch/ia32/include/asm.h
===================================================================
--- kernel/arch/ia32/include/asm.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/ia32/include/asm.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -64,7 +64,7 @@
 }
 
-#define GEN_READ_REG(reg) NO_TRACE static inline unative_t read_ ##reg (void) \
+#define GEN_READ_REG(reg) NO_TRACE static inline sysarg_t read_ ##reg (void) \
 	{ \
-		unative_t res; \
+		sysarg_t res; \
 		asm volatile ( \
 			"movl %%" #reg ", %[res]" \
@@ -74,5 +74,5 @@
 	}
 
-#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (unative_t regn) \
+#define GEN_WRITE_REG(reg) NO_TRACE static inline void write_ ##reg (sysarg_t regn) \
 	{ \
 		asm volatile ( \
@@ -366,5 +366,5 @@
 	asm volatile (
 		"invlpg %[addr]\n"
-		:: [addr] "m" (*(unative_t *) addr)
+		:: [addr] "m" (*(sysarg_t *) addr)
 	);
 }
Index: kernel/arch/ia32/include/proc/thread.h
===================================================================
--- kernel/arch/ia32/include/proc/thread.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/ia32/include/proc/thread.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -39,5 +39,5 @@
 
 typedef struct {
-	unative_t tls;
+	sysarg_t tls;
 } thread_arch_t;
 
Index: kernel/arch/ia32/include/types.h
===================================================================
--- kernel/arch/ia32/include/types.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/ia32/include/types.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -43,5 +43,5 @@
 typedef uint32_t ipl_t;
 
-typedef uint32_t unative_t;
+typedef uint32_t sysarg_t;
 typedef int32_t native_t;
 typedef uint32_t atomic_count_t;
@@ -54,6 +54,6 @@
 
 #define PRIdn  PRId32  /**< Format for native_t. */
-#define PRIun  PRIu32  /**< Format for unative_t. */
-#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
+#define PRIun  PRIu32  /**< Format for sysarg_t. */
+#define PRIxn  PRIx32  /**< Format for hexadecimal sysarg_t. */
 #define PRIua  PRIu32  /**< Format for atomic_count_t. */
 
Index: kernel/arch/ia32/src/ia32.c
===================================================================
--- kernel/arch/ia32/src/ia32.c	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/ia32/src/ia32.c	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -211,5 +211,5 @@
  * selector, and the descriptor->base is the correct address.
  */
-unative_t sys_tls_set(unative_t addr)
+sysarg_t sys_tls_set(sysarg_t addr)
 {
 	THREAD->arch.tls = addr;
Index: kernel/arch/ia64/include/bootinfo.h
===================================================================
--- kernel/arch/ia64/include/bootinfo.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/ia64/include/bootinfo.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -62,5 +62,5 @@
 	unsigned int memmap_items;
 	
-	unative_t *sapic;
+	sysarg_t *sapic;
 	unsigned long sys_freq;
 	unsigned long freq_scale;
Index: kernel/arch/ia64/include/types.h
===================================================================
--- kernel/arch/ia64/include/types.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/ia64/include/types.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -43,11 +43,11 @@
 typedef uint64_t ipl_t;
 
-typedef uint64_t unative_t;
+typedef uint64_t sysarg_t;
 typedef int64_t native_t;
 typedef uint64_t atomic_count_t;
 
 typedef struct {
-	unative_t fnc;
-	unative_t gp;
+	sysarg_t fnc;
+	sysarg_t gp;
 } __attribute__((may_alias)) fncptr_t;
 
@@ -56,6 +56,6 @@
 
 #define PRIdn  PRId64  /**< Format for native_t. */
-#define PRIun  PRIu64  /**< Format for unative_t. */
-#define PRIxn  PRIx64  /**< Format for hexadecimal unative_t. */
+#define PRIun  PRIu64  /**< Format for sysarg_t. */
+#define PRIxn  PRIx64  /**< Format for hexadecimal sysarg_t. */
 #define PRIua  PRIu64  /**< Format for atomic_count_t. */
 
Index: kernel/arch/ia64/src/ia64.c
===================================================================
--- kernel/arch/ia64/src/ia64.c	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/ia64/src/ia64.c	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -104,5 +104,5 @@
 static void iosapic_init(void)
 {
-	uint64_t IOSAPIC = PA2KA((unative_t)(iosapic_base)) | FW_OFFSET;
+	uint64_t IOSAPIC = PA2KA((sysarg_t)(iosapic_base)) | FW_OFFSET;
 	int i;
 	
@@ -251,5 +251,5 @@
  * We use r13 (a.k.a. tp) for this purpose.
  */
-unative_t sys_tls_set(unative_t addr)
+sysarg_t sys_tls_set(sysarg_t addr)
 {
 	return 0;
@@ -274,6 +274,6 @@
 void *arch_construct_function(fncptr_t *fptr, void *addr, void *caller)
 {
-	fptr->fnc = (unative_t) addr;
-	fptr->gp = ((unative_t *) caller)[1];
+	fptr->fnc = (sysarg_t) addr;
+	fptr->gp = ((sysarg_t *) caller)[1];
 	
 	return (void *) fptr;
Index: kernel/arch/mips32/include/debugger.h
===================================================================
--- kernel/arch/mips32/include/debugger.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/mips32/include/debugger.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -58,8 +58,8 @@
 
 typedef struct  {
-	uintptr_t address;          /**< Breakpoint address */
-	unative_t instruction;      /**< Original instruction */
-	unative_t nextinstruction;  /**< Original instruction following break */
-	unsigned int flags;         /**< Flags regarding breakpoint */
+	uintptr_t address;         /**< Breakpoint address */
+	sysarg_t instruction;      /**< Original instruction */
+	sysarg_t nextinstruction;  /**< Original instruction following break */
+	unsigned int flags;        /**< Flags regarding breakpoint */
 	size_t counter;
 	void (*bkfunc)(void *, istate_t *);
@@ -68,5 +68,5 @@
 extern bpinfo_t breakpoints[BKPOINTS_MAX];
 
-extern bool is_jump(unative_t);
+extern bool is_jump(sysarg_t);
 
 extern void debugger_init(void);
Index: kernel/arch/mips32/include/fpu_context.h
===================================================================
--- kernel/arch/mips32/include/fpu_context.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/mips32/include/fpu_context.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -38,9 +38,9 @@
 #include <typedefs.h>
 
-#define FPU_CONTEXT_ALIGN    sizeof(unative_t)
+#define FPU_CONTEXT_ALIGN    sizeof(sysarg_t)
 
 typedef struct {
-	unative_t dregs[32];
-	unative_t cregs[32];
+	sysarg_t dregs[32];
+	sysarg_t cregs[32];
 } fpu_context_t;
 
Index: kernel/arch/mips32/include/types.h
===================================================================
--- kernel/arch/mips32/include/types.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/mips32/include/types.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -43,5 +43,5 @@
 typedef uint32_t ipl_t;
 
-typedef uint32_t unative_t;
+typedef uint32_t sysarg_t;
 typedef int32_t native_t;
 typedef uint32_t atomic_count_t;
@@ -54,6 +54,6 @@
 
 #define PRIdn  PRId32  /**< Format for native_t. */
-#define PRIun  PRIu32  /**< Format for unative_t. */
-#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
+#define PRIun  PRIu32  /**< Format for sysarg_t. */
+#define PRIxn  PRIx32  /**< Format for hexadecimal sysarg_t. */
 #define PRIua  PRIu32  /**< Format for atomic_count_t. */
 
Index: kernel/arch/mips32/src/debugger.c
===================================================================
--- kernel/arch/mips32/src/debugger.c	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/mips32/src/debugger.c	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -134,5 +134,5 @@
  *
  */
-bool is_jump(unative_t instr)
+bool is_jump(sysarg_t instr)
 {
 	unsigned int i;
@@ -166,6 +166,6 @@
 			return 0;
 		} else if ((breakpoints[i].address == (uintptr_t) argv->intval +
-		    sizeof(unative_t)) || (breakpoints[i].address ==
-		    (uintptr_t) argv->intval - sizeof(unative_t))) {
+		    sizeof(sysarg_t)) || (breakpoints[i].address ==
+		    (uintptr_t) argv->intval - sizeof(sysarg_t))) {
 			printf("Adjacent breakpoints not supported, conflict "
 			    "with %d.\n", i);
@@ -194,6 +194,6 @@
 	
 	cur->address = (uintptr_t) argv->intval;
-	cur->instruction = ((unative_t *) cur->address)[0];
-	cur->nextinstruction = ((unative_t *) cur->address)[1];
+	cur->instruction = ((sysarg_t *) cur->address)[0];
+	cur->nextinstruction = ((sysarg_t *) cur->address)[1];
 	if (argv == &add_argv) {
 		cur->flags = 0;
@@ -209,5 +209,5 @@
 	
 	/* Set breakpoint */
-	*((unative_t *) cur->address) = 0x0d;
+	*((sysarg_t *) cur->address) = 0x0d;
 	smc_coherence(cur->address);
 	
@@ -341,5 +341,5 @@
 		/* Reinst only breakpoint */
 		if ((breakpoints[i].flags & BKPOINT_REINST) &&
-		    (fireaddr == breakpoints[i].address + sizeof(unative_t))) {
+		    (fireaddr == breakpoints[i].address + sizeof(sysarg_t))) {
 			cur = &breakpoints[i];
 			break;
Index: kernel/arch/mips32/src/mips32.c
===================================================================
--- kernel/arch/mips32/src/mips32.c	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/mips32/src/mips32.c	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -233,5 +233,5 @@
  * possible to have it separately in the future.
  */
-unative_t sys_tls_set(unative_t addr)
+sysarg_t sys_tls_set(sysarg_t addr)
 {
 	return 0;
Index: kernel/arch/ppc32/include/exception.h
===================================================================
--- kernel/arch/ppc32/include/exception.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/ppc32/include/exception.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -98,10 +98,10 @@
 }
 
-NO_TRACE static inline unative_t istate_get_pc(istate_t *istate)
+NO_TRACE static inline sysarg_t istate_get_pc(istate_t *istate)
 {
 	return istate->pc;
 }
 
-NO_TRACE static inline unative_t istate_get_fp(istate_t *istate)
+NO_TRACE static inline sysarg_t istate_get_fp(istate_t *istate)
 {
 	return istate->sp;
Index: kernel/arch/ppc32/include/types.h
===================================================================
--- kernel/arch/ppc32/include/types.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/ppc32/include/types.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -43,5 +43,5 @@
 typedef uint32_t ipl_t;
 
-typedef uint32_t unative_t;
+typedef uint32_t sysarg_t;
 typedef int32_t native_t;
 typedef uint32_t atomic_count_t;
@@ -54,6 +54,6 @@
 
 #define PRIdn  PRId32  /**< Format for native_t. */
-#define PRIun  PRIu32  /**< Format for unative_t. */
-#define PRIxn  PRIx32  /**< Format for hexadecimal unative_t. */
+#define PRIun  PRIu32  /**< Format for sysarg_t. */
+#define PRIxn  PRIx32  /**< Format for hexadecimal sysarg_t. */
 #define PRIua  PRIu32  /**< Format for atomic_count_t. */
 
Index: kernel/arch/sparc64/include/mm/sun4u/tlb.h
===================================================================
--- kernel/arch/sparc64/include/mm/sun4u/tlb.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/sparc64/include/mm/sun4u/tlb.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -678,5 +678,5 @@
 }
 
-extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
+extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *);
 extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
 extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
Index: kernel/arch/sparc64/include/mm/sun4v/tlb.h
===================================================================
--- kernel/arch/sparc64/include/mm/sun4v/tlb.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/sparc64/include/mm/sun4v/tlb.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -141,7 +141,7 @@
 }
 
-extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
-extern void fast_data_access_mmu_miss(unative_t, istate_t *);
-extern void fast_data_access_protection(unative_t, istate_t *);
+extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *);
+extern void fast_data_access_mmu_miss(sysarg_t, istate_t *);
+extern void fast_data_access_protection(sysarg_t, istate_t *);
 
 extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
Index: kernel/arch/sparc64/include/types.h
===================================================================
--- kernel/arch/sparc64/include/types.h	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/sparc64/include/types.h	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -43,5 +43,5 @@
 typedef uint64_t ipl_t;
 
-typedef uint64_t unative_t;
+typedef uint64_t sysarg_t;
 typedef int64_t native_t;
 typedef uint64_t atomic_count_t;
@@ -56,6 +56,6 @@
 
 #define PRIdn  PRId64  /**< Format for native_t. */
-#define PRIun  PRIu64  /**< Format for unative_t. */
-#define PRIxn  PRIx64  /**< Format for hexadecimal unative_t. */
+#define PRIun  PRIu64  /**< Format for sysarg_t. */
+#define PRIxn  PRIx64  /**< Format for hexadecimal sysarg_t. */
 #define PRIua  PRIu64  /**< Format for atomic_count_t. */
 
Index: kernel/arch/sparc64/src/mm/sun4u/tlb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4u/tlb.c	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/sparc64/src/mm/sun4u/tlb.c	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -200,5 +200,5 @@
 
 /** ITLB miss handler. */
-void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
+void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate)
 {
 	uintptr_t page_16k = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
Index: kernel/arch/sparc64/src/mm/sun4v/tlb.c
===================================================================
--- kernel/arch/sparc64/src/mm/sun4v/tlb.c	(revision 41a7f624830c173ff6e5ed22c0abc99dbc08751a)
+++ kernel/arch/sparc64/src/mm/sun4v/tlb.c	(revision 0bff73aed85c65c908499a83db3b7a8e89c7b3fc)
@@ -213,5 +213,5 @@
 
 /** ITLB miss handler. */
-void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
+void fast_instruction_access_mmu_miss(sysarg_t unused, istate_t *istate)
 {
 	uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);