Changeset 0b9ac3c in mainline for kernel/arch/sparc64/include/trap


Ignore:
Timestamp:
2010-02-23T19:03:28Z (16 years ago)
Author:
Jiri Svoboda <jiri@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
c62d2e1
Parents:
1ccafee (diff), 5e50394 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes.

Location:
kernel/arch/sparc64/include/trap
Files:
6 added
5 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/trap/exception.h

    r1ccafee r0b9ac3c  
    3838
    3939#define TT_INSTRUCTION_ACCESS_EXCEPTION         0x08
     40#define TT_INSTRUCTION_ACCESS_MMU_MISS          0x09
    4041#define TT_INSTRUCTION_ACCESS_ERROR             0x0a
     42#define TT_IAE_UNAUTH_ACCESS                    0x0b
     43#define TT_IAE_NFO_PAGE                         0x0c
    4144#define TT_ILLEGAL_INSTRUCTION                  0x10
    4245#define TT_PRIVILEGED_OPCODE                    0x11
    4346#define TT_UNIMPLEMENTED_LDD                    0x12
    4447#define TT_UNIMPLEMENTED_STD                    0x13
     48#define TT_DAE_INVALID_ASI                      0x14
     49#define TT_DAE_PRIVILEGE_VIOLATION              0x15
     50#define TT_DAE_NC_PAGE                          0x16
     51#define TT_DAE_NFO_PAGE                         0x17
    4552#define TT_FP_DISABLED                          0x20
    4653#define TT_FP_EXCEPTION_IEEE_754                0x21
    … …  
    4956#define TT_DIVISION_BY_ZERO                     0x28
    5057#define TT_DATA_ACCESS_EXCEPTION                0x30
     58#define TT_DATA_ACCESS_MMU_MISS                 0x31
    5159#define TT_DATA_ACCESS_ERROR                    0x32
    5260#define TT_MEM_ADDRESS_NOT_ALIGNED              0x34

  • kernel/arch/sparc64/include/trap/interrupt.h

    r1ccafee r0b9ac3c  
    3232/**
    3333 * @file
    34  * @brief This file contains interrupt vector trap handler.
     34 * @brief This file contains level N interrupt and inter-processor interrupt
     35 * trap handler.
    3536 */
    36 
    37 #ifndef KERN_sparc64_TRAP_INTERRUPT_H_
    38 #define KERN_sparc64_TRAP_INTERRUPT_H_
    39 
    40 #include <arch/trap/trap_table.h>
    41 #include <arch/stack.h>
    42 
    43 /* IMAP register bits */
    44 #define IGN_MASK        0x7c0
    45 #define INO_MASK        0x1f
    46 #define IMAP_V_MASK     (1ULL << 31)
    47 
    48 #define IGN_SHIFT       6
    49 
    50 
    51 /* Interrupt ASI registers. */
    52 #define ASI_INTR_W                      0x77
    53 #define ASI_INTR_DISPATCH_STATUS        0x48
    54 #define ASI_INTR_R                      0x7f
    55 #define ASI_INTR_RECEIVE                0x49
    56 
    57 /* VA's used with ASI_INTR_W register. */
    58 #if defined (US)
    59 #define ASI_UDB_INTR_W_DATA_0   0x40
    60 #define ASI_UDB_INTR_W_DATA_1   0x50
    61 #define ASI_UDB_INTR_W_DATA_2   0x60
    62 #elif defined (US3)
    63 #define VA_INTR_W_DATA_0        0x40
    64 #define VA_INTR_W_DATA_1        0x48
    65 #define VA_INTR_W_DATA_2        0x50
    66 #define VA_INTR_W_DATA_3        0x58
    67 #define VA_INTR_W_DATA_4        0x60
    68 #define VA_INTR_W_DATA_5        0x68
    69 #define VA_INTR_W_DATA_6        0x80
    70 #define VA_INTR_W_DATA_7        0x88
    71 #endif
    72 #define VA_INTR_W_DISPATCH      0x70
    73 
    74 /* VA's used with ASI_INTR_R register. */
    75 #if defined(US)
    76 #define ASI_UDB_INTR_R_DATA_0   0x40
    77 #define ASI_UDB_INTR_R_DATA_1   0x50
    78 #define ASI_UDB_INTR_R_DATA_2   0x60
    79 #elif defined (US3)
    80 #define VA_INTR_R_DATA_0        0x40
    81 #define VA_INTR_R_DATA_1        0x48
    82 #define VA_INTR_R_DATA_2        0x50
    83 #define VA_INTR_R_DATA_3        0x58
    84 #define VA_INTR_R_DATA_4        0x60
    85 #define VA_INTR_R_DATA_5        0x68
    86 #define VA_INTR_R_DATA_6        0x80
    87 #define VA_INTR_R_DATA_7        0x88
    88 #endif
    89 
    90 /* Shifts in the Interrupt Vector Dispatch virtual address. */
    91 #define INTR_VEC_DISPATCH_MID_SHIFT     14
    92 
    93 /* Bits in the Interrupt Dispatch Status register. */
    94 #define INTR_DISPATCH_STATUS_NACK       0x2
    95 #define INTR_DISPATCH_STATUS_BUSY       0x1
     37#ifndef KERN_sparc64_INTERRUPT_TRAP_H_
     38#define KERN_sparc64_INTERRUPT_TRAP_H_
    9639
    9740#define TT_INTERRUPT_LEVEL_1                    0x41
    … …  
    11154#define TT_INTERRUPT_LEVEL_15                   0x4f
    11255
    113 #define TT_INTERRUPT_VECTOR_TRAP                0x60
     56#define INTERRUPT_LEVEL_N_HANDLER_SIZE          TRAP_TABLE_ENTRY_SIZE
    11457
    115 #define INTERRUPT_LEVEL_N_HANDLER_SIZE          TRAP_TABLE_ENTRY_SIZE
    116 #define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE      TRAP_TABLE_ENTRY_SIZE
     58/* IMAP register bits */
     59#define IGN_MASK        0x7c0
     60#define INO_MASK        0x1f
     61#define IMAP_V_MASK     (1ULL << 31)
     62
     63#define IGN_SHIFT       6
     64
    11765
    11866#ifdef __ASM__
    … …  
    12169        PREEMPTIBLE_HANDLER exc_dispatch
    12270.endm
    123 
    124 .macro INTERRUPT_VECTOR_TRAP_HANDLER
    125         PREEMPTIBLE_HANDLER interrupt
    126 .endm
    127 #endif /* __ASM__ */
     71#endif
    12872
    12973#ifndef __ASM__
    … …  
    13478#endif /* !def __ASM__ */
    13579
     80
     81#if defined (SUN4U)
     82#include <arch/trap/sun4u/interrupt.h>
     83#elif defined (SUN4V)
     84#include <arch/trap/sun4v/interrupt.h>
     85#endif
     86
    13687#endif
    13788

  • kernel/arch/sparc64/include/trap/mmu.h

    r1ccafee r0b9ac3c  
    3838#define KERN_sparc64_MMU_TRAP_H_
    3939
    40 #include <arch/stack.h>
    41 #include <arch/regdef.h>
    42 #include <arch/mm/tlb.h>
    43 #include <arch/mm/mmu.h>
    44 #include <arch/mm/tte.h>
    45 #include <arch/trap/regwin.h>
    46 
    47 #ifdef CONFIG_TSB
    48 #include <arch/mm/tsb.h>
     40#if defined (SUN4U)
     41#include <arch/trap/sun4u/mmu.h>
     42#elif defined (SUN4V)
     43#include <arch/trap/sun4v/mmu.h>
    4944#endif
    50 
    51 #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS     0x64
    52 #define TT_FAST_DATA_ACCESS_MMU_MISS            0x68
    53 #define TT_FAST_DATA_ACCESS_PROTECTION          0x6c
    54 
    55 #define FAST_MMU_HANDLER_SIZE                   128
    56 
    57 #ifdef __ASM__
    58 
    59 .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
    60         /*
    61          * First, try to refill TLB from TSB.
    62          */
    63 #ifdef CONFIG_TSB
    64         ldxa [%g0] ASI_IMMU, %g1                        ! read TSB Tag Target Register
    65         ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2        ! read TSB 8K Pointer
    66         ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4            ! 16-byte atomic load into %g4 and %g5
    67         cmp %g1, %g4                                    ! is this the entry we are looking for?
    68         bne,pn %xcc, 0f
    69         nop
    70         stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG            ! copy mapping from ITSB to ITLB
    71         retry
    72 #endif
    73 
    74 0:
    75         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    76         PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
    77 .endm
    78 
    79 .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
    80         /*
    81          * First, try to refill TLB from TSB.
    82          */
    83 
    84 #ifdef CONFIG_TSB
    85         ldxa [%g0] ASI_DMMU, %g1                        ! read TSB Tag Target Register
    86         srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2     ! is this a kernel miss?
    87         brz,pn %g2, 0f
    88         ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3        ! read TSB 8K Pointer
    89         ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4            ! 16-byte atomic load into %g4 and %g5
    90         cmp %g1, %g4                                    ! is this the entry we are looking for?
    91         bne,pn %xcc, 0f
    92         nop
    93         stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG            ! copy mapping from DTSB to DTLB
    94         retry
    95 #endif
    96 
    97         /*
    98          * Second, test if it is the portion of the kernel address space
    99          * which is faulting. If that is the case, immediately create
    100          * identity mapping for that page in DTLB. VPN 0 is excluded from
    101          * this treatment.
    102          *
    103          * Note that branch-delay slots are used in order to save space.
    104          */
    105 0:
    106         sethi %hi(fast_data_access_mmu_miss_data_hi), %g7
    107         wr %g0, ASI_DMMU, %asi
    108         ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1             ! read the faulting Context and VPN
    109         set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
    110         andcc %g1, %g2, %g3                             ! get Context
    111         bnz %xcc, 0f                                    ! Context is non-zero
    112         andncc %g1, %g2, %g3                            ! get page address into %g3
    113         bz  %xcc, 0f                                    ! page address is zero
    114         ldx [%g7 + %lo(end_of_identity)], %g4
    115         cmp %g3, %g4
    116         bgeu %xcc, 0f
    117 
    118         ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2
    119         add %g3, %g2, %g2
    120         stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG            ! identity map the kernel page
    121         retry
    122 
    123         /*
    124          * Third, catch and handle special cases when the trap is caused by
    125          * the userspace register window spill or fill handler. In case
    126          * one of these two traps caused this trap, we just lower the trap
    127          * level and service the DTLB miss. In the end, we restart
    128          * the offending SAVE or RESTORE.
    129          */
    130 0:
    131 .if (\tl > 0)
    132         wrpr %g0, 1, %tl
    133 .endif
    134 
    135         /*
    136          * Switch from the MM globals.
    137          */
    138         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    139 
    140         /*
    141          * Read the Tag Access register for the higher-level handler.
    142          * This is necessary to survive nested DTLB misses.
    143          */     
    144         ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2
    145 
    146         /*
    147          * g2 will be passed as an argument to fast_data_access_mmu_miss().
    148          */
    149         PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
    150 .endm
    151 
    152 .macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
    153         /*
    154          * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
    155          */
    156 
    157 .if (\tl > 0)
    158         wrpr %g0, 1, %tl
    159 .endif
    160 
    161         /*
    162          * Switch from the MM globals.
    163          */
    164         wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
    165 
    166         /*
    167          * Read the Tag Access register for the higher-level handler.
    168          * This is necessary to survive nested DTLB misses.
    169          */     
    170         mov VA_DMMU_TAG_ACCESS, %g2
    171         ldxa [%g2] ASI_DMMU, %g2
    172 
    173         /*
    174          * g2 will be passed as an argument to fast_data_access_mmu_miss().
    175          */
    176         PREEMPTIBLE_HANDLER fast_data_access_protection
    177 .endm
    178 
    179 #endif /* __ASM__ */
    18045
    18146#endif

  • kernel/arch/sparc64/include/trap/regwin.h

    r1ccafee r0b9ac3c  
    131131
    132132/*
    133  * Macro used to spill userspace window to userspace window buffer.
    134  * It can be either triggered from preemptible_handler doing SAVE
    135  * at (TL=1) or from normal kernel code doing SAVE when OTHERWIN>0
    136  * at (TL=0).
    137  */
    138 .macro SPILL_TO_USPACE_WINDOW_BUFFER
    139         stx %l0, [%g7 + L0_OFFSET]     
    140         stx %l1, [%g7 + L1_OFFSET]
    141         stx %l2, [%g7 + L2_OFFSET]
    142         stx %l3, [%g7 + L3_OFFSET]
    143         stx %l4, [%g7 + L4_OFFSET]
    144         stx %l5, [%g7 + L5_OFFSET]
    145         stx %l6, [%g7 + L6_OFFSET]
    146         stx %l7, [%g7 + L7_OFFSET]
    147         stx %i0, [%g7 + I0_OFFSET]
    148         stx %i1, [%g7 + I1_OFFSET]
    149         stx %i2, [%g7 + I2_OFFSET]
    150         stx %i3, [%g7 + I3_OFFSET]
    151         stx %i4, [%g7 + I4_OFFSET]
    152         stx %i5, [%g7 + I5_OFFSET]
    153         stx %i6, [%g7 + I6_OFFSET]
    154         stx %i7, [%g7 + I7_OFFSET]
    155         add %g7, STACK_WINDOW_SAVE_AREA_SIZE, %g7
    156         saved
    157         retry
    158 .endm
    159 
    160 
    161 /*
    162133 * Macro used by the nucleus and the primary context 0 during normal fills.
    163134 */
    … …  
    232203#endif /* __ASM__ */
    233204
     205#if defined (SUN4U)
     206#include <arch/trap/sun4u/regwin.h>
     207#elif defined (SUN4V)
     208#include <arch/trap/sun4v/regwin.h>
    234209#endif
    235210
     211#endif
     212
    236213/** @}
    237214 */

  • kernel/arch/sparc64/include/trap/trap_table.h

    r1ccafee r0b9ac3c  
    101101.macro PREEMPTIBLE_HANDLER f
    102102        sethi %hi(\f), %g1
    103         ba %xcc, preemptible_handler
     103        b preemptible_handler
    104104        or %g1, %lo(\f), %g1
    105105.endm
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