Index: kernel/arch/arm32/include/arch/barrier.h
===================================================================
--- kernel/arch/arm32/include/arch/barrier.h	(revision 05882233d8ca97c6879ac5c42456c344c8569d89)
+++ kernel/arch/arm32/include/arch/barrier.h	(revision 0abc2aea144199fee5fb2b5b1ffcf9f0ac6528ce)
@@ -117,26 +117,21 @@
  */
 
-#if defined PROCESSOR_ARCH_armv7_a | defined PROCESSOR_ARCH_armv6 | defined KERNEL
-//TODO might be PL1 only on armv5-
-#define smc_coherence(a) \
-do { \
-	dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \
-	write_barrier();               /* Wait for completion */\
-	icache_invalidate();\
-	inst_barrier();                /* Wait for Inst refetch */\
-} while (0)
+#ifdef KERNEL
+
 /*
  * @note: Cache type register is not available in uspace. We would need
  * to export the cache line value, or use syscall for uspace smc_coherence
  */
-#define smc_coherence_block(a, l) \
+#define smc_coherence(a, l) \
 do { \
 	for (uintptr_t addr = (uintptr_t) a; addr < (uintptr_t) a + l; \
 	    addr += CP15_C7_MVA_ALIGN) \
-		smc_coherence(addr); \
+		dcache_clean_mva_pou(ALIGN_DOWN((uintptr_t) a, CP15_C7_MVA_ALIGN)); \
+	write_barrier();               /* Wait for completion */\
+	icache_invalidate();\
+	write_barrier();\
+	inst_barrier();                /* Wait for Inst refetch */\
 } while (0)
-#else
-#define smc_coherence(a)
-#define smc_coherence_block(a, l)
+
 #endif
 
Index: kernel/arch/arm32/src/exception.c
===================================================================
--- kernel/arch/arm32/src/exception.c	(revision 05882233d8ca97c6879ac5c42456c344c8569d89)
+++ kernel/arch/arm32/src/exception.c	(revision 0abc2aea144199fee5fb2b5b1ffcf9f0ac6528ce)
@@ -75,5 +75,5 @@
 	/* Make it LDR instruction and store at exception vector */
 	*vector = handler_address_ptr | LDR_OPCODE;
-	smc_coherence(vector);
+	smc_coherence(vector, 4);
 
 	/* Store handler's address */