Changeset 0ab362c in mainline for kernel/arch/arm32/src/cpu/cpu.c

Timestamp:

2012-11-22T14:36:04Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e32720ff

Parents:

1f7753a (diff), 0f2c80a (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge support for BeagleBoard-xM (armv7).

Most of the changes outside arm arch are pio_* stuff (addition of pio_trace capability, header consolidation)

File:

• kernel/arch/arm32/src/cpu/cpu.c (modified) (3 diffs)

kernel/arch/arm32/src/cpu/cpu.c

@@ -44 +44 @@
 /** Implementators (vendor) names */
 static const char *imp_data[] = {
-        "?",                                    /* IMP_DATA_START_OFFSET */
-        "ARM Ltd",                              /* 0x41 */
-        "",                                     /* 0x42 */
-        "",                                     /* 0x43 */
-        "Digital Equipment Corporation",        /* 0x44 */
-        "", "", "", "", "", "", "", "", "", "", /* 0x45 - 0x4e */
-        "", "", "", "", "", "", "", "", "", "", /* 0x4f - 0x58 */
-        "", "", "", "", "", "", "", "", "", "", /* 0x59 - 0x62 */
-        "", "", "", "", "", "",                 /* 0x63 - 0x68 */
-        "Intel Corporation"                     /* 0x69 */
+        "?",                                     /* IMP_DATA_START_OFFSET */
+        "ARM Limited",                           /* 0x41 */
+        "", "",                                  /* 0x42 - 0x43 */
+        "Digital Equipment Corporation",         /* 0x44 */
+        "", "", "", "", "", "", "", "",          /* 0x45 - 0x4c */
+        "Motorola, Freescale Semicondutor Inc.", /* 0x4d */
+        "", "", "",                              /* 0x4e - 0x50 */
+        "Qualcomm Inc.",                         /* 0x51 */
+        "", "", "", "",                          /* 0x52 - 0x55 */
+        "Marvell Semiconductor",                 /* 0x56 */
+        "", "", "", "", "", "", "", "", "", "",  /* 0x57 - 0x60 */
+        "", "", "", "", "", "", "", "",          /* 0x61 - 0x68 */
+        "Intel Corporation"                      /* 0x69 */
 };
 
@@ -94 +97 @@
 }
 
-/** Does nothing on ARM. */
+/** Enables unaligned access and caching for armv6+ */
 void cpu_arch_init(void)
 {
+#if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6)
+        uint32_t control_reg = 0;
+        asm volatile (
+                "mrc p15, 0, %[control_reg], c1, c0"
+                : [control_reg] "=r" (control_reg)
+        );
+        
+        /* Turn off tex remap, RAZ ignores writes prior to armv7 */
+        control_reg &= ~CP15_R1_TEX_REMAP_EN;
+        /* Turn off accessed flag, RAZ ignores writes prior to armv7 */
+        control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
+        /* Enable unaligned access, RAZ ignores writes prior to armv6
+         * switchable on armv6, RAO ignores writes on armv7,
+         * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
+         * L.3.1 (p. 2456) */
+        control_reg |= CP15_R1_UNALIGNED_EN;
+        /* Disable alignment checks, this turns unaligned access to undefined,
+         * unless U bit is set. */
+        control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
+        /* Enable caching, On arm prior to armv7 there is only one level
+         * of caches. Data cache is coherent.
+         * "This means that the behavior of accesses from the same observer to
+         * different VAs, that are translated to the same PA
+         * with the same memory attributes, is fully coherent."
+         *    ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
+         *    B3.11.1 (p. 1383)
+         * ICache coherency is elaborate on in barrier.h.
+         * We are safe to turn these on.
+         */
+        control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;
+        
+        asm volatile (
+                "mcr p15, 0, %[control_reg], c1, c0"
+                :: [control_reg] "r" (control_reg)
+        );
+#endif
 }
 
 /** Retrieves processor identification and stores it to #CPU.arch */
-void cpu_identify(void) 
+void cpu_identify(void)
 {
         arch_cpu_identify(&CPU->arch);
@@ -112 +151 @@
         cpu_arch_t * cpu_arch = &m->arch;
 
-        if ((cpu_arch->imp_num) > 0 &&
-            (cpu_arch->imp_num < (imp_data_length + IMP_DATA_START_OFFSET))) {
+        const unsigned imp_offset = cpu_arch->imp_num - IMP_DATA_START_OFFSET;
+
+        if (imp_offset < imp_data_length) {
                 vendor = imp_data[cpu_arch->imp_num - IMP_DATA_START_OFFSET];
         }
 
-        if ((cpu_arch->arch_num) > 0 &&
-            (cpu_arch->arch_num < arch_data_length)) {
+        // TODO CPUs with arch_num == 0xf use CPUID scheme for identification
+        if (cpu_arch->arch_num < arch_data_length) {
                 architecture = arch_data[cpu_arch->arch_num];
         }