Index: arch/amd64/include/mm/page.h =================================================================== --- arch/amd64/include/mm/page.h (revision d0a0f125da5e6e33ad6557453e99903f9057c78b) +++ arch/amd64/include/mm/page.h (revision 0882a9a17a26cf3ed328548c95dfadf23263a59f) @@ -76,4 +76,5 @@ #ifndef __ASM__ +/** Page Table Entry. */ struct page_specifier { unsigned present : 1; @@ -86,5 +87,6 @@ unsigned unused: 1; unsigned global : 1; - unsigned avl : 3; + unsigned soft_valid : 1; /**< Valid content even if present bit is cleared. */ + unsigned avl : 2; unsigned addr_12_31 : 30; unsigned addr_32_51 : 21; @@ -125,4 +127,9 @@ p->no_execute = (flags & PAGE_EXEC) == 0; p->global = (flags & PAGE_GLOBAL) != 0; + + /* + * Ensure that there is at least one bit set even if the present bit is cleared. + */ + p->soft_valid = 1; } Index: arch/ia32/include/mm/page.h =================================================================== --- arch/ia32/include/mm/page.h (revision d0a0f125da5e6e33ad6557453e99903f9057c78b) +++ arch/ia32/include/mm/page.h (revision 0882a9a17a26cf3ed328548c95dfadf23263a59f) @@ -78,4 +78,5 @@ #include +/** Page Table Entry. */ struct page_specifier { unsigned present : 1; @@ -88,5 +89,6 @@ unsigned pat : 1; unsigned global : 1; - unsigned avl : 3; + unsigned soft_valid : 1; /**< Valid content even if the present bit is not set. */ + unsigned avl : 2; unsigned frame_address : 20; } __attribute__ ((packed)); @@ -116,4 +118,9 @@ p->writeable = (flags & PAGE_WRITE) != 0; p->global = (flags & PAGE_GLOBAL) != 0; + + /* + * Ensure that there is at least one bit set even if the present bit is cleared. + */ + p->soft_valid = true; } Index: arch/mips32/include/mm/page.h =================================================================== --- arch/mips32/include/mm/page.h (revision d0a0f125da5e6e33ad6557453e99903f9057c78b) +++ arch/mips32/include/mm/page.h (revision 0882a9a17a26cf3ed328548c95dfadf23263a59f) @@ -49,4 +49,7 @@ * - Offset is 14 bits => pages are 16K long * - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long + * - PTE's replace EntryLo v (valid) bit with p (present) bit + * - PTE's use only one bit to distinguish between cacheable and uncacheable mappings + * - PTE's define soft_valid field to ensure there is at least one 1 bit even if the p bit is cleared * - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed) * - PTL0 has 64 entries (6 bits) @@ -63,13 +66,13 @@ #define SET_PTL0_ADDRESS_ARCH(ptl0) -#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].lo.pfn<<12) +#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].pfn<<12) #define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1) #define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2) -#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *)(ptl3))[(i)].lo.pfn<<12) +#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *)(ptl3))[(i)].pfn<<12) -#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].lo.pfn = (a)>>12) +#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].pfn = (a)>>12) #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) -#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].lo.pfn = (a)>>12) +#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].pfn = (a)>>12) #define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i)) @@ -95,11 +98,11 @@ return ( - ((p->lo.c>PAGE_UNCACHED)<lo.v)<cacheable<p)<w)<lo.g<g<lo.c = (flags & PAGE_CACHEABLE) != 0 ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED; - p->lo.v = !(flags & PAGE_NOT_PRESENT); - p->lo.g = (flags & PAGE_GLOBAL) != 0; + p->cacheable = (flags & PAGE_CACHEABLE) != 0; + p->p = !(flags & PAGE_NOT_PRESENT); + p->g = (flags & PAGE_GLOBAL) != 0; p->w = (flags & PAGE_WRITE) != 0; + + /* + * Ensure that valid entries have at least one bit set. + */ + p->soft_valid = 1; } Index: arch/mips32/include/mm/tlb.h =================================================================== --- arch/mips32/include/mm/tlb.h (revision d0a0f125da5e6e33ad6557453e99903f9057c78b) +++ arch/mips32/include/mm/tlb.h (revision 0882a9a17a26cf3ed328548c95dfadf23263a59f) @@ -64,11 +64,15 @@ }; -union pte { - entry_lo_t lo; - struct { - unsigned : 30; - unsigned w : 1; /* writable */ - unsigned a : 1; /* accessed */ - } __attribute__ ((packed)); +/** Page Table Entry. */ +struct pte { + unsigned g : 1; /**< Global bit. */ + unsigned p : 1; /**< Present bit. */ + unsigned d : 1; /**< Dirty bit. */ + unsigned cacheable : 1; /**< Cacheable bit. */ + unsigned : 1; /**< Unused. */ + unsigned soft_valid : 1; /**< Valid content even if not present. */ + unsigned pfn : 24; /**< Physical frame number. */ + unsigned w : 1; /**< Page writable bit. */ + unsigned a : 1; /**< Accessed bit. */ }; Index: arch/mips32/include/types.h =================================================================== --- arch/mips32/include/types.h (revision d0a0f125da5e6e33ad6557453e99903f9057c78b) +++ arch/mips32/include/types.h (revision 0882a9a17a26cf3ed328548c95dfadf23263a59f) @@ -50,5 +50,5 @@ typedef __u32 __native; -typedef union pte pte_t; +typedef struct pte pte_t; typedef __u32 pfn_t; Index: arch/mips32/src/mm/tlb.c =================================================================== --- arch/mips32/src/mm/tlb.c (revision d0a0f125da5e6e33ad6557453e99903f9057c78b) +++ arch/mips32/src/mm/tlb.c (revision 0882a9a17a26cf3ed328548c95dfadf23263a59f) @@ -46,5 +46,5 @@ static pte_t *find_mapping_and_check(__address badvaddr); -static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn); +static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn); static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr); @@ -105,5 +105,5 @@ prepare_entry_hi(&hi, AS->asid, badvaddr); - prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn); + prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); /* @@ -179,5 +179,5 @@ pte->a = 1; - prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->lo.d, pte->lo.c, pte->lo.pfn); + prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn); /* @@ -253,7 +253,7 @@ */ pte->a = 1; - pte->lo.d = 1; - - prepare_entry_lo(&lo, pte->lo.g, pte->lo.v, pte->w, pte->lo.c, pte->lo.pfn); + pte->d = 1; + + prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn); /* @@ -338,5 +338,5 @@ */ pte = page_mapping_find(AS, badvaddr); - if (pte && pte->lo.v) { + if (pte && pte->p) { /* * Mapping found in page tables. @@ -355,5 +355,5 @@ */ pte = page_mapping_find(AS, badvaddr); - ASSERT(pte && pte->lo.v); + ASSERT(pte && pte->p); return pte; } @@ -371,5 +371,5 @@ * Handler cannot succeed if the mapping is marked as invalid. */ - if (!pte->lo.v) { + if (!pte->p) { printf("Invalid mapping.\n"); return NULL; @@ -379,5 +379,5 @@ } -void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, int c, __address pfn) +void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn) { lo->value = 0; @@ -385,5 +385,5 @@ lo->v = v; lo->d = d; - lo->c = c; + lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED; lo->pfn = pfn; } Index: genarch/src/mm/asid_fifo.c =================================================================== --- genarch/src/mm/asid_fifo.c (revision d0a0f125da5e6e33ad6557453e99903f9057c78b) +++ genarch/src/mm/asid_fifo.c (revision 0882a9a17a26cf3ed328548c95dfadf23263a59f) @@ -35,4 +35,5 @@ #define FIFO_STATIC_LIMIT 1024 #define FIFO_STATIC (ASIDS_ALLOCABLE