Index: Makefile
===================================================================
--- Makefile	(revision 846848a632676ac86608fbe67cb2574e1b00cc5e)
+++ Makefile	(revision 07d78705131fd1e3b5ec9c46c4d0949018348976)
@@ -52,4 +52,6 @@
 endif
 
+CFLAGS += -DCONFIG_MIPS_FPU
+
 BUILDS := $(addsuffix .build,$(DIRS))
 CLEANS := $(addsuffix .clean,$(DIRS))
Index: libc/arch/mips32/Makefile.inc
===================================================================
--- libc/arch/mips32/Makefile.inc	(revision 846848a632676ac86608fbe67cb2574e1b00cc5e)
+++ libc/arch/mips32/Makefile.inc	(revision 07d78705131fd1e3b5ec9c46c4d0949018348976)
@@ -34,8 +34,14 @@
 CFLAGS += -mips3
 
+-include ../Makefile.config
+ifeq ($(CONFIG_MIPS_FPU),y)
+	CFLAGS += -DCONFIG_MIPS_FPU
+endif
+
 ARCH_SOURCES += arch/$(ARCH)/src/syscall.c \
 	arch/$(ARCH)/src/psthread.S \
 	arch/$(ARCH)/src/thread.c
 
+
 BFD_ARCH = mips
 BFD_NAME = elf32-little
Index: libc/arch/mips32/include/context_offset.h
===================================================================
--- libc/arch/mips32/include/context_offset.h	(revision 846848a632676ac86608fbe67cb2574e1b00cc5e)
+++ libc/arch/mips32/include/context_offset.h	(revision 07d78705131fd1e3b5ec9c46c4d0949018348976)
@@ -15,4 +15,16 @@
 #define OFFSET_TLS     0x30
 
+#define OFFSET_F20     0x34
+#define OFFSET_F21     0x38
+#define OFFSET_F22     0x3c
+#define OFFSET_F23     0x40
+#define OFFSET_F24     0x44
+#define OFFSET_F25     0x48
+#define OFFSET_F26     0x4c
+#define OFFSET_F27     0x50
+#define OFFSET_F28     0x54
+#define OFFSET_F29     0x58
+#define OFFSET_F30     0x5c
+
  /** @}
  */
Index: libc/arch/mips32/include/psthread.h
===================================================================
--- libc/arch/mips32/include/psthread.h	(revision 846848a632676ac86608fbe67cb2574e1b00cc5e)
+++ libc/arch/mips32/include/psthread.h	(revision 07d78705131fd1e3b5ec9c46c4d0949018348976)
@@ -70,4 +70,17 @@
 	uint32_t gp;
 	uint32_t tls; /* Thread local storage(=k1) */
+
+	uint32_t f20;
+	uint32_t f21;
+	uint32_t f22;
+	uint32_t f23;
+	uint32_t f24;
+	uint32_t f25;
+	uint32_t f26;
+	uint32_t f27;
+	uint32_t f28;
+	uint32_t f29;
+	uint32_t f30;
+	
 } context_t;
 
Index: libc/arch/mips32/src/entry.s
===================================================================
--- libc/arch/mips32/src/entry.s	(revision 846848a632676ac86608fbe67cb2574e1b00cc5e)
+++ libc/arch/mips32/src/entry.s	(revision 07d78705131fd1e3b5ec9c46c4d0949018348976)
@@ -61,4 +61,5 @@
 	jal __exit
 	nop
+.end
 
 .ent __entry_driver
@@ -83,5 +84,5 @@
 	jal __exit
 	nop
-
+.end
 # Alignment of output section data to 0x4000
 .section .data
Index: libc/arch/mips32/src/psthread.S
===================================================================
--- libc/arch/mips32/src/psthread.S	(revision 846848a632676ac86608fbe67cb2574e1b00cc5e)
+++ libc/arch/mips32/src/psthread.S	(revision 07d78705131fd1e3b5ec9c46c4d0949018348976)
@@ -38,5 +38,5 @@
 .global context_save
 .global context_restore
-
+	
 .macro CONTEXT_STORE r
 	sw $s0,OFFSET_S0(\r)
@@ -51,5 +51,40 @@
 	sw $gp,OFFSET_GP(\r)
 	sw $k1,OFFSET_TLS(\r)
+
+#ifdef CONFIG_MIPS_FPU	
+	mfc1 $t0,$20
+	sw $t0, OFFSET_F20(\r)
+
+	mfc1 $t0,$21
+	sw $t0, OFFSET_F21(\r)
+
+	mfc1 $t0,$22
+	sw $t0, OFFSET_F22(\r)
+
+	mfc1 $t0,$23
+	sw $t0, OFFSET_F23(\r)
+
+	mfc1 $t0,$24
+	sw $t0, OFFSET_F24(\r)
+
+	mfc1 $t0,$25
+	sw $t0, OFFSET_F25(\r)
+
+	mfc1 $t0,$26
+	sw $t0, OFFSET_F26(\r)
+
+	mfc1 $t0,$27
+	sw $t0, OFFSET_F27(\r)
+
+	mfc1 $t0,$28
+	sw $t0, OFFSET_F28(\r)
+
+	mfc1 $t0,$29
+	sw $t0, OFFSET_F29(\r)
 	
+	mfc1 $t0,$30
+	sw $t0, OFFSET_F30(\r)
+#endif	
+		
 	sw $ra,OFFSET_PC(\r)
 	sw $sp,OFFSET_SP(\r)
@@ -68,5 +103,40 @@
 	lw $gp,OFFSET_GP(\r)
 	lw $k1,OFFSET_TLS(\r)
-	
+
+#ifdef CONFIG_MIPS_FPU	
+	lw $t0, OFFSET_F20(\r)
+	mtc1 $t0,$20
+
+	lw $t0, OFFSET_F21(\r)
+	mtc1 $t0,$21
+
+	lw $t0, OFFSET_F22(\r)
+	mtc1 $t0,$22
+
+	lw $t0, OFFSET_F23(\r)
+	mtc1 $t0,$23
+
+	lw $t0, OFFSET_F24(\r)
+	mtc1 $t0,$24
+
+	lw $t0, OFFSET_F25(\r)
+	mtc1 $t0,$25
+
+	lw $t0, OFFSET_F26(\r)
+	mtc1 $t0,$26
+
+	lw $t0, OFFSET_F27(\r)
+	mtc1 $t0,$27
+
+	lw $t0, OFFSET_F28(\r)
+	mtc1 $t0,$28
+
+	lw $t0, OFFSET_F29(\r)
+	mtc1 $t0,$29
+
+	lw $t0, OFFSET_F30(\r)
+	mtc1 $t0,$30
+#endif	
+		
 	lw $ra,OFFSET_PC(\r)
 	lw $sp,OFFSET_SP(\r)
Index: uspace.config
===================================================================
--- uspace.config	(revision 846848a632676ac86608fbe67cb2574e1b00cc5e)
+++ uspace.config	(revision 07d78705131fd1e3b5ec9c46c4d0949018348976)
@@ -28,2 +28,6 @@
 ! [ARCH=ppc64] PPC64_COMPILER (choice)
 % [ARCH=ppc64] SAVEAS PPC64_COMPILER COMPILER
+
+# MIPS FPU support
+! [ARCH=mips32|ARCH=mips32eb] CONFIG_MIPS_FPU (n/y)
+