Changeset 07c66cf in mainline for uspace/srv

Timestamp:

2010-07-28T21:17:27Z (15 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

527298a

Parents:

1720cf9

Message:

Avoid magic numbers.

Location:

uspace/srv/hw/char/s3c24xx_uart

Files:

• s3c24xx_uart.c (modified) (3 diffs)
• s3c24xx_uart.h (modified) (1 diff)

uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.c

@@ -53 +53 @@
 #define NAME "s3c24ser"
 #define NAMESPACE "char"
-
-/* Bits in UTRSTAT register */
-#define S3C24XX_UTRSTAT_TX_EMPTY        0x4
-#define S3C24XX_UTRSTAT_RDATA           0x1
-
-/* Bits in UFSTAT register */
-#define S3C24XX_UFSTAT_TX_FULL          0x4000
-#define S3C24XX_UFSTAT_RX_FULL          0x0040
-#define S3C24XX_UFSTAT_RX_COUNT         0x002f
 
 static irq_cmd_t uart_irq_cmds[] = {
@@ -169 +160 @@
                 }
 
-                if (status & 0x0f)
+                if (status != 0)
                         printf(NAME ": Error status 0x%x\n", status);
         }
@@ -202 +193 @@
 
         /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */
-        pio_write_32(&uart->io->ufcon, 0x01);
+        pio_write_32(&uart->io->ufcon, UFCON_FIFO_ENABLE |
+            UFCON_TX_FIFO_TLEVEL_EMPTY | UFCON_RX_FIFO_TLEVEL_1B);
 
         /* Set RX interrupt to pulse mode */
         pio_write_32(&uart->io->ucon,
-            pio_read_32(&uart->io->ucon) & ~(1 << 8));
+            pio_read_32(&uart->io->ucon) & ~UCON_RX_INT_LEVEL);
 
         return EOK;

uspace/srv/hw/char/s3c24xx_uart/s3c24xx_uart.h

@@ -58 +58 @@
 } s3c24xx_uart_io_t;
 
+/* Bits in UTRSTAT register */
+#define S3C24XX_UTRSTAT_TX_EMPTY        0x4
+#define S3C24XX_UTRSTAT_RDATA           0x1
+
+/* Bits in UFSTAT register */
+#define S3C24XX_UFSTAT_TX_FULL          0x4000
+#define S3C24XX_UFSTAT_RX_FULL          0x0040
+#define S3C24XX_UFSTAT_RX_COUNT         0x002f
+
+/* Bits in UCON register */
+#define UCON_RX_INT_LEVEL               0x100
+
+/* Bits in UFCON register */
+#define UFCON_TX_FIFO_TLEVEL_EMPTY      0x00
+#define UFCON_RX_FIFO_TLEVEL_1B         0x00
+#define UFCON_FIFO_ENABLE               0x01
+
+
 /** S3C24xx UART instance */
 typedef struct {