Changeset 0777f4c5 in mainline for uspace/srv/hw/netif/dp8390/dp8390.c
- Timestamp:
- 2011-01-06T15:41:05Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 6fc0edd
- Parents:
- 74864ac
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/srv/hw/netif/dp8390/dp8390.c
r74864ac r0777f4c5 478 478 } 479 479 480 /*===========================================================================* 481 * dp_check_ints * 482 *===========================================================================*/ 483 void dp_check_ints(dep, isr) 484 dpeth_t *dep; 485 int isr; 486 { 487 int /*isr,*/ tsr; 480 void dp_check_ints(dpeth_t *dep) 481 { 482 int isr, tsr; 488 483 int size, sendq_tail; 489 490 if (!(dep->de_flags & DEF_ENABLED))484 485 if (!(dep->de_flags & DEF_ENABLED)) 491 486 fprintf(stderr, "dp8390: got premature interrupt\n"); 492 493 for(;;) 494 { 495 // isr = inb_reg0(dep, DP_ISR); 487 488 for (;;) { 489 isr = inb_reg0(dep, DP_ISR); 496 490 if (!isr) 497 491 break; 492 498 493 outb_reg0(dep, DP_ISR, isr); 499 if (isr &(ISR_PTX|ISR_TXE)) 500 { 501 if (isr &ISR_TXE) 502 { 494 495 if (isr & (ISR_PTX | ISR_TXE)) { 496 if (isr & ISR_TXE) 503 497 dep->de_stat.ets_sendErr++; 498 else { 499 tsr = inb_reg0(dep, DP_TSR); 500 501 if (tsr & TSR_PTX) 502 dep->de_stat.ets_packetT++; 503 504 if (tsr & TSR_COL) 505 dep->de_stat.ets_collision++; 506 507 if (tsr & TSR_ABT) 508 dep->de_stat.ets_transAb++; 509 510 if (tsr & TSR_CRS) 511 dep->de_stat.ets_carrSense++; 512 513 if ((tsr & TSR_FU) && (++dep->de_stat.ets_fifoUnder <= 10)) 514 printf("%s: fifo underrun\n", dep->de_name); 515 516 if ((tsr & TSR_CDH) && (++dep->de_stat.ets_CDheartbeat <= 10)) 517 printf("%s: CD heart beat failure\n", dep->de_name); 518 519 if (tsr & TSR_OWC) 520 dep->de_stat.ets_OWC++; 504 521 } 505 else 506 { 507 tsr = inb_reg0(dep, DP_TSR); 508 509 if (tsr &TSR_PTX) dep->de_stat.ets_packetT++; 510 #if 0 /* Reserved in later manuals, should be ignored */ 511 if (!(tsr &TSR_DFR)) 512 { 513 /* In most (all?) implementations of 514 * the dp8390, this bit is set 515 * when the packet is not deferred 516 */ 517 dep->de_stat.ets_transDef++; 518 } 519 #endif 520 if (tsr &TSR_COL) dep->de_stat.ets_collision++; 521 if (tsr &TSR_ABT) dep->de_stat.ets_transAb++; 522 if (tsr &TSR_CRS) dep->de_stat.ets_carrSense++; 523 if (tsr &TSR_FU 524 && ++dep->de_stat.ets_fifoUnder <= 10) 525 { 526 printf("%s: fifo underrun\n", 527 dep->de_name); 528 } 529 if (tsr &TSR_CDH 530 && ++dep->de_stat.ets_CDheartbeat <= 10) 531 { 532 printf("%s: CD heart beat failure\n", 533 dep->de_name); 534 } 535 if (tsr &TSR_OWC) dep->de_stat.ets_OWC++; 536 } 537 sendq_tail= dep->de_sendq_tail; 538 539 if (!(dep->de_sendq[sendq_tail].sq_filled)) 540 { 522 523 sendq_tail = dep->de_sendq_tail; 524 525 if (!(dep->de_sendq[sendq_tail].sq_filled)) { 541 526 /* Software bug? */ 542 527 assert(false); 543 528 544 529 /* Or hardware bug? */ 545 printf( 546 "%s: transmit interrupt, but not sending\n", 547 dep->de_name); 530 printf("%s: transmit interrupt, but not sending\n", dep->de_name); 548 531 continue; 549 532 } 550 dep->de_sendq[sendq_tail].sq_filled= 0; 533 534 dep->de_sendq[sendq_tail].sq_filled = 0; 535 551 536 if (++sendq_tail == dep->de_sendq_nr) 552 sendq_tail= 0; 553 dep->de_sendq_tail= sendq_tail; 554 if (dep->de_sendq[sendq_tail].sq_filled) 555 { 556 size= dep->de_sendq[sendq_tail].sq_size; 537 sendq_tail = 0; 538 539 dep->de_sendq_tail = sendq_tail; 540 541 if (dep->de_sendq[sendq_tail].sq_filled) { 542 size = dep->de_sendq[sendq_tail].sq_size; 557 543 outb_reg0(dep, DP_TPSR, 558 544 dep->de_sendq[sendq_tail].sq_sendpage); 559 545 outb_reg0(dep, DP_TBCR1, size >> 8); 560 outb_reg0(dep, DP_TBCR0, size & 0xff);546 outb_reg0(dep, DP_TBCR0, size & 0xff); 561 547 outb_reg0(dep, DP_CR, CR_TXP | CR_EXTRA); 562 548 } 549 563 550 // if (dep->de_flags &DEF_SEND_AVAIL) 564 551 dp_send(dep); 565 552 } 566 567 if (isr &ISR_PRX) 568 { 553 554 if (isr & ISR_PRX) { 569 555 /* Only call dp_recv if there is a read request */ 570 556 // if (dep->de_flags) &DEF_READING) … … 572 558 } 573 559 574 if (isr &ISR_RXE) dep->de_stat.ets_recvErr++; 575 if (isr &ISR_CNT) 576 { 560 if (isr & ISR_RXE) 561 dep->de_stat.ets_recvErr++; 562 563 if (isr & ISR_CNT) { 577 564 dep->de_stat.ets_CRCerr += inb_reg0(dep, DP_CNTR0); 578 565 dep->de_stat.ets_frameAll += inb_reg0(dep, DP_CNTR1); 579 566 dep->de_stat.ets_missedP += inb_reg0(dep, DP_CNTR2); 580 567 } 581 if (isr &ISR_OVW)582 {568 569 if (isr & ISR_OVW) { 583 570 dep->de_stat.ets_OVW++; 584 #if 0 585 {printW(); printf( 586 "%s: got overwrite warning\n", dep->de_name);} 587 #endif 588 /* if (dep->de_flags &DEF_READING) 589 { 590 printf( 591 "dp_check_ints: strange: overwrite warning and pending read request\n"); 571 /* if (dep->de_flags & DEF_READING) { 572 printf("dp_check_ints: strange: overwrite warning and pending read request\n"); 592 573 dp_recv(dep); 593 574 } 594 575 */ } 595 if (isr &ISR_RDC)596 {576 577 if (isr & ISR_RDC) { 597 578 /* Nothing to do */ 598 579 } 599 if (isr &ISR_RST) 600 { 601 /* this means we got an interrupt but the ethernet 580 581 if (isr & ISR_RST) { 582 /* 583 * This means we got an interrupt but the ethernet 602 584 * chip is shutdown. We set the flag DEF_STOPPED, 603 585 * and continue processing arrived packets. When the 604 586 * receive buffer is empty, we reset the dp8390. 605 587 */ 606 #if 0607 {printW(); printf(608 "%s: NIC stopped\n", dep->de_name);}609 #endif610 588 dep->de_flags |= DEF_STOPPED; 611 589 break; 612 590 } 613 isr = inb_reg0(dep, DP_ISR); 614 } 615 // if ((dep->de_flags &(DEF_READING|DEF_STOPPED)) == 616 // (DEF_READING|DEF_STOPPED)) 617 if ((dep->de_flags &DEF_STOPPED) == DEF_STOPPED) 618 { 619 /* The chip is stopped, and all arrived packets are 620 * delivered. 591 } 592 593 // if ((dep->de_flags & (DEF_READING | DEF_STOPPED)) == (DEF_READING | DEF_STOPPED)) 594 if ((dep->de_flags & DEF_STOPPED) == DEF_STOPPED) { 595 /* 596 * The chip is stopped, and all arrived packets 597 * are delivered. 621 598 */ 622 599 dp_reset(dep);
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