Index: uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision 712a10b0c43fb640bc561b97efe87b1ca4b0fb0f)
+++ uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c	(revision 063ae7061e8d9afc7544f3cfa1e0c2b6d4342952)
@@ -43,8 +43,11 @@
 #include <ddi.h>
 
+#include "uhh.h"
+#include "usbtll.h"
+
 #define NAME  "rootamdm37x"
 
 /** Obtain function soft-state from DDF function node */
-#define ROOTMAC_FUN(fnode) \
+#define ROOTARM_FUN(fnode) \
 	((rootamdm37x_fun_t *) (fnode)->driver_data)
 
@@ -53,4 +56,9 @@
 } rootamdm37x_fun_t;
 
+#define OHCI_BASE_ADDRESS  0x48064400
+#define OHCI_SIZE  1024
+#define EHCI_BASE_ADDRESS  0x48064800
+#define EHCI_SIZE  1024
+
 static hw_resource_t ohci_res[] = {
 	{
@@ -58,6 +66,6 @@
 		/* See amdm37x TRM page. 3316 for these values */
 		.res.io_range = {
-			.address = 0x48064400,
-			.size = 1024,
+			.address = OHCI_BASE_ADDRESS,
+			.size = OHCI_SIZE,
 			.endianness = LITTLE_ENDIAN
 		},
@@ -66,20 +74,4 @@
 		.type = INTERRUPT,
 		.res.interrupt = { .irq = 76 },
-	},
-};
-
-static hw_resource_t ehci_res[] = {
-	{
-		.type = MEM_RANGE,
-		/* See amdm37x TRM page. 3316 for these values */
-		.res.io_range = {
-			.address = 0x48064800,
-			.size = 1024,
-			.endianness = LITTLE_ENDIAN
-		},
-	},
-	{
-		.type = INTERRUPT,
-		.res.interrupt = { .irq = 77 },
 	},
 };
@@ -92,4 +84,20 @@
 };
 
+static hw_resource_t ehci_res[] = {
+	{
+		.type = MEM_RANGE,
+		/* See amdm37x TRM page. 3316 for these values */
+		.res.io_range = {
+			.address = EHCI_BASE_ADDRESS,
+			.size = EHCI_SIZE,
+			.endianness = LITTLE_ENDIAN
+		},
+	},
+	{
+		.type = INTERRUPT,
+		.res.interrupt = { .irq = 77 },
+	},
+};
+
 static const rootamdm37x_fun_t ehci = {
 	.hw_resources = {
@@ -99,6 +107,58 @@
 };
 
-
-static ddf_dev_ops_t rootamdm37x_fun_ops;
+static hw_resource_list_t *rootamdm37x_get_resources(ddf_fun_t *fnode);
+static bool rootamdm37x_enable_interrupt(ddf_fun_t *fun);
+
+static hw_res_ops_t fun_hw_res_ops = {
+	.get_resource_list = &rootamdm37x_get_resources,
+	.enable_interrupt = &rootamdm37x_enable_interrupt,
+};
+
+static ddf_dev_ops_t rootamdm37x_fun_ops =
+{
+	.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops
+};
+
+static int usb_clocks(bool on)
+{
+	uint32_t *usb_host_cm = NULL;
+	uint32_t *l4_core_cm = NULL;
+
+	int ret = pio_enable((void*)0x48005400, 8192, (void**)&usb_host_cm);
+	if (ret != EOK)
+		return ret;
+
+	ret = pio_enable((void*)0x48004a00, 8192, (void**)&l4_core_cm);
+	if (ret != EOK)
+		return ret;
+
+	assert(l4_core_cm);
+	assert(usb_host_cm);
+	if (on) {
+		l4_core_cm[0xe] |= 0x4;  /* iclk */
+		l4_core_cm[0x3] |= 0x4;  /* fclk */
+
+		/* offset 0x10 (0x4 int32)[0] enables fclk,
+		 * offset 0x00 (0x0 int32)[0 and 1] enables iclk,
+		 * offset 0x30 (0xc int32)[0] enables autoidle
+		 */
+		usb_host_cm[0x4] = 0x1;
+		usb_host_cm[0x0] = 0x3;
+		usb_host_cm[0xc] = 0x1;
+	} else {
+		usb_host_cm[0xc] = 0;
+		usb_host_cm[0x0] = 0;
+		usb_host_cm[0x4] = 0;
+		l4_core_cm[0xe] &= ~0x4;
+		l4_core_cm[0x3] &= ~0x4;
+	}
+
+	return ret;
+}
+
+static int usb_tll_init()
+{
+	return EOK;
+}
 
 static bool rootamdm37x_add_fun(ddf_dev_t *dev, const char *name,
@@ -151,5 +211,5 @@
 }
 
-/** Get the root device.
+/** Add the root device.
  *
  * @param dev Device which is root of the whole device tree
@@ -161,17 +221,15 @@
 static int rootamdm37x_dev_add(ddf_dev_t *dev)
 {
-	{
-	/* Enable USB host clocks */
-	uint32_t *reg = NULL;
-	const int ret = pio_enable((void*)0x48005400, 8192, (void**)&reg);
-	assert(ret == EOK);
-	assert(reg);
-	/* offset 0x10 (0x4 int32)[0] enables fclk,
-	 * offset 0x00 (0x0 int32)[0 and 1] enables iclk,
-	 * offset 0x30 (0xc int32)[0] enables autoidle
-	 */
-	reg[0x4] = 0x1;
-	reg[0x0] = 0x3;
-	reg[0xc] = 0x1;
+	int ret = usb_clocks(true);
+	if (ret != EOK) {
+		ddf_msg(LVL_FATAL, "Failed to enable USB HC clocks!.\n");
+		return ret;
+	}
+
+	ret = usb_tll_init();
+	if (ret != EOK) {
+		ddf_msg(LVL_FATAL, "Failed to init USB TLL!.\n");
+		usb_clocks(false);
+		return ret;
 	}
 
@@ -200,7 +258,6 @@
 static hw_resource_list_t *rootamdm37x_get_resources(ddf_fun_t *fnode)
 {
-	rootamdm37x_fun_t *fun = ROOTMAC_FUN(fnode);
+	rootamdm37x_fun_t *fun = ROOTARM_FUN(fnode);
 	assert(fun != NULL);
-	
 	return &fun->hw_resources;
 }
@@ -209,12 +266,6 @@
 {
 	/* TODO */
-	
 	return false;
 }
-
-static hw_res_ops_t fun_hw_res_ops = {
-   	.get_resource_list = &rootamdm37x_get_resources,
-	.enable_interrupt = &rootamdm37x_enable_interrupt
-};
 
 int main(int argc, char *argv[])
@@ -222,5 +273,4 @@
 	printf("%s: HelenOS AM/DM37x(OMAP37x) platform driver\n", NAME);
 	ddf_log_init(NAME, LVL_ERROR);
-	rootamdm37x_fun_ops.interfaces[HW_RES_DEV_IFACE] = &fun_hw_res_ops;
 	return ddf_driver_main(&rootamdm37x_driver);
 }
Index: uspace/drv/infrastructure/rootamdm37x/uhh.h
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/uhh.h	(revision 063ae7061e8d9afc7544f3cfa1e0c2b6d4342952)
+++ uspace/drv/infrastructure/rootamdm37x/uhh.h	(revision 063ae7061e8d9afc7544f3cfa1e0c2b6d4342952)
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup amdm37xdrvuhh
+ * @{
+ */
+/** @file
+ * @brief UHH IO register structure.
+ */
+#ifndef AMDM37x_UHH_H
+#define AMDM37x_UHH_H
+#include <sys/types.h>
+
+#define AMDM37x_UHH_BASE_ADDRESS  0x48064000
+#define AMDM37x_UHH_SIZE  1024
+
+typedef struct {
+	const ioport32_t revision;
+#define UHH_REVISION_MASK  0xf
+#define UHH_REVISION_MINOR_SHIFT  0
+#define UHH_REVISION_MAJOR_SHIFT  4
+
+	uint32_t padd0_[3];
+	ioport32_t sysconfig;
+#define UHH_SYSCONFIG_AUTOIDLE_FLAG  (1 << 0)
+#define UHH_SYSCONFIG_SOFTRESET_FLAG  (1 << 1)
+#define UHH_SYSCONFIG_ENWAKEUP_FLAG  (1 << 2)
+#define UHH_SYSCONFIG_CLOCKACTIVITY_FLAG  (1 << 8)
+#define UHH_SYSCONFIG_SIDLE_MODE_MASK  0x3
+#define UHH_SYSCONFIG_SIDLE_MODE_SHIFT  3
+#define UHH_SYSCONFIG_MIDLE_MODE_MASK  0x3
+#define UHH_SYSCONFIG_MIDLE_MODE_SHIFT  12
+
+	const ioport32_t sysstatus;
+#define UHH_SYSSTATUS_RESETDONE_FLAG  (1 << 0)
+#define UHH_SYSSTATUS_OHCI_RESETDONE_FLAG  (1 << 1)
+#define UHH_SYSSTATUS_EHCI_RESETDONE_FLAG  (1 << 2)
+
+	uint32_t padd1_[10];
+	ioport32_t hostconfig;
+#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_FLAG  (1 << 0)
+#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_FLAG  (1 << 1)
+#define UHH_HOSTCONFIG_ENA_INCR4_FLAG  (1 << 2)
+#define UHH_HOSTCONFIG_ENA_INCR8_FLAG  (1 << 3)
+#define UHH_HOSTCONFIG_ENA_INCR16_FLA  (1 << 4)
+#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_FLAG  (1 << 5)
+#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_FLAG  (1 << 8)
+#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_FLAG  (1 << 9)
+#define UHH_HOSTCONFIG_P3_CONNECT_STATUS_FLAG  (1 << 10)
+#define UHH_HOSTCONFIG_P2_ULPI_BYPASS_FLAG  (1 << 11)
+#define UHH_HOSTCONFIG_P3_ULPI_BYPASS_FLAG  (1 << 12)
+
+	ioport32_t debug_csr;
+#define UHH_DEBUG_CSR_EHCI_FLADJ_MASK  (0x3f)
+#define UHH_DEBUG_CSR_EHCI_FLADJ_SHIFT  0
+#define UHH_DEBUG_CSR_EHCI_SIMULATION_MODE_FLAG  (1 << 6)
+#define UHH_DEBUG_CSR_OHCI_CNTSEL_FLAG  (1 << 7)
+#define UHH_DEBUG_CSR_OHCI_GLOBAL_sUSPEND_FLAG  (1 << 16)
+#define UHH_DEBUG_CSR_OHCI_CCS1_FLAG  (1 << 17)
+#define UHH_DEBUG_CSR_OHCI_CCS2_FLAG  (1 << 18)
+#define UHH_DEBUG_CSR_OHCI_CCS3_FLAG  (1 << 19)
+
+} uhh_regs_t;
+
+#endif
+/**
+ * @}
+ */
Index: uspace/drv/infrastructure/rootamdm37x/usbtll.h
===================================================================
--- uspace/drv/infrastructure/rootamdm37x/usbtll.h	(revision 063ae7061e8d9afc7544f3cfa1e0c2b6d4342952)
+++ uspace/drv/infrastructure/rootamdm37x/usbtll.h	(revision 063ae7061e8d9afc7544f3cfa1e0c2b6d4342952)
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012 Jan Vesely
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/** @addtogroup amdm37xdrvusbtll
+ * @{
+ */
+/** @file
+ * @brief USBTLL IO register structure.
+ */
+#ifndef AMDM37x_USBTLL_H
+#define AMDM37x_USBTLL_H
+#include <sys/types.h>
+
+#define AMDM37x_USBTLL_BASE_ADDRESS  0x48062000
+#define AMDM37x_USBTLL_SIZE  4096
+
+typedef struct {
+	const ioport32_t revision;
+#define TLL_REVISION_MASK  0xf
+#define TLL_REVISION_MINOR_SHIFT  0
+#define TLL_REVISION_MAJOR_SHIFT  4
+
+	uint32_t padd0_[3];
+	ioport32_t sysconfig;
+#define TLL_SYSCONFIG_AUTOIDLE_FLAG  (1 << 0)
+#define TLL_SYSCONFIG_SOFTRESET_FLAG  (1 << 1)
+#define TLL_SYSCONFIG_ENWAKEUP_FLAG  (1 << 2)
+#define TLL_SYSCONFIG_CLOCKACTIVITY_FLAG  (1 << 8)
+#define TLL_SYSCONFIG_SIDLE_MODE_MASK  0x3
+#define TLL_SYSCONFIG_SIDLE_MODE_SHIFT  3
+
+	ioport32_t sysstatus;
+#define TLL_SYSSTATUS_RESET_DONE_FLAG  (1 << 0)
+
+	const ioport32_t irqstatus;
+#define TLL_IRQSTATUS_FCLK_START_FLAG  (1 << 0)
+#define TLL_IRQSTATUS_FCLK_END_FLAG  (1 << 1)
+#define TLL_IRQSTATUS_ACCESS_ERROR_FLAG  (1 << 2)
+
+	ioport32_t irqenable;
+#define TLL_IRQSTATUS_FCLK_START_EN_FLAG  (1 << 0)
+#define TLL_IRQSTATUS_FCLK_END_EN_FLAG  (1 << 1)
+#define TLL_IRQSTATUS_ACCESS_ERROR_EN_FLAG  (1 << 2)
+
+	uint32_t padd1_[4];
+	ioport32_t shared_conf;
+#define TLL_SHARED_CONF_FCLK_IS_ON_FLAG  (1 << 0)
+#define TLL_SHARED_CONF_FCLK_REQ_FLAG  (1 << 1)
+#define TLL_SHARED_CONF_USB_180D_SDR_EN_FLAG  (1 << 5)
+#define TLL_SHARED_CONF_USB_90D_DDR_EN_FLAG  (1 << 6)
+#define TLL_SHARED_CONF_USB_DIVRATIO_MASK  0x7
+#define TLL_SHARED_CONF_USB_DIVRATIO_SHIFT 2
+
+	uint32_t padd2_[3];
+	ioport32_t channel_conf[3];
+#define TLL_CHANNEL_CONF_CHANEN_FLAG  (1 << 0)
+#define TLL_CHANNEL_CONF_CHANMODE_MASK  0x3
+#define TLL_CHANNEL_CONF_CHANMODE_SHIFT  1
+#define TLL_CHANNEL_CONF_UTMIISADEV_FLAG  (1 << 3)
+#define TLL_CHANNEL_CONF_TLLATTACH_FLAG  (1 << 4)
+#define TLL_CHANNEL_CONF_TLLCONNECT_FLAG  (1 << 5)
+#define TLL_CHANNEL_CONF_TLLFULLSPEED_FLAG  (1 << 6)
+#define TLL_CHANNEL_CONF_ULPIOUTCLKMODE_FLAG  (1 << 7)
+#define TLL_CHANNEL_CONF_ULPIDDRMODE_FLAG  (1 << 8)
+#define TLL_CHANNEL_CONF_UTMIAUTOIDLE_FLAG  (1 << 9)
+#define TLL_CHANNEL_CONF_ULPIAUTOIDLE_FLAG  (1 << 10)
+#define TLL_CHANNEL_CONF_ULPINOBITSTUFF_FLAG  (1 << 11)
+#define TLL_CHANNEL_CONF_CHRGVBUS_FLAG  (1 << 15)
+#define TLL_CHANNEL_CONF_DRVVBUS_FLAG  (1 << 16)
+#define TLL_CHANNEL_CONF_TESTEN_FLAG  (1 << 17)
+#define TLL_CHANNEL_CONF_TESTTXEN_FLAG  (1 << 18)
+#define TLL_CHANNEL_CONF_TESTTXDAT_FLAG  (1 << 19)
+#define TLL_CHANNEL_CONF_TESTTXSE0_FLAG  (1 << 20)
+#define TLL_CHANNEL_CONF_FSLSMODE_MASK  0xf
+#define TLL_CHANNEL_CONF_FSLSMODE_SHIFT  24
+#define TLL_CHANNEL_CONF_FSLSLINESTATE_MASK  0x3
+#define TLL_CHANNEL_CONF_FSLSLINESTATE_SHIFT  28
+
+	/* The rest are 8bit ULPI registers */
+} tll_regs_t;
+
+#endif
+/**
+ * @}
+ */
+
