Index: kernel/arch/sparc64/include/arch.h =================================================================== --- kernel/arch/sparc64/include/arch.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,62 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** - * @file - * @brief Various sparc64-specific macros. - */ - -#ifndef KERN_sparc64_ARCH_H_ -#define KERN_sparc64_ARCH_H_ - -#include - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#endif - -#define ASI_AIUP 0x10 /** Access to primary context with user privileges. */ -#define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ - -#define NWINDOWS 8 /** Number of register window sets. */ - -#ifndef __ASM__ - -extern void arch_pre_main(bootinfo_t *); - -#endif /* __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/arch/arch.h =================================================================== --- kernel/arch/sparc64/include/arch/arch.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/arch.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** + * @file + * @brief Various sparc64-specific macros. + */ + +#ifndef KERN_sparc64_ARCH_H_ +#define KERN_sparc64_ARCH_H_ + +#include + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + +#define ASI_AIUP 0x10 /** Access to primary context with user privileges. */ +#define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ + +#define NWINDOWS 8 /** Number of register window sets. */ + +#ifndef __ASM__ + +extern void arch_pre_main(bootinfo_t *); + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/asm.h =================================================================== --- kernel/arch/sparc64/include/arch/asm.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/asm.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,557 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_ASM_H_ +#define KERN_sparc64_ASM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) +{ + *port = v; + memory_barrier(); +} + +NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) +{ + *port = v; + memory_barrier(); +} + +NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) +{ + *port = v; + memory_barrier(); +} + +NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) +{ + uint8_t rv = *port; + memory_barrier(); + return rv; +} + +NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) +{ + uint16_t rv = *port; + memory_barrier(); + return rv; +} + +NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) +{ + uint32_t rv = *port; + memory_barrier(); + return rv; +} + +/** Read Processor State register. + * + * @return Value of PSTATE register. + * + */ +NO_TRACE static inline uint64_t pstate_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%pstate, %[v]\n" + : [v] "=r" (v) + ); + + return v; +} + +/** Write Processor State register. + * + * @param v New value of PSTATE register. + * + */ +NO_TRACE static inline void pstate_write(uint64_t v) +{ + asm volatile ( + "wrpr %[v], %[zero], %%pstate\n" + :: [v] "r" (v), + [zero] "i" (0) + ); +} + +/** Read TICK_compare Register. + * + * @return Value of TICK_comapre register. + * + */ +NO_TRACE static inline uint64_t tick_compare_read(void) +{ + uint64_t v; + + asm volatile ( + "rd %%tick_cmpr, %[v]\n" + : [v] "=r" (v) + ); + + return v; +} + +/** Write TICK_compare Register. + * + * @param v New value of TICK_comapre register. + * + */ +NO_TRACE static inline void tick_compare_write(uint64_t v) +{ + asm volatile ( + "wr %[v], %[zero], %%tick_cmpr\n" + :: [v] "r" (v), + [zero] "i" (0) + ); +} + +/** Read STICK_compare Register. + * + * @return Value of STICK_compare register. + * + */ +NO_TRACE static inline uint64_t stick_compare_read(void) +{ + uint64_t v; + + asm volatile ( + "rd %%asr25, %[v]\n" + : [v] "=r" (v) + ); + + return v; +} + +/** Write STICK_compare Register. + * + * @param v New value of STICK_comapre register. + * + */ +NO_TRACE static inline void stick_compare_write(uint64_t v) +{ + asm volatile ( + "wr %[v], %[zero], %%asr25\n" + :: [v] "r" (v), + [zero] "i" (0) + ); +} + +/** Read TICK Register. + * + * @return Value of TICK register. + * + */ +NO_TRACE static inline uint64_t tick_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%tick, %[v]\n" + : [v] "=r" (v) + ); + + return v; +} + +/** Write TICK Register. + * + * @param v New value of TICK register. + * + */ +NO_TRACE static inline void tick_write(uint64_t v) +{ + asm volatile ( + "wrpr %[v], %[zero], %%tick\n" + :: [v] "r" (v), + [zero] "i" (0) + ); +} + +/** Read FPRS Register. + * + * @return Value of FPRS register. + * + */ +NO_TRACE static inline uint64_t fprs_read(void) +{ + uint64_t v; + + asm volatile ( + "rd %%fprs, %[v]\n" + : [v] "=r" (v) + ); + + return v; +} + +/** Write FPRS Register. + * + * @param v New value of FPRS register. + * + */ +NO_TRACE static inline void fprs_write(uint64_t v) +{ + asm volatile ( + "wr %[v], %[zero], %%fprs\n" + :: [v] "r" (v), + [zero] "i" (0) + ); +} + +/** Read SOFTINT Register. + * + * @return Value of SOFTINT register. + * + */ +NO_TRACE static inline uint64_t softint_read(void) +{ + uint64_t v; + + asm volatile ( + "rd %%softint, %[v]\n" + : [v] "=r" (v) + ); + + return v; +} + +/** Write SOFTINT Register. + * + * @param v New value of SOFTINT register. + * + */ +NO_TRACE static inline void softint_write(uint64_t v) +{ + asm volatile ( + "wr %[v], %[zero], %%softint\n" + :: [v] "r" (v), + [zero] "i" (0) + ); +} + +/** Write CLEAR_SOFTINT Register. + * + * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. + * + * @param v New value of CLEAR_SOFTINT register. + * + */ +NO_TRACE static inline void clear_softint_write(uint64_t v) +{ + asm volatile ( + "wr %[v], %[zero], %%clear_softint\n" + :: [v] "r" (v), + [zero] "i" (0) + ); +} + +/** Write SET_SOFTINT Register. + * + * Bits set in SET_SOFTINT register will be set in SOFTINT register. + * + * @param v New value of SET_SOFTINT register. + * + */ +NO_TRACE static inline void set_softint_write(uint64_t v) +{ + asm volatile ( + "wr %[v], %[zero], %%set_softint\n" + :: [v] "r" (v), + [zero] "i" (0) + ); +} + +/** Enable interrupts. + * + * Enable interrupts and return previous + * value of IPL. + * + * @return Old interrupt priority level. + * + */ +NO_TRACE static inline ipl_t interrupts_enable(void) { + pstate_reg_t pstate; + uint64_t value = pstate_read(); + + pstate.value = value; + pstate.ie = true; + pstate_write(pstate.value); + + return (ipl_t) value; +} + +/** Disable interrupts. + * + * Disable interrupts and return previous + * value of IPL. + * + * @return Old interrupt priority level. + * + */ +NO_TRACE static inline ipl_t interrupts_disable(void) { + pstate_reg_t pstate; + uint64_t value = pstate_read(); + + pstate.value = value; + pstate.ie = false; + pstate_write(pstate.value); + + return (ipl_t) value; +} + +/** Restore interrupt priority level. + * + * Restore IPL. + * + * @param ipl Saved interrupt priority level. + * + */ +NO_TRACE static inline void interrupts_restore(ipl_t ipl) { + pstate_reg_t pstate; + + pstate.value = pstate_read(); + pstate.ie = ((pstate_reg_t) ipl).ie; + pstate_write(pstate.value); +} + +/** Return interrupt priority level. + * + * Return IPL. + * + * @return Current interrupt priority level. + * + */ +NO_TRACE static inline ipl_t interrupts_read(void) { + return (ipl_t) pstate_read(); +} + +/** Check interrupts state. + * + * @return True if interrupts are disabled. + * + */ +NO_TRACE static inline bool interrupts_disabled(void) +{ + pstate_reg_t pstate; + + pstate.value = pstate_read(); + return !pstate.ie; +} + +/** Return base address of current stack. + * + * Return the base address of the current stack. + * The stack is assumed to be STACK_SIZE bytes long. + * The stack must start on page boundary. + * + */ +NO_TRACE static inline uintptr_t get_stack_base(void) +{ + uintptr_t unbiased_sp; + + asm volatile ( + "add %%sp, %[stack_bias], %[unbiased_sp]\n" + : [unbiased_sp] "=r" (unbiased_sp) + : [stack_bias] "i" (STACK_BIAS) + ); + + return ALIGN_DOWN(unbiased_sp, STACK_SIZE); +} + +/** Read Version Register. + * + * @return Value of VER register. + * + */ +NO_TRACE static inline uint64_t ver_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%ver, %[v]\n" + : [v] "=r" (v) + ); + + return v; +} + +/** Read Trap Program Counter register. + * + * @return Current value in TPC. + * + */ +NO_TRACE static inline uint64_t tpc_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%tpc, %[v]\n" + : [v] "=r" (v) + ); + + return v; +} + +/** Read Trap Level register. + * + * @return Current value in TL. + * + */ +NO_TRACE static inline uint64_t tl_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%tl, %[v]\n" + : [v] "=r" (v) + ); + + return v; +} + +/** Read Trap Base Address register. + * + * @return Current value in TBA. + * + */ +NO_TRACE static inline uint64_t tba_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%tba, %[v]\n" + : [v] "=r" (v) + ); + + return v; +} + +/** Write Trap Base Address register. + * + * @param v New value of TBA. + * + */ +NO_TRACE static inline void tba_write(uint64_t v) +{ + asm volatile ( + "wrpr %[v], %[zero], %%tba\n" + :: [v] "r" (v), + [zero] "i" (0) + ); +} + +/** Load uint64_t from alternate space. + * + * @param asi ASI determining the alternate space. + * @param va Virtual address within the ASI. + * + * @return Value read from the virtual address in + * the specified address space. + * + */ +NO_TRACE static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) +{ + uint64_t v; + + asm volatile ( + "ldxa [%[va]] %[asi], %[v]\n" + : [v] "=r" (v) + : [va] "r" (va), + [asi] "i" ((unsigned int) asi) + ); + + return v; +} + +/** Store uint64_t to alternate space. + * + * @param asi ASI determining the alternate space. + * @param va Virtual address within the ASI. + * @param v Value to be written. + * + */ +NO_TRACE static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) +{ + asm volatile ( + "stxa %[v], [%[va]] %[asi]\n" + :: [v] "r" (v), + [va] "r" (va), + [asi] "i" ((unsigned int) asi) + : "memory" + ); +} + +/** Flush all valid register windows to memory. */ +NO_TRACE static inline void flushw(void) +{ + asm volatile ("flushw\n"); +} + +/** Switch to nucleus by setting TL to 1. */ +NO_TRACE static inline void nucleus_enter(void) +{ + asm volatile ("wrpr %g0, 1, %tl\n"); +} + +/** Switch from nucleus by setting TL to 0. */ +NO_TRACE static inline void nucleus_leave(void) +{ + asm volatile ("wrpr %g0, %g0, %tl\n"); +} + +extern void cpu_halt(void) __attribute__((noreturn)); +extern void cpu_sleep(void); +extern void asm_delay_loop(const uint32_t usec); + +extern uint64_t read_from_ag_g6(void); +extern uint64_t read_from_ag_g7(void); +extern void write_to_ag_g6(uint64_t val); +extern void write_to_ag_g7(uint64_t val); +extern void write_to_ig_g6(uint64_t val); + +extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/atomic.h =================================================================== --- kernel/arch/sparc64/include/arch/atomic.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/atomic.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_ATOMIC_H_ +#define KERN_sparc64_ATOMIC_H_ + +#include +#include +#include +#include + +/** Atomic add operation. + * + * Use atomic compare and swap operation to atomically add signed value. + * + * @param val Atomic variable. + * @param i Signed value to be added. + * + * @return Value of the atomic variable as it existed before addition. + * + */ +NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val, + atomic_count_t i) +{ + atomic_count_t a; + atomic_count_t b; + + do { + volatile uintptr_t ptr = (uintptr_t) &val->count; + + a = *((atomic_count_t *) ptr); + b = a + i; + + asm volatile ( + "casx %0, %2, %1\n" + : "+m" (*((atomic_count_t *) ptr)), + "+r" (b) + : "r" (a) + ); + } while (a != b); + + return a; +} + +NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val) +{ + return atomic_add(val, 1) + 1; +} + +NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) +{ + return atomic_add(val, 1); +} + +NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val) +{ + return atomic_add(val, -1) - 1; +} + +NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) +{ + return atomic_add(val, -1); +} + +NO_TRACE static inline void atomic_inc(atomic_t *val) +{ + (void) atomic_add(val, 1); +} + +NO_TRACE static inline void atomic_dec(atomic_t *val) +{ + (void) atomic_add(val, -1); +} + +NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val) +{ + atomic_count_t v = 1; + volatile uintptr_t ptr = (uintptr_t) &val->count; + + asm volatile ( + "casx %0, %2, %1\n" + : "+m" (*((atomic_count_t *) ptr)), + "+r" (v) + : "r" (0) + ); + + return v; +} + +NO_TRACE static inline void atomic_lock_arch(atomic_t *val) +{ + atomic_count_t tmp1 = 1; + atomic_count_t tmp2 = 0; + + volatile uintptr_t ptr = (uintptr_t) &val->count; + + preemption_disable(); + + asm volatile ( + "0:\n" + "casx %0, %3, %1\n" + "brz %1, 2f\n" + "nop\n" + "1:\n" + "ldx %0, %2\n" + "brz %2, 0b\n" + "nop\n" + "ba,a %%xcc, 1b\n" + "2:\n" + : "+m" (*((atomic_count_t *) ptr)), + "+r" (tmp1), + "+r" (tmp2) + : "r" (0) + ); + + /* + * Prevent critical section code from bleeding out this way up. + */ + CS_ENTER_BARRIER(); +} + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/barrier.h =================================================================== --- kernel/arch/sparc64/include/arch/barrier.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/barrier.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_BARRIER_H_ +#define KERN_sparc64_BARRIER_H_ + +#include + +/* + * Our critical section barriers are prepared for the weakest RMO memory model. + */ +#define CS_ENTER_BARRIER() \ + asm volatile ( \ + "membar #LoadLoad | #LoadStore\n" \ + ::: "memory" \ + ) + +#define CS_LEAVE_BARRIER() \ + asm volatile ( \ + "membar #StoreStore\n" \ + "membar #LoadStore\n" \ + ::: "memory" \ + ) + +#define memory_barrier() \ + asm volatile ( \ + "membar #LoadLoad | #StoreStore\n" \ + ::: "memory" \ + ) + +#define read_barrier() \ + asm volatile ( \ + "membar #LoadLoad\n" \ + ::: "memory" \ + ) + +#define write_barrier() \ + asm volatile ( \ + "membar #StoreStore\n" \ + ::: "memory" \ + ) + +#define flush(a) \ + asm volatile ( \ + "flush %[reg]\n" \ + :: [reg] "r" ((a)) \ + : "memory" \ + ) + +/** Flush Instruction pipeline. */ +NO_TRACE static inline void flush_pipeline(void) +{ + uint64_t pc; + + /* + * The FLUSH instruction takes address parameter. + * As such, it may trap if the address is not found in DTLB. + * + * The entire kernel text is mapped by a locked ITLB and + * DTLB entries. Therefore, when this function is called, + * the %pc register will always be in the range mapped by + * DTLB. + * + */ + + asm volatile ( + "rd %%pc, %[pc]\n" + "flush %[pc]\n" + : [pc] "=&r" (pc) + ); +} + +/** Memory Barrier instruction. */ +NO_TRACE static inline void membar(void) +{ + asm volatile ( + "membar #Sync\n" + ); +} + +#if defined (US) + +#define FLUSH_INVAL_MIN 4 + +#define smc_coherence(a) \ + do { \ + write_barrier(); \ + flush((a)); \ + } while (0) + +#define smc_coherence_block(a, l) \ + do { \ + unsigned long i; \ + write_barrier(); \ + \ + for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \ + flush((void *)(a) + i); \ + } while (0) + +#elif defined (US3) + +#define smc_coherence(a) \ + do { \ + write_barrier(); \ + flush_pipeline(); \ + } while (0) + +#define smc_coherence_block(a, l) \ + do { \ + write_barrier(); \ + flush_pipeline(); \ + } while (0) + +#endif /* defined(US3) */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/boot/boot.h =================================================================== --- kernel/arch/sparc64/include/arch/boot/boot.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/boot/boot.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_BOOT_H_ +#define KERN_sparc64_BOOT_H_ + +#define VMA 0x400000 +#define LMA VMA + +#ifndef __ASM__ +#ifndef __LINKER__ + +#include +#include +#include + +#define TASKMAP_MAX_RECORDS 32 +#define MEMMAP_MAX_RECORDS 32 + +#define BOOTINFO_TASK_NAME_BUFLEN 32 + +typedef struct { + void *addr; + size_t size; + char name[BOOTINFO_TASK_NAME_BUFLEN]; +} utask_t; + +typedef struct { + size_t cnt; + utask_t tasks[TASKMAP_MAX_RECORDS]; +} taskmap_t; + +typedef struct { + void *start; + size_t size; +} memzone_t; + +typedef struct { + uint64_t total; + size_t cnt; + memzone_t zones[MEMMAP_MAX_RECORDS]; +} memmap_t; + +/** Bootinfo structure. + * + * Must be in sync with bootinfo structure used by the boot loader. + * + */ +typedef struct { + uintptr_t physmem_start; + taskmap_t taskmap; + memmap_t memmap; + ballocs_t ballocs; + ofw_tree_node_t *ofw_root; +} bootinfo_t; + +extern memmap_t memmap; + +#endif +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/console.h =================================================================== --- kernel/arch/sparc64/include/arch/console.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/console.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_CONSOLE_H_ +#define KERN_sparc64_CONSOLE_H_ + +extern void kkbdpoll(void *arg); +extern void standalone_sparc64_console_init(void); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/context.h =================================================================== --- kernel/arch/sparc64/include/arch/context.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/context.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_CONTEXT_H_ +#define KERN_sparc64_CONTEXT_H_ + +#include +#include +#include + +#define SP_DELTA (STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE) + +#define context_set(c, _pc, stack, size) \ + do { \ + (c)->pc = ((uintptr_t) _pc) - 8; \ + (c)->sp = ((uintptr_t) stack) + ALIGN_UP((size), \ + STACK_ALIGNMENT) - (STACK_BIAS + SP_DELTA); \ + (c)->fp = -STACK_BIAS; \ + } while (0) + +/* + * Save only registers that must be preserved across + * function calls. + */ +typedef struct { + uintptr_t sp; /* %o6 */ + uintptr_t pc; /* %o7 */ + uint64_t i0; + uint64_t i1; + uint64_t i2; + uint64_t i3; + uint64_t i4; + uint64_t i5; + uintptr_t fp; /* %i6 */ + uintptr_t i7; + uint64_t l0; + uint64_t l1; + uint64_t l2; + uint64_t l3; + uint64_t l4; + uint64_t l5; + uint64_t l6; + uint64_t l7; + ipl_t ipl; +} context_t; + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/context_offset.h =================================================================== --- kernel/arch/sparc64/include/arch/context_offset.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/context_offset.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef KERN_sparc64_CONTEXT_OFFSET_H_ +#define KERN_sparc64_CONTEXT_OFFSET_H_ + +#define OFFSET_SP 0x0 +#define OFFSET_PC 0x8 +#define OFFSET_I0 0x10 +#define OFFSET_I1 0x18 +#define OFFSET_I2 0x20 +#define OFFSET_I3 0x28 +#define OFFSET_I4 0x30 +#define OFFSET_I5 0x38 +#define OFFSET_FP 0x40 +#define OFFSET_I7 0x48 +#define OFFSET_L0 0x50 +#define OFFSET_L1 0x58 +#define OFFSET_L2 0x60 +#define OFFSET_L3 0x68 +#define OFFSET_L4 0x70 +#define OFFSET_L5 0x78 +#define OFFSET_L6 0x80 +#define OFFSET_L7 0x88 + +#ifndef KERNEL +# define OFFSET_TP 0x90 +#endif + +#ifdef __ASM__ + +.macro CONTEXT_SAVE_ARCH_CORE ctx:req + stx %sp, [\ctx + OFFSET_SP] + stx %o7, [\ctx + OFFSET_PC] + stx %i0, [\ctx + OFFSET_I0] + stx %i1, [\ctx + OFFSET_I1] + stx %i2, [\ctx + OFFSET_I2] + stx %i3, [\ctx + OFFSET_I3] + stx %i4, [\ctx + OFFSET_I4] + stx %i5, [\ctx + OFFSET_I5] + stx %fp, [\ctx + OFFSET_FP] + stx %i7, [\ctx + OFFSET_I7] + stx %l0, [\ctx + OFFSET_L0] + stx %l1, [\ctx + OFFSET_L1] + stx %l2, [\ctx + OFFSET_L2] + stx %l3, [\ctx + OFFSET_L3] + stx %l4, [\ctx + OFFSET_L4] + stx %l5, [\ctx + OFFSET_L5] + stx %l6, [\ctx + OFFSET_L6] + stx %l7, [\ctx + OFFSET_L7] +#ifndef KERNEL + stx %g7, [\ctx + OFFSET_TP] +#endif +.endm + +.macro CONTEXT_RESTORE_ARCH_CORE ctx:req + ldx [\ctx + OFFSET_SP], %sp + ldx [\ctx + OFFSET_PC], %o7 + ldx [\ctx + OFFSET_I0], %i0 + ldx [\ctx + OFFSET_I1], %i1 + ldx [\ctx + OFFSET_I2], %i2 + ldx [\ctx + OFFSET_I3], %i3 + ldx [\ctx + OFFSET_I4], %i4 + ldx [\ctx + OFFSET_I5], %i5 + ldx [\ctx + OFFSET_FP], %fp + ldx [\ctx + OFFSET_I7], %i7 + ldx [\ctx + OFFSET_L0], %l0 + ldx [\ctx + OFFSET_L1], %l1 + ldx [\ctx + OFFSET_L2], %l2 + ldx [\ctx + OFFSET_L3], %l3 + ldx [\ctx + OFFSET_L4], %l4 + ldx [\ctx + OFFSET_L5], %l5 + ldx [\ctx + OFFSET_L6], %l6 + ldx [\ctx + OFFSET_L7], %l7 +#ifndef KERNEL + ldx [\ctx + OFFSET_TP], %g7 +#endif +.endm + +#endif /* __ASM__ */ + +#endif Index: kernel/arch/sparc64/include/arch/cpu.h =================================================================== --- kernel/arch/sparc64/include/arch/cpu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/cpu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_CPU_H_ +#define KERN_sparc64_CPU_H_ + +#define MANUF_FUJITSU 0x04 +#define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */ +#define MANUF_SUN 0x3e + +#define IMPL_ULTRASPARCI 0x10 +#define IMPL_ULTRASPARCII 0x11 +#define IMPL_ULTRASPARCII_I 0x12 +#define IMPL_ULTRASPARCII_E 0x13 +#define IMPL_ULTRASPARCIII 0x14 +#define IMPL_ULTRASPARCIII_PLUS 0x15 +#define IMPL_ULTRASPARCIII_I 0x16 +#define IMPL_ULTRASPARCIV 0x18 +#define IMPL_ULTRASPARCIV_PLUS 0x19 + +#define IMPL_SPARC64V 0x5 + +#ifndef __ASM__ + +#include +#include +#include +#include + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + + +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/cpu_family.h =================================================================== --- kernel/arch/sparc64/include/arch/cpu_family.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/cpu_family.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2008 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_CPU_FAMILY_H_ +#define KERN_sparc64_CPU_FAMILY_H_ + +#include +#include +#include +#include + +/** + * Find the processor (sub)family. + * + * @return true iff the CPU belongs to the US family + */ +static inline bool is_us(void) +{ + int impl = ((ver_reg_t) ver_read()).impl; + return (impl == IMPL_ULTRASPARCI) || (impl == IMPL_ULTRASPARCII) || + (impl == IMPL_ULTRASPARCII_I) || (impl == IMPL_ULTRASPARCII_E); +} + +/** + * Find the processor (sub)family. + * + * @return true iff the CPU belongs to the US-III subfamily + */ +static inline bool is_us_iii(void) +{ + int impl = ((ver_reg_t) ver_read()).impl; + return (impl == IMPL_ULTRASPARCIII) || + (impl == IMPL_ULTRASPARCIII_PLUS) || + (impl == IMPL_ULTRASPARCIII_I); +} + +/** + * Find the processor (sub)family. + * + * @return true iff the CPU belongs to the US-IV subfamily + */ +static inline bool is_us_iv(void) +{ + int impl = ((ver_reg_t) ver_read()).impl; + return (impl == IMPL_ULTRASPARCIV) || (impl == IMPL_ULTRASPARCIV_PLUS); +} + +#endif + +/** @} + */ + Index: kernel/arch/sparc64/include/arch/cpu_node.h =================================================================== --- kernel/arch/sparc64/include/arch/cpu_node.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/cpu_node.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2005 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_CPU_NODE_H_ +#define KERN_sparc64_CPU_NODE_H_ + +#include + + +/** Finds the parent node of all the CPU nodes (nodes named "cpu" or "cmp"). + * + * Depending on the machine type (and possibly the OFW version), CPUs can be + * at "/" or at "/ssm@0,0". + */ +static inline ofw_tree_node_t *cpus_parent(void) +{ + ofw_tree_node_t *parent; + parent = ofw_tree_find_child(ofw_tree_lookup("/"), "ssm@0,0"); + if (parent == NULL) + parent = ofw_tree_lookup("/"); + return parent; +} + +#endif + +/** @} + */ + Index: kernel/arch/sparc64/include/arch/cycle.h =================================================================== --- kernel/arch/sparc64/include/arch/cycle.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/cycle.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_CYCLE_H_ +#define KERN_sparc64_CYCLE_H_ + +#include +#include + +NO_TRACE static inline uint64_t get_cycle(void) +{ + return tick_read(); +} + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/drivers/fb.h =================================================================== --- kernel/arch/sparc64/include/arch/drivers/fb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/drivers/fb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_FB_H_ +#define KERN_sparc64_FB_H_ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/drivers/kbd.h =================================================================== --- kernel/arch/sparc64/include/arch/drivers/kbd.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/drivers/kbd.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_KBD_H_ +#define KERN_sparc64_KBD_H_ + +#include +#include + +extern void kbd_init(ofw_tree_node_t *node); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/drivers/niagara.h =================================================================== --- kernel/arch/sparc64/include/arch/drivers/niagara.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/drivers/niagara.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2008 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_NIAGARA_H +#define KERN_sparc64_NIAGARA_H + +#include +#include + +typedef struct { + thread_t *thread; + indev_t *srlnin; +} niagara_instance_t; + +char niagara_getc(void); +void niagara_grab(void); +void niagara_release(void); +niagara_instance_t *niagarain_init(void); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/drivers/pci.h =================================================================== --- kernel/arch/sparc64/include/arch/drivers/pci.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/drivers/pci.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_PCI_H_ +#define KERN_sparc64_PCI_H_ + +#include +#include +#include +#include + +typedef enum pci_model pci_model_t; +typedef struct pci pci_t; +typedef struct pci_operations pci_operations_t; + +enum pci_model { + PCI_UNKNOWN, + PCI_SABRE, + PCI_PSYCHO +}; + +struct pci_operations { + void (* enable_interrupt)(pci_t *, int); + void (* clear_interrupt)(pci_t *, int); +}; + +struct pci { + pci_model_t model; + pci_operations_t *op; + volatile uint64_t *reg; /**< Registers including interrupt registers. */ +}; + +extern pci_t *pci_init(ofw_tree_node_t *); +extern void pci_enable_interrupt(pci_t *, int); +extern void pci_clear_interrupt(void *, int); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/drivers/scr.h =================================================================== --- kernel/arch/sparc64/include/arch/drivers/scr.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/drivers/scr.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_SCR_H_ +#define KERN_sparc64_SCR_H_ + +#include +#include + +typedef enum { + SCR_UNKNOWN, + SCR_ATYFB, + SCR_FFB, + SCR_CGSIX, + SCR_XVR, + SCR_QEMU_VGA +} scr_type_t; + +extern scr_type_t scr_type; + +extern void scr_init(ofw_tree_node_t *node); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/drivers/tick.h =================================================================== --- kernel/arch/sparc64/include/arch/drivers/tick.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/drivers/tick.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TICK_H_ +#define KERN_sparc64_TICK_H_ + +#include +#include + +/* mask of the "counter" field of the Tick register */ +#define TICK_COUNTER_MASK (~(1l << 63)) + +extern void tick_init(void); +extern void tick_interrupt(unsigned int, istate_t *); + +/** + * Reads the Tick register counter. + */ +static inline uint64_t tick_counter_read(void) +{ + return TICK_COUNTER_MASK & tick_read(); +} + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/elf.h =================================================================== --- kernel/arch/sparc64/include/arch/elf.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/elf.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006 Sergey Bondari + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_ELF_H_ +#define KERN_sparc64_ELF_H_ + +#define ELF_MACHINE EM_SPARCV9 +#define ELF_DATA_ENCODING ELFDATA2MSB +#define ELF_CLASS ELFCLASS64 + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/faddr.h =================================================================== --- kernel/arch/sparc64/include/arch/faddr.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/faddr.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_FADDR_H_ +#define KERN_sparc64_FADDR_H_ + +#include + +#define FADDR(fptr) ((uintptr_t) (fptr)) + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/fpu_context.h =================================================================== --- kernel/arch/sparc64/include/arch/fpu_context.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/fpu_context.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_FPU_CONTEXT_H_ +#define KERN_sparc64_FPU_CONTEXT_H_ + +#include + +#define FPU_CONTEXT_ALIGN 8 + +typedef struct { + uint64_t d[32]; + uint64_t fsr; +} fpu_context_t; + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/interrupt.h =================================================================== --- kernel/arch/sparc64/include/arch/interrupt.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/interrupt.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt sparc64 + * @ingroup interrupt + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_INTERRUPT_H_ +#define KERN_sparc64_INTERRUPT_H_ + +#include +#include + +#define IVT_ITEMS 15 +#define IVT_FIRST 1 + +/* This needs to be defined for inter-architecture API portability. */ +#define VECTOR_TLB_SHOOTDOWN_IPI 0 + +enum { + IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI +}; + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/istate.h =================================================================== --- kernel/arch/sparc64/include/arch/istate.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/istate.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt sparc64 + * @ingroup interrupt + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_ISTATE_H_ +#define KERN_sparc64_ISTATE_H_ + +#include + +#ifdef KERNEL + +#include + +#else /* KERNEL */ + +#include + +#endif /* KERNEL */ + +typedef struct istate { + uint64_t tnpc; + uint64_t tpc; + uint64_t tstate; +} istate_t; + +NO_TRACE static inline void istate_set_retaddr(istate_t *istate, + uintptr_t retaddr) +{ + istate->tpc = retaddr; +} + +NO_TRACE static inline int istate_from_uspace(istate_t *istate) +{ + return !(istate->tstate & TSTATE_PRIV_BIT); +} + +NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate) +{ + return istate->tpc; +} + +NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate) +{ + /* TODO */ + return 0; +} + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/as.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/as.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/as.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_AS_H_ +#define KERN_sparc64_AS_H_ + +#if defined (SUN4U) + +#include + +#elif defined (SUN4V) + +#include + +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/asid.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/asid.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/asid.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_ASID_H_ +#define KERN_sparc64_ASID_H_ + +#include + +/* + * On SPARC, Context means the same thing as ASID trough out the kernel. + */ +typedef uint16_t asid_t; + +#define ASID_MAX_ARCH 8191 /* 2^13 - 1 */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/cache_spec.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/cache_spec.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/cache_spec.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2008 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_CACHE_SPEC_H_ +#define KERN_sparc64_CACHE_SPEC_H_ + +/* + * The following macros are valid for the following processors: + * + * UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III, + * UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+ + * + * Should we support other UltraSPARC processors, we need to make sure that + * the macros are defined correctly for them. + */ + +#if defined (US) + #define DCACHE_SIZE (16 * 1024) +#elif defined (US3) + #define DCACHE_SIZE (64 * 1024) +#endif + +#define DCACHE_LINE_SIZE 32 +#define DCACHE_TAG_SHIFT 2 + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/frame.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/frame.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/frame.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_FRAME_H_ +#define KERN_sparc64_FRAME_H_ + +#if defined (SUN4U) + +#include + +#elif defined (SUN4V) + +#include + +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/km.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/km.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/km.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2011 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_KM_H_ +#define KERN_sparc64_KM_H_ + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/mmu.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/mmu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/mmu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_MMU_H_ +#define KERN_sparc64_MMU_H_ + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/page.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/page.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/page.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_PAGE_H_ +#define KERN_sparc64_PAGE_H_ + +#include + +/* + * On the TLB and TSB level, we still use 8K pages, which are supported by the + * MMU. + */ +#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH +#define MMU_PAGE_SIZE MMU_FRAME_SIZE + +/* + * On the page table level, we use 16K pages. 16K pages are not supported by + * the MMU but we emulate them with pairs of 8K pages. + */ +#define PAGE_WIDTH FRAME_WIDTH +#define PAGE_SIZE FRAME_SIZE + +#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) + +#ifndef __ASM__ + +#include + +extern uintptr_t physmem_base; + +#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) +#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) + +typedef union { + uintptr_t address; + struct { + uint64_t vpn : 51; /**< Virtual Page Number. */ + unsigned offset : 13; /**< Offset. */ + } __attribute__ ((packed)); +} page_address_t; + +extern void page_arch_init(void); + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/pagesize.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/pagesize.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/pagesize.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * Copyright (c) 2008 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_PAGESIZE_H +#define KERN_sparc64_PAGESIZE_H + +/** Page sizes. */ +#define PAGESIZE_8K 0 +#define PAGESIZE_64K 1 +#define PAGESIZE_512K 2 +#define PAGESIZE_4M 3 + +#endif Index: kernel/arch/sparc64/include/arch/mm/sun4u/as.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4u/as.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4u/as.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_AS_H_ +#define KERN_sparc64_sun4u_AS_H_ + +#include + +#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1 + +#define KERNEL_ADDRESS_SPACE_START_ARCH UINT64_C(0x0000000000000000) +#define KERNEL_ADDRESS_SPACE_END_ARCH UINT64_C(0xffffffffffffffff) +#define USER_ADDRESS_SPACE_START_ARCH UINT64_C(0x0000000000000000) +#define USER_ADDRESS_SPACE_END_ARCH UINT64_C(0xffffffffffffffff) + +#ifdef CONFIG_TSB + +/** TSB Tag Target register. */ +typedef union tsb_tag_target { + uint64_t value; + struct { + unsigned invalid : 1; /**< Invalidated by software. */ + unsigned : 2; + unsigned context : 13; /**< Software ASID. */ + unsigned : 6; + uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ + } __attribute__ ((packed)); +} tsb_tag_target_t; + +/** TSB entry. */ +typedef struct tsb_entry { + tsb_tag_target_t tag; + tte_data_t data; +} __attribute__ ((packed)) tsb_entry_t; + +typedef struct { + tsb_entry_t *itsb; + tsb_entry_t *dtsb; +} as_arch_t; + +#else + +typedef struct { +} as_arch_t; + +#endif /* CONFIG_TSB */ + +#include + +#ifdef CONFIG_TSB +#include +#define as_invalidate_translation_cache(as, page, cnt) \ + tsb_invalidate((as), (page), (cnt)) +#else +#define as_invalidate_translation_cache(as, page, cnt) +#endif + +extern void as_arch_init(void); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4u/frame.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4u/frame.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4u/frame.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_SUN4U_FRAME_H_ +#define KERN_sparc64_SUN4U_FRAME_H_ + +/* + * Page size supported by the MMU. + * For 8K there is the nasty illegal virtual aliasing problem. + * Therefore, the kernel uses 8K only internally on the TLB and TSB levels. + */ +#define MMU_FRAME_WIDTH 13 /* 8K */ +#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) + +/* + * Page size exported to the generic memory management subsystems. + * This page size is not directly supported by the MMU, but we can emulate + * each 16K page with a pair of adjacent 8K pages. + */ +#define FRAME_WIDTH 14 /* 16K */ +#define FRAME_SIZE (1 << FRAME_WIDTH) + +#ifndef __ASM__ + +#include + +union frame_address { + uintptr_t address; + struct { +#if defined (US) + unsigned : 23; + uint64_t pfn : 28; /**< Physical Frame Number. */ +#elif defined (US3) + unsigned : 21; + uint64_t pfn : 30; /**< Physical Frame Number. */ +#endif + unsigned offset : 13; /**< Offset. */ + } __attribute__ ((packed)); +}; + +typedef union frame_address frame_address_t; + +extern uintptr_t end_of_identity; + +extern void frame_low_arch_init(void); +extern void frame_high_arch_init(void); +#define physmem_print() + +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4u/km.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4u/km.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4u/km.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2011 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_KM_H_ +#define KERN_sparc64_sun4u_KM_H_ + +#include + +/* + * Be conservative and assume the 44-bit virtual address width as found + * on the UltraSPARC CPU, even when running on a newer CPU, such as + * UltraSPARC III, which has the full 64-bit virtual address width. + * + * Do not use the 4 GiB area on either side of the VA hole to meet the + * limitations of the UltraSPARC CPU. + */ + +#define KM_SPARC64_US_IDENTITY_START UINT64_C(0x0000000000000000) +#define KM_SPARC64_US_IDENTITY_SIZE UINT64_C(0x000007ff00000000) + +#define KM_SPARC64_US_NON_IDENTITY_START UINT64_C(0xfffff80100000000) +#define KM_SPARC64_US_NON_IDENTITY_SIZE UINT64_C(0x000007ff00000000) + +extern void km_identity_arch_init(void); +extern void km_non_identity_arch_init(void); +extern bool km_is_non_identity_arch(uintptr_t); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4u/mmu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_MMU_H_ +#define KERN_sparc64_sun4u_MMU_H_ + +#if defined(US) +/* LSU Control Register ASI. */ +#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ +#endif + +/* I-MMU ASIs. */ +#define ASI_IMMU 0x50 +#define ASI_IMMU_TSB_8KB_PTR_REG 0x51 +#define ASI_IMMU_TSB_64KB_PTR_REG 0x52 +#define ASI_ITLB_DATA_IN_REG 0x54 +#define ASI_ITLB_DATA_ACCESS_REG 0x55 +#define ASI_ITLB_TAG_READ_REG 0x56 +#define ASI_IMMU_DEMAP 0x57 + +/* Virtual Addresses within ASI_IMMU. */ +#define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ +#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ +#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ +#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ +#if defined (US3) +#define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */ +#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ +#endif + + +/* D-MMU ASIs. */ +#define ASI_DMMU 0x58 +#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 +#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a +#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b +#define ASI_DTLB_DATA_IN_REG 0x5c +#define ASI_DTLB_DATA_ACCESS_REG 0x5d +#define ASI_DTLB_TAG_READ_REG 0x5e +#define ASI_DMMU_DEMAP 0x5f + +/* Virtual Addresses within ASI_DMMU. */ +#define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ +#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ +#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ +#define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ +#define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ +#define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ +#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ +#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ +#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ +#if defined (US3) +#define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */ +#define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */ +#define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */ +#endif + +#ifndef __ASM__ + +#include +#include +#include + +#if defined(US) +/** LSU Control Register. */ +typedef union { + uint64_t value; + struct { + unsigned : 23; + unsigned pm : 8; + unsigned vm : 8; + unsigned pr : 1; + unsigned pw : 1; + unsigned vr : 1; + unsigned vw : 1; + unsigned : 1; + unsigned fm : 16; + unsigned dm : 1; /**< D-MMU enable. */ + unsigned im : 1; /**< I-MMU enable. */ + unsigned dc : 1; /**< D-Cache enable. */ + unsigned ic : 1; /**< I-Cache enable. */ + + } __attribute__ ((packed)); +} lsu_cr_reg_t; +#endif /* US */ + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4u/tlb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,694 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TLB_sun4u_H_ +#define KERN_sparc64_TLB_sun4u_H_ + +#if defined (US) +#define ITLB_ENTRY_COUNT 64 +#define DTLB_ENTRY_COUNT 64 +#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT +#endif + +/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ +#if defined (US3) +#define DTLB_MAX_LOCKED_ENTRIES 16 +#endif + +#define MEM_CONTEXT_KERNEL 0 +#define MEM_CONTEXT_TEMP 1 + +/** Page sizes. */ +#define PAGESIZE_8K 0 +#define PAGESIZE_64K 1 +#define PAGESIZE_512K 2 +#define PAGESIZE_4M 3 + +/** Bit width of the TLB-locked portion of kernel address space. */ +#define KERNEL_PAGE_WIDTH 22 /* 4M */ + +/* TLB Demap Operation types. */ +#define TLB_DEMAP_PAGE 0 +#define TLB_DEMAP_CONTEXT 1 +#if defined (US3) +#define TLB_DEMAP_ALL 2 +#endif + +#define TLB_DEMAP_TYPE_SHIFT 6 + +/* TLB Demap Operation Context register encodings. */ +#define TLB_DEMAP_PRIMARY 0 +#define TLB_DEMAP_SECONDARY 1 +#define TLB_DEMAP_NUCLEUS 2 + +/* There are more TLBs in one MMU in US3, their codes are defined here. */ +#if defined (US3) +/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */ +#define TLB_DSMALL 0 +#define TLB_DBIG_0 2 +#define TLB_DBIG_1 3 + +/* I-MMU: one small (16-entry) TLB and one big TLB */ +#define TLB_ISMALL 0 +#define TLB_IBIG 2 +#endif + +#define TLB_DEMAP_CONTEXT_SHIFT 4 + +/* TLB Tag Access shifts */ +#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 +#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) +#define TLB_TAG_ACCESS_VPN_SHIFT 13 + +#ifndef __ASM__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +union tlb_context_reg { + uint64_t v; + struct { + unsigned long : 51; + unsigned context : 13; /**< Context/ASID. */ + } __attribute__ ((packed)); +}; +typedef union tlb_context_reg tlb_context_reg_t; + +/** I-/D-TLB Data In/Access Register type. */ +typedef tte_data_t tlb_data_t; + +/** I-/D-TLB Data Access Address in Alternate Space. */ + +#if defined (US) + +union tlb_data_access_addr { + uint64_t value; + struct { + uint64_t : 55; + unsigned tlb_entry : 6; + unsigned : 3; + } __attribute__ ((packed)); +}; +typedef union tlb_data_access_addr dtlb_data_access_addr_t; +typedef union tlb_data_access_addr dtlb_tag_read_addr_t; +typedef union tlb_data_access_addr itlb_data_access_addr_t; +typedef union tlb_data_access_addr itlb_tag_read_addr_t; + +#elif defined (US3) + +/* + * In US3, I-MMU and D-MMU have different formats of the data + * access register virtual address. In the corresponding + * structures the member variable for the entry number is + * called "local_tlb_entry" - it contrasts with the "tlb_entry" + * for the US data access register VA structure. The rationale + * behind this is to prevent careless mistakes in the code + * caused by setting only the entry number and not the TLB + * number in the US3 code (when taking the code from US). + */ + +union dtlb_data_access_addr { + uint64_t value; + struct { + uint64_t : 45; + unsigned : 1; + unsigned tlb_number : 2; + unsigned : 4; + unsigned local_tlb_entry : 9; + unsigned : 3; + } __attribute__ ((packed)); +}; +typedef union dtlb_data_access_addr dtlb_data_access_addr_t; +typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; + +union itlb_data_access_addr { + uint64_t value; + struct { + uint64_t : 45; + unsigned : 1; + unsigned tlb_number : 2; + unsigned : 6; + unsigned local_tlb_entry : 7; + unsigned : 3; + } __attribute__ ((packed)); +}; +typedef union itlb_data_access_addr itlb_data_access_addr_t; +typedef union itlb_data_access_addr itlb_tag_read_addr_t; + +#endif + +/** I-/D-TLB Tag Read Register. */ +union tlb_tag_read_reg { + uint64_t value; + struct { + uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ + unsigned context : 13; /**< Context identifier. */ + } __attribute__ ((packed)); +}; +typedef union tlb_tag_read_reg tlb_tag_read_reg_t; +typedef union tlb_tag_read_reg tlb_tag_access_reg_t; + + +/** TLB Demap Operation Address. */ +union tlb_demap_addr { + uint64_t value; + struct { + uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ +#if defined (US) + unsigned : 6; /**< Ignored. */ + unsigned type : 1; /**< The type of demap operation. */ +#elif defined (US3) + unsigned : 5; /**< Ignored. */ + unsigned type: 2; /**< The type of demap operation. */ +#endif + unsigned context : 2; /**< Context register selection. */ + unsigned : 4; /**< Zero. */ + } __attribute__ ((packed)); +}; +typedef union tlb_demap_addr tlb_demap_addr_t; + +/** TLB Synchronous Fault Status Register. */ +union tlb_sfsr_reg { + uint64_t value; + struct { +#if defined (US) + unsigned long : 40; /**< Implementation dependent. */ + unsigned asi : 8; /**< ASI. */ + unsigned : 2; + unsigned ft : 7; /**< Fault type. */ +#elif defined (US3) + unsigned long : 39; /**< Implementation dependent. */ + unsigned nf : 1; /**< Non-faulting load. */ + unsigned asi : 8; /**< ASI. */ + unsigned tm : 1; /**< I-TLB miss. */ + unsigned : 3; /**< Reserved. */ + unsigned ft : 5; /**< Fault type. */ +#endif + unsigned e : 1; /**< Side-effect bit. */ + unsigned ct : 2; /**< Context Register selection. */ + unsigned pr : 1; /**< Privilege bit. */ + unsigned w : 1; /**< Write bit. */ + unsigned ow : 1; /**< Overwrite bit. */ + unsigned fv : 1; /**< Fault Valid bit. */ + } __attribute__ ((packed)); +}; +typedef union tlb_sfsr_reg tlb_sfsr_reg_t; + +#if defined (US3) + +/* + * Functions for determining the number of entries in TLBs. They either return + * a constant value or a value based on the CPU autodetection. + */ + +/** + * Determine the number of entries in the DMMU's small TLB. + */ +NO_TRACE static inline uint16_t tlb_dsmall_size(void) +{ + return 16; +} + +/** + * Determine the number of entries in each DMMU's big TLB. + */ +NO_TRACE static inline uint16_t tlb_dbig_size(void) +{ + return 512; +} + +/** + * Determine the number of entries in the IMMU's small TLB. + */ +NO_TRACE static inline uint16_t tlb_ismall_size(void) +{ + return 16; +} + +/** + * Determine the number of entries in the IMMU's big TLB. + */ +NO_TRACE static inline uint16_t tlb_ibig_size(void) +{ + if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) + return 512; + else + return 128; +} + +#endif + +/** Read MMU Primary Context Register. + * + * @return Current value of Primary Context Register. + */ +NO_TRACE static inline uint64_t mmu_primary_context_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); +} + +/** Write MMU Primary Context Register. + * + * @param v New value of Primary Context Register. + */ +NO_TRACE static inline void mmu_primary_context_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); + flush_pipeline(); +} + +/** Read MMU Secondary Context Register. + * + * @return Current value of Secondary Context Register. + */ +NO_TRACE static inline uint64_t mmu_secondary_context_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); +} + +/** Write MMU Primary Context Register. + * + * @param v New value of Primary Context Register. + */ +NO_TRACE static inline void mmu_secondary_context_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); + flush_pipeline(); +} + +#if defined (US) + +/** Read IMMU TLB Data Access Register. + * + * @param entry TLB Entry index. + * + * @return Current value of specified IMMU TLB Data Access + * Register. + */ +NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry) +{ + itlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_entry = entry; + return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); +} + +/** Write IMMU TLB Data Access Register. + * + * @param entry TLB Entry index. + * @param value Value to be written. + */ +NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value) +{ + itlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_entry = entry; + asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); + flush_pipeline(); +} + +/** Read DMMU TLB Data Access Register. + * + * @param entry TLB Entry index. + * + * @return Current value of specified DMMU TLB Data Access + * Register. + */ +NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry) +{ + dtlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_entry = entry; + return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); +} + +/** Write DMMU TLB Data Access Register. + * + * @param entry TLB Entry index. + * @param value Value to be written. + */ +NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value) +{ + dtlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_entry = entry; + asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); + membar(); +} + +/** Read IMMU TLB Tag Read Register. + * + * @param entry TLB Entry index. + * + * @return Current value of specified IMMU TLB Tag Read Register. + */ +NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry) +{ + itlb_tag_read_addr_t tag; + + tag.value = 0; + tag.tlb_entry = entry; + return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); +} + +/** Read DMMU TLB Tag Read Register. + * + * @param entry TLB Entry index. + * + * @return Current value of specified DMMU TLB Tag Read Register. + */ +NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry) +{ + dtlb_tag_read_addr_t tag; + + tag.value = 0; + tag.tlb_entry = entry; + return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); +} + +#elif defined (US3) + + +/** Read IMMU TLB Data Access Register. + * + * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) + * @param entry TLB Entry index. + * + * @return Current value of specified IMMU TLB Data Access + * Register. + */ +NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry) +{ + itlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_number = tlb; + reg.local_tlb_entry = entry; + return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); +} + +/** Write IMMU TLB Data Access Register. + * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) + * @param entry TLB Entry index. + * @param value Value to be written. + */ +NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry, + uint64_t value) +{ + itlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_number = tlb; + reg.local_tlb_entry = entry; + asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); + flush_pipeline(); +} + +/** Read DMMU TLB Data Access Register. + * + * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) + * @param entry TLB Entry index. + * + * @return Current value of specified DMMU TLB Data Access + * Register. + */ +NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry) +{ + dtlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_number = tlb; + reg.local_tlb_entry = entry; + return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); +} + +/** Write DMMU TLB Data Access Register. + * + * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) + * @param entry TLB Entry index. + * @param value Value to be written. + */ +NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry, + uint64_t value) +{ + dtlb_data_access_addr_t reg; + + reg.value = 0; + reg.tlb_number = tlb; + reg.local_tlb_entry = entry; + asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); + membar(); +} + +/** Read IMMU TLB Tag Read Register. + * + * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) + * @param entry TLB Entry index. + * + * @return Current value of specified IMMU TLB Tag Read Register. + */ +NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry) +{ + itlb_tag_read_addr_t tag; + + tag.value = 0; + tag.tlb_number = tlb; + tag.local_tlb_entry = entry; + return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); +} + +/** Read DMMU TLB Tag Read Register. + * + * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) + * @param entry TLB Entry index. + * + * @return Current value of specified DMMU TLB Tag Read Register. + */ +NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry) +{ + dtlb_tag_read_addr_t tag; + + tag.value = 0; + tag.tlb_number = tlb; + tag.local_tlb_entry = entry; + return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); +} + +#endif + + +/** Write IMMU TLB Tag Access Register. + * + * @param v Value to be written. + */ +NO_TRACE static inline void itlb_tag_access_write(uint64_t v) +{ + asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); + flush_pipeline(); +} + +/** Read IMMU TLB Tag Access Register. + * + * @return Current value of IMMU TLB Tag Access Register. + */ +NO_TRACE static inline uint64_t itlb_tag_access_read(void) +{ + return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); +} + +/** Write DMMU TLB Tag Access Register. + * + * @param v Value to be written. + */ +NO_TRACE static inline void dtlb_tag_access_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); + membar(); +} + +/** Read DMMU TLB Tag Access Register. + * + * @return Current value of DMMU TLB Tag Access Register. + */ +NO_TRACE static inline uint64_t dtlb_tag_access_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); +} + + +/** Write IMMU TLB Data in Register. + * + * @param v Value to be written. + */ +NO_TRACE static inline void itlb_data_in_write(uint64_t v) +{ + asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); + flush_pipeline(); +} + +/** Write DMMU TLB Data in Register. + * + * @param v Value to be written. + */ +NO_TRACE static inline void dtlb_data_in_write(uint64_t v) +{ + asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); + membar(); +} + +/** Read ITLB Synchronous Fault Status Register. + * + * @return Current content of I-SFSR register. + */ +NO_TRACE static inline uint64_t itlb_sfsr_read(void) +{ + return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); +} + +/** Write ITLB Synchronous Fault Status Register. + * + * @param v New value of I-SFSR register. + */ +NO_TRACE static inline void itlb_sfsr_write(uint64_t v) +{ + asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); + flush_pipeline(); +} + +/** Read DTLB Synchronous Fault Status Register. + * + * @return Current content of D-SFSR register. + */ +NO_TRACE static inline uint64_t dtlb_sfsr_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); +} + +/** Write DTLB Synchronous Fault Status Register. + * + * @param v New value of D-SFSR register. + */ +NO_TRACE static inline void dtlb_sfsr_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); + membar(); +} + +/** Read DTLB Synchronous Fault Address Register. + * + * @return Current content of D-SFAR register. + */ +NO_TRACE static inline uint64_t dtlb_sfar_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); +} + +/** Perform IMMU TLB Demap Operation. + * + * @param type Selects between context and page demap (and entire MMU + * demap on US3). + * @param context_encoding Specifies which Context register has Context ID for + * demap. + * @param page Address which is on the page to be demapped. + */ +NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page) +{ + tlb_demap_addr_t da; + page_address_t pg; + + da.value = 0; + pg.address = page; + + da.type = type; + da.context = context_encoding; + da.vpn = pg.vpn; + + /* da.value is the address within the ASI */ + asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); + + flush_pipeline(); +} + +/** Perform DMMU TLB Demap Operation. + * + * @param type Selects between context and page demap (and entire MMU + * demap on US3). + * @param context_encoding Specifies which Context register has Context ID for + * demap. + * @param page Address which is on the page to be demapped. + */ +NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) +{ + tlb_demap_addr_t da; + page_address_t pg; + + da.value = 0; + pg.address = page; + + da.type = type; + da.context = context_encoding; + da.vpn = pg.vpn; + + /* da.value is the address within the ASI */ + asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); + + membar(); +} + +extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *); +extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *); +extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *); + +extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); + +extern void dump_sfsr_and_sfar(void); +extern void describe_dmmu_fault(void); + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4u/tsb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_TSB_H_ +#define KERN_sparc64_sun4u_TSB_H_ + +/* + * ITSB abd DTSB will claim 64K of memory, which + * is a nice number considered that it is one of + * the page sizes supported by hardware, which, + * again, is nice because TSBs need to be locked + * in TLBs - only one TLB entry will do. + */ +#define TSB_SIZE 2 /* when changing this, change + * as.c as well */ +#define ITSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) +#define DTSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) + +#define TSB_TAG_TARGET_CONTEXT_SHIFT 48 + +#ifndef __ASM__ + +#include +#include +#include + +/** TSB Base register. */ +typedef union tsb_base_reg { + uint64_t value; + struct { + uint64_t base : 51; /**< TSB base address, bits 63:13. */ + unsigned split : 1; /**< Split vs. common TSB for 8K and 64K + * pages. HelenOS uses only 8K pages + * for user mappings, so we always set + * this to 0. + */ + unsigned : 9; + unsigned size : 3; /**< TSB size. Number of entries is + * 512 * 2^size. */ + } __attribute__ ((packed)); +} tsb_base_reg_t; + +/** Read ITSB Base register. + * + * @return Content of the ITSB Base register. + */ +static inline uint64_t itsb_base_read(void) +{ + return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE); +} + +/** Read DTSB Base register. + * + * @return Content of the DTSB Base register. + */ +static inline uint64_t dtsb_base_read(void) +{ + return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE); +} + +/** Write ITSB Base register. + * + * @param v New content of the ITSB Base register. + */ +static inline void itsb_base_write(uint64_t v) +{ + asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v); +} + +/** Write DTSB Base register. + * + * @param v New content of the DTSB Base register. + */ +static inline void dtsb_base_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v); +} + +#if defined (US3) + +/** Write DTSB Primary Extension register. + * + * @param v New content of the DTSB Primary Extension register. + */ +static inline void dtsb_primary_extension_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v); +} + +/** Write DTSB Secondary Extension register. + * + * @param v New content of the DTSB Secondary Extension register. + */ +static inline void dtsb_secondary_extension_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v); +} + +/** Write DTSB Nucleus Extension register. + * + * @param v New content of the DTSB Nucleus Extension register. + */ +static inline void dtsb_nucleus_extension_write(uint64_t v) +{ + asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v); +} + +/** Write ITSB Primary Extension register. + * + * @param v New content of the ITSB Primary Extension register. + */ +static inline void itsb_primary_extension_write(uint64_t v) +{ + asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v); +} + +/** Write ITSB Nucleus Extension register. + * + * @param v New content of the ITSB Nucleus Extension register. + */ +static inline void itsb_nucleus_extension_write(uint64_t v) +{ + asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v); +} + +#endif + +/* Forward declarations. */ +struct as; +struct pte; + +extern void tsb_invalidate(struct as *as, uintptr_t page, size_t pages); +extern void itsb_pte_copy(struct pte *t, size_t index); +extern void dtsb_pte_copy(struct pte *t, size_t index, bool ro); + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4u/tte.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4u/tte.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4u/tte.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_TTE_H_ +#define KERN_sparc64_sun4u_TTE_H_ + +#define TTE_G (1 << 0) +#define TTE_W (1 << 1) +#define TTE_P (1 << 2) +#define TTE_E (1 << 3) +#define TTE_CV (1 << 4) +#define TTE_CP (1 << 5) +#define TTE_L (1 << 6) + +#define TTE_V_SHIFT 63 +#define TTE_SIZE_SHIFT 61 + +#ifndef __ASM__ + +#include + +/* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */ +#define VA_TAG_PAGE_SHIFT 22 + +/** Translation Table Entry - Tag. */ +union tte_tag { + uint64_t value; + struct { + unsigned g : 1; /**< Global. */ + unsigned : 2; /**< Reserved. */ + unsigned context : 13; /**< Context identifier. */ + unsigned : 6; /**< Reserved. */ + uint64_t va_tag : 42; /**< Virtual Address Tag, bits 63:22. */ + } __attribute__ ((packed)); +}; + +typedef union tte_tag tte_tag_t; + +/** Translation Table Entry - Data. */ +union tte_data { + uint64_t value; + struct { + unsigned v : 1; /**< Valid. */ + unsigned size : 2; /**< Page size of this entry. */ + unsigned nfo : 1; /**< No-Fault-Only. */ + unsigned ie : 1; /**< Invert Endianness. */ + unsigned soft2 : 9; /**< Software defined field. */ +#if defined (US) + unsigned diag : 9; /**< Diagnostic data. */ + unsigned pfn : 28; /**< Physical Address bits, bits 40:13. */ +#elif defined (US3) + unsigned : 7; /**< Reserved. */ + unsigned pfn : 30; /**< Physical Address bits, bits 42:13 */ +#endif + unsigned soft : 6; /**< Software defined field. */ + unsigned l : 1; /**< Lock. */ + unsigned cp : 1; /**< Cacheable in physically indexed cache. */ + unsigned cv : 1; /**< Cacheable in virtually indexed cache. */ + unsigned e : 1; /**< Side-effect. */ + unsigned p : 1; /**< Privileged. */ + unsigned w : 1; /**< Writable. */ + unsigned g : 1; /**< Global. */ + } __attribute__ ((packed)); +}; + +typedef union tte_data tte_data_t; + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4v/as.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4v/as.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4v/as.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * Copyright (c) 2009 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_AS_H_ +#define KERN_sparc64_sun4v_AS_H_ + +#include +#include + +#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1 + +#define KERNEL_ADDRESS_SPACE_START_ARCH UINT64_C(0x0000000000000000) +#define KERNEL_ADDRESS_SPACE_END_ARCH UINT64_C(0xffffffffffffffff) +#define USER_ADDRESS_SPACE_START_ARCH UINT64_C(0x0000000000000000) +#define USER_ADDRESS_SPACE_END_ARCH UINT64_C(0xffffffffffffffff) + +#ifdef CONFIG_TSB + +/** + * TTE Tag. + * + * Even though for sun4v the format of the TSB Tag states that the context + * field has 16 bits, the T1 CPU still only supports 13-bit contexts and the + * three most significant bits are always zero. + */ +typedef union tte_tag { + uint64_t value; + struct { + unsigned : 3; + unsigned context : 13; /**< Software ASID. */ + unsigned : 6; + uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ + } __attribute__ ((packed)); +} tte_tag_t; + +/** TSB entry. */ +typedef struct tsb_entry { + tte_tag_t tag; + tte_data_t data; +} __attribute__ ((packed)) tsb_entry_t; + +typedef struct { + tsb_descr_t tsb_description; +} as_arch_t; + +#else + +typedef struct { +} as_arch_t; + +#endif /* CONFIG_TSB */ + +#include + +#ifdef CONFIG_TSB +#include +#define as_invalidate_translation_cache(as, page, cnt) \ + tsb_invalidate((as), (page), (cnt)) +#else +#define as_invalidate_translation_cache(as, page, cnt) +#endif + +extern void as_arch_init(void); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4v/frame.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4v/frame.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4v/frame.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_FRAME_H_ +#define KERN_sparc64_sun4v_FRAME_H_ + +#define MMU_FRAME_WIDTH 13 /* 8K */ +#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) + +#define FRAME_WIDTH 13 +#define FRAME_SIZE (1 << FRAME_WIDTH) + +#ifndef __ASM__ + +#include + +extern void frame_low_arch_init(void); +extern void frame_high_arch_init(void); +#define physmem_print() + +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4v/km.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4v/km.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4v/km.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2011 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_KM_H_ +#define KERN_sparc64_sun4v_KM_H_ + +#include + +/* + * Do not use the 4 GiB area on either side of the VA hole to meet the + * limitations of the UltraSPARC T1 CPU. + */ + +#define KM_SPARC64_T1_IDENTITY_START UINT64_C(0x0000000000000000) +#define KM_SPARC64_T1_IDENTITY_SIZE UINT64_C(0x00007fff00000000) + +#define KM_SPARC64_T1_NON_IDENTITY_START UINT64_C(0xffff800100000000) +#define KM_SPARC64_T1_NON_IDENTITY_SIZE UINT64_C(0x00007fff00000000) + +extern void km_identity_arch_init(void); +extern void km_non_identity_arch_init(void); +extern bool km_is_non_identity_arch(uintptr_t); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4v/mmu.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4v/mmu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4v/mmu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * Copyright (c) 2008 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_MMU_H_ +#define KERN_sparc64_sun4v_MMU_H_ + +#define ASI_REAL 0x14 /**< MMU bypass ASI */ + +#define VA_PRIMARY_CONTEXT_REG 0x8 /**< primary context register VA. */ +#define ASI_PRIMARY_CONTEXT_REG 0x21 /**< primary context register ASI. */ + +#define VA_SECONDARY_CONTEXT_REG 0x10 /**< secondary context register VA. */ +#define ASI_SECONDARY_CONTEXT_REG 0x21 /**< secondary context register ASI. */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4v/page.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4v/page.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4v/page.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_PAGE_H_ +#define KERN_sparc64_sun4v_PAGE_H_ + +#include + +#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH +#define MMU_PAGE_SIZE MMU_FRAME_SIZE + +#define PAGE_WIDTH FRAME_WIDTH +#define PAGE_SIZE FRAME_SIZE + +#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) + +#ifndef __ASM__ + +#include + +extern uintptr_t physmem_base; + +#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) +#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) + +typedef union { + uintptr_t address; + struct { + uint64_t vpn : 51; /**< Virtual Page Number. */ + unsigned offset : 13; /**< Offset. */ + } __attribute__ ((packed)); +} page_address_t; + +extern void page_arch_init(void); + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4v/tlb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * Copyright (c) 2008 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_TLB_H_ +#define KERN_sparc64_sun4v_TLB_H_ + +#define MMU_FSA_ALIGNMENT 64 +#define MMU_FSA_SIZE 128 + +#ifndef __ASM__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * Structure filled by hypervisor (or directly CPU, if implemented so) when + * a MMU fault occurs. The structure describes the exact condition which + * has caused the fault. + */ +typedef struct mmu_fault_status_area { + uint64_t ift; /**< Instruction fault type (IFT) */ + uint64_t ifa; /**< Instruction fault address (IFA) */ + uint64_t ifc; /**< Instruction fault context (IFC) */ + uint8_t reserved1[0x28]; + + uint64_t dft; /**< Data fault type (DFT) */ + uint64_t dfa; /**< Data fault address (DFA) */ + uint64_t dfc; /**< Data fault context (DFC) */ + uint8_t reserved2[0x28]; +} __attribute__ ((packed)) mmu_fault_status_area_t; + +#define DTLB_MAX_LOCKED_ENTRIES 8 + +/** Bit width of the TLB-locked portion of kernel address space. */ +#define KERNEL_PAGE_WIDTH 22 /* 4M */ + +/* + * Reading and writing context registers. + * + * Note that UltraSPARC Architecture-compatible processors do not require + * a MEMBAR #Sync, FLUSH, DONE, or RETRY instruction after a store to an + * MMU register for proper operation. + * + */ + +/** Read MMU Primary Context Register. + * + * @return Current value of Primary Context Register. + */ +NO_TRACE static inline uint64_t mmu_primary_context_read(void) +{ + return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG); +} + +/** Write MMU Primary Context Register. + * + * @param v New value of Primary Context Register. + */ +NO_TRACE static inline void mmu_primary_context_write(uint64_t v) +{ + asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v); +} + +/** Read MMU Secondary Context Register. + * + * @return Current value of Secondary Context Register. + */ +NO_TRACE static inline uint64_t mmu_secondary_context_read(void) +{ + return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG); +} + +/** Write MMU Secondary Context Register. + * + * @param v New value of Secondary Context Register. + */ +NO_TRACE static inline void mmu_secondary_context_write(uint64_t v) +{ + asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v); +} + +/** + * Demaps all mappings in a context. + * + * @param context number of the context + * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both + */ +NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag) { + __hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag); +} + +/** + * Demaps given page. + * + * @param vaddr VA of the page to be demapped + * @param context number of the context + * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both + */ +NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) { + __hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag); +} + +extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *); +extern void fast_data_access_mmu_miss(sysarg_t, istate_t *); +extern void fast_data_access_protection(sysarg_t, istate_t *); + +extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); + +extern void describe_dmmu_fault(void); + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4v/tsb.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4v/tsb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4v/tsb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * Copyright (c) 2009 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_TSB_H_ +#define KERN_sparc64_sun4v_TSB_H_ + +/* + * TSB will claim 64K of memory, which + * is a nice number considered that it is one of + * the page sizes supported by hardware, which, + * again, is nice because TSBs need to be locked + * in TLBs - only one TLB entry will do. + */ +#define TSB_SIZE 3 /* when changing this, change + * as.c as well */ +#define TSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) + +#ifndef __ASM__ + +#include +#include +#include + +/** TSB description, used in hypercalls */ +typedef struct tsb_descr { + uint16_t page_size; /**< Page size (0 = 8K, 1 = 64K,...). */ + uint16_t associativity; /**< TSB associativity (will be 1). */ + uint32_t num_ttes; /**< Number of TTEs. */ + uint32_t context; /**< Context number. */ + uint32_t pgsize_mask; /**< Equals "1 << page_size". */ + uint64_t tsb_base; /**< Real address of TSB base. */ + uint64_t reserved; +} __attribute__ ((packed)) tsb_descr_t; + + +/* Forward declarations. */ +struct as; +struct pte; + +extern void tsb_invalidate(struct as *as, uintptr_t page, uint64_t pages); +extern void itsb_pte_copy(struct pte *t); +extern void dtsb_pte_copy(struct pte *t, bool ro); + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/sun4v/tte.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/sun4v/tte.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/sun4v/tte.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_TTE_H_ +#define KERN_sparc64_sun4v_TTE_H_ + +#define TTE_V_SHIFT 63 /**< valid */ +#define TTE_TADDR_SHIFT 13 /**< target address */ +#define TTE_CP_SHIFT 10 /**< cacheable physically */ +#define TTE_CV_SHIFT 9 /**< caheable virtually */ +#define TTE_P_SHIFT 8 /**< privileged */ +#define TTE_EP_SHIFT 7 /**< execute permission */ +#define TTE_W_SHIFT 6 /**< writable */ +#define TTE_SZ_SHIFT 0 /**< size */ + +#define MMU_FLAG_ITLB 2 /**< operation applies to ITLB */ +#define MMU_FLAG_DTLB 1 /**< operation applies to DTLB */ + +#ifndef __ASM__ + +#include + +/** Translation Table Entry - Data. */ +union tte_data { + uint64_t value; + struct { + unsigned v : 1; /**< Valid. */ + unsigned nfo : 1; /**< No-Fault-Only. */ + unsigned soft : 6; /**< Software defined field. */ + unsigned long ra : 43; /**< Real address. */ + unsigned ie : 1; /**< Invert endianess. */ + unsigned e : 1; /**< Side-effect. */ + unsigned cp : 1; /**< Cacheable in physically indexed cache. */ + unsigned cv : 1; /**< Cacheable in virtually indexed cache. */ + unsigned p : 1; /**< Privileged. */ + unsigned x : 1; /**< Executable. */ + unsigned w : 1; /**< Writable. */ + unsigned soft2 : 2; /**< Software defined field. */ + unsigned size : 4; /**< Page size. */ + } __attribute__ ((packed)); +}; + +typedef union tte_data tte_data_t; + +#define VA_TAG_PAGE_SHIFT 22 + +#endif /* !def __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/tlb.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/tlb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/tlb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TLB_H_ +#define KERN_sparc64_TLB_H_ + +#if defined (SUN4U) + +#include + +#elif defined (SUN4V) + +#include + +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/tsb.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/tsb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/tsb.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TSB_H_ +#define KERN_sparc64_TSB_H_ + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/mm/tte.h =================================================================== --- kernel/arch/sparc64/include/arch/mm/tte.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/mm/tte.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64mm + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TTE_H_ +#define KERN_sparc64_TTE_H_ + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/proc/task.h =================================================================== --- kernel/arch/sparc64/include/arch/proc/task.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/proc/task.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64proc + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TASK_H_ +#define KERN_sparc64_TASK_H_ + +typedef struct { +} task_arch_t; + +#define task_create_arch(t) +#define task_destroy_arch(t) + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/proc/thread.h =================================================================== --- kernel/arch/sparc64/include/arch/proc/thread.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/proc/thread.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64proc + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_THREAD_H_ +#define KERN_sparc64_THREAD_H_ + +#include +#include + +typedef struct { + /** Buffer for register windows with userspace content. */ + uint8_t *uspace_window_buffer; +} thread_arch_t; + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/regdef.h =================================================================== --- kernel/arch/sparc64/include/arch/regdef.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/regdef.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_REGDEF_H_ +#define KERN_sparc64_REGDEF_H_ + +#define PSTATE_IE_BIT (1 << 1) +#define PSTATE_AM_BIT (1 << 3) + +#define PSTATE_AG_BIT (1 << 0) +#define PSTATE_IG_BIT (1 << 11) +#define PSTATE_MG_BIT (1 << 10) + +#define PSTATE_PRIV_BIT (1 << 2) +#define PSTATE_PEF_BIT (1 << 4) + +#define TSTATE_PSTATE_SHIFT 8 +#define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT << TSTATE_PSTATE_SHIFT) +#define TSTATE_IE_BIT (PSTATE_IE_BIT << TSTATE_PSTATE_SHIFT) +#define TSTATE_PEF_BIT (PSTATE_PEF_BIT << TSTATE_PSTATE_SHIFT) + +#define TSTATE_CWP_MASK 0x1f + +#define WSTATE_NORMAL(n) (n) +#define WSTATE_OTHER(n) ((n) << 3) + +/* + * The following definitions concern the UPA_CONFIG register on US and the + * FIREPLANE_CONFIG register on US3. + */ +#define ICBUS_CONFIG_MID_SHIFT 17 + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/register.h =================================================================== --- kernel/arch/sparc64/include/arch/register.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/register.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_REGISTER_H_ +#define KERN_sparc64_REGISTER_H_ + +#include +#include + +/** Version Register. */ +union ver_reg { + uint64_t value; + struct { + uint16_t manuf; /**< Manufacturer code. */ + uint16_t impl; /**< Implementation code. */ + uint8_t mask; /**< Mask set revision. */ + unsigned : 8; + uint8_t maxtl; + unsigned : 3; + unsigned maxwin : 5; + } __attribute__ ((packed)); +}; +typedef union ver_reg ver_reg_t; + +/** Processor State Register. */ +union pstate_reg { + uint64_t value; + struct { + uint64_t : 52; + unsigned ig : 1; /**< Interrupt Globals. */ + unsigned mg : 1; /**< MMU Globals. */ + unsigned cle : 1; /**< Current Little Endian. */ + unsigned tle : 1; /**< Trap Little Endian. */ + unsigned mm : 2; /**< Memory Model. */ + unsigned red : 1; /**< RED state. */ + unsigned pef : 1; /**< Enable floating-point. */ + unsigned am : 1; /**< 32-bit Address Mask. */ + unsigned priv : 1; /**< Privileged Mode. */ + unsigned ie : 1; /**< Interrupt Enable. */ + unsigned ag : 1; /**< Alternate Globals*/ + } __attribute__ ((packed)); +}; +typedef union pstate_reg pstate_reg_t; + +/** TICK Register. */ +union tick_reg { + uint64_t value; + struct { + unsigned npt : 1; /**< Non-privileged Trap enable. */ + uint64_t counter : 63; /**< Elapsed CPU clck cycle counter. */ + } __attribute__ ((packed)); +}; +typedef union tick_reg tick_reg_t; + +/** TICK_compare Register. */ +union tick_compare_reg { + uint64_t value; + struct { + unsigned int_dis : 1; /**< TICK_INT interrupt disabled flag. */ + uint64_t tick_cmpr : 63; /**< Compare value for TICK interrupts. */ + } __attribute__ ((packed)); +}; +typedef union tick_compare_reg tick_compare_reg_t; + +/** SOFTINT Register. */ +union softint_reg { + uint64_t value; + struct { + uint64_t : 47; + unsigned stick_int : 1; + unsigned int_level : 15; + unsigned tick_int : 1; + } __attribute__ ((packed)); +}; +typedef union softint_reg softint_reg_t; + +/** Floating-point Registers State Register. */ +union fprs_reg { + uint64_t value; + struct { + uint64_t : 61; + unsigned fef : 1; + unsigned du : 1; + unsigned dl : 1; + } __attribute__ ((packed)); +}; +typedef union fprs_reg fprs_reg_t; + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/smp/sun4v/smp.h =================================================================== --- kernel/arch/sparc64/include/arch/smp/sun4v/smp.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/smp/sun4v/smp.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2009 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** + * @file + * @brief sun4v smp functions + */ + +#ifndef KERN_sparc64_sun4v_SMP_H_ +#define KERN_sparc64_sun4v_SMP_H_ + +#include +#include + +extern bool calculate_optimal_nrdy(exec_unit_t *); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/sparc64.h =================================================================== --- kernel/arch/sparc64/include/arch/sparc64.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/sparc64.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_SPARC64_H_ +#define KERN_sparc64_SPARC64_H_ + +#include + +extern void interrupt_register(unsigned int, const char *, iroutine_t); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/stack.h =================================================================== --- kernel/arch/sparc64/include/arch/stack.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/stack.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_STACK_H_ +#define KERN_sparc64_STACK_H_ + +#define STACK_ITEM_SIZE 8 + +/** According to SPARC Compliance Definition, every stack frame is 16-byte aligned. */ +#define STACK_ALIGNMENT 16 + +/** + * 16-extended-word save area for %i[0-7] and %l[0-7] registers. + */ +#define STACK_WINDOW_SAVE_AREA_SIZE (16 * STACK_ITEM_SIZE) + +/** + * Six extended words for first six arguments. + */ +#define STACK_ARG_SAVE_AREA_SIZE (6 * STACK_ITEM_SIZE) + +/** + * By convention, the actual top of the stack is %sp + STACK_BIAS. + */ +#define STACK_BIAS 2047 + +/* + * Offsets of arguments on stack. + */ +#define STACK_ARG0 0 +#define STACK_ARG1 8 +#define STACK_ARG2 16 +#define STACK_ARG3 24 +#define STACK_ARG4 32 +#define STACK_ARG5 40 +#define STACK_ARG6 48 + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/sun4u/arch.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4u/arch.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/sun4u/arch.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** + * @file + * @brief Various sun4u-specific macros. + */ + +#ifndef KERN_sparc64_sun4u_ARCH_H_ +#define KERN_sparc64_sun4u_ARCH_H_ + +#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ +#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ +#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/sun4u/asm.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4u/asm.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/sun4u/asm.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_ASM_H_ +#define KERN_sparc64_sun4u_ASM_H_ + +#include + +/** Read Version Register. + * + * @return Value of VER register. + * + */ +NO_TRACE static inline uint64_t ver_read(void) +{ + uint64_t v; + + asm volatile ( + "rdpr %%ver, %[v]\n" + : [v] "=r" (v) + ); + + return v; +} + +extern uint64_t read_from_ag_g7(void); +extern void write_to_ag_g6(uint64_t); +extern void write_to_ag_g7(uint64_t); +extern void write_to_ig_g6(uint64_t); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/sun4u/cpu.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4u/cpu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/sun4u/cpu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4u_CPU_H_ +#define KERN_sparc64_sun4u_CPU_H_ + +#define MANUF_FUJITSU 0x04 +#define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */ +#define MANUF_SUN 0x3e + +#define IMPL_ULTRASPARCI 0x10 +#define IMPL_ULTRASPARCII 0x11 +#define IMPL_ULTRASPARCII_I 0x12 +#define IMPL_ULTRASPARCII_E 0x13 +#define IMPL_ULTRASPARCIII 0x14 +#define IMPL_ULTRASPARCIII_PLUS 0x15 +#define IMPL_ULTRASPARCIII_I 0x16 +#define IMPL_ULTRASPARCIV 0x18 +#define IMPL_ULTRASPARCIV_PLUS 0x19 + +#define IMPL_SPARC64V 0x5 + +#ifndef __ASM__ + +#include +#include +#include +#include +#include + +typedef struct { + uint32_t mid; /**< Processor ID as read from + UPA_CONFIG/FIREPLANE_CONFIG. */ + ver_reg_t ver; + uint32_t clock_frequency; /**< Processor frequency in Hz. */ + uint64_t next_tick_cmpr; /**< Next clock interrupt should be + generated when the TICK register + matches this value. */ +} cpu_arch_t; + +/** Read the module ID (agent ID/CPUID) of the current CPU. + * + */ +NO_TRACE static inline uint32_t read_mid(void) +{ + uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0); + icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT; + +#if defined (US) + return icbus_config & 0x1f; +#elif defined (US3) + if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I) + return icbus_config & 0x1f; + else + return icbus_config & 0x3ff; +#endif +} + +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/sun4v/arch.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4v/arch.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/sun4v/arch.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2009 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** + * @file + * @brief Various sun4v-specific macros. + */ + +#ifndef KERN_sparc64_sun4v_ARCH_H_ +#define KERN_sparc64_sun4v_ARCH_H_ + +/* scratch pad registers ASI */ +#define ASI_SCRATCHPAD 0x20 + +/* + * Assignment of scratchpad register virtual addresses. The same convention is + * used by both Linux and Solaris. + */ + +/* register where the address of the MMU fault status area will be stored */ +#define SCRATCHPAD_MMU_FSA 0x00 + +/* register where the CPUID will be stored */ +#define SCRATCHPAD_CPUID 0x08 + +/* register where the kernel stack address will be stored */ +#define SCRATCHPAD_KSTACK 0x10 + +/* register where the userspace window buffer address will be stored */ +#define SCRATCHPAD_WBUF 0x18 + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/sun4v/asm.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4v/asm.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/sun4v/asm.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_ASM_H_ +#define KERN_sparc64_sun4v_ASM_H_ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/sun4v/cpu.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4v/cpu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/sun4v/cpu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_CPU_H_ +#define KERN_sparc64_sun4v_CPU_H_ + +/** Maximum number of virtual processors. */ +#define MAX_NUM_STRANDS 64 + +/** Maximum number of logical processors in a processor core */ +#define MAX_CORE_STRANDS 8 + +#ifndef __ASM__ + +#include +#include + +struct cpu; + +typedef struct { + uint64_t exec_unit_id; + uint8_t strand_count; + uint64_t cpuids[MAX_CORE_STRANDS]; + struct cpu *cpus[MAX_CORE_STRANDS]; + atomic_t nrdy; + SPINLOCK_DECLARE(proposed_nrdy_lock); +} exec_unit_t; + +typedef struct cpu_arch { + uint64_t id; /**< virtual processor ID */ + uint32_t clock_frequency; /**< Processor frequency in Hz. */ + uint64_t next_tick_cmpr; /**< Next clock interrupt should be + generated when the TICK register + matches this value. */ + exec_unit_t *exec_unit; /**< Physical core. */ + unsigned long proposed_nrdy; /**< Proposed No. of ready threads + so that cores are equally balanced. */ +} cpu_arch_t; + +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/sun4v/hypercall.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4v/hypercall.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/sun4v/hypercall.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2008 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** + * @file + * @brief Macros, constants and functions needed to perform a call to the + * hypervisor API. For details and terminology see this document: + * UltraSPARC Virtual Machine Specification (The Hypervisor API + * specification for Logical Domains). + * + */ + +#ifndef KERN_sparc64_sun4v_HYPERCALL_H_ +#define KERN_sparc64_sun4v_HYPERCALL_H_ + +/* SW trap numbers for hyperfast traps */ +#define FAST_TRAP 0x80 +#define MMU_MAP_ADDR 0x83 +#define MMU_UNMAP_ADDR 0x84 + +/* function codes for fast traps */ +#define MACH_DESC 0x01 +#define CPU_START 0x10 +#define CPU_STOP 0x11 +#define CPU_YIELD 0x12 +#define CPU_QCONF 0x14 +#define CPU_MYID 0x16 +#define CPU_STATE 0x17 +#define CPU_SET_RTBA 0x18 +#define CPU_GET_RTBA 0x19 +#define MMU_TSB_CTX0 0x20 +#define MMU_TSB_CTXNON0 0x21 +#define MMU_DEMAP_PAGE 0x22 +#define MMU_DEMAP_CTX 0x23 +#define MMU_DEMAP_ALL 0x24 +#define MMU_MAP_PERM_ADDR 0x25 +#define MMU_FAULT_AREA_CONF 0x26 +#define MMU_ENABLE 0x27 +#define MMU_UNMAP_PERM_ADDR 0x28 +#define MMU_TSB_CTX0_INFO 0x29 +#define MMU_TSB_CTXNON0_INFO 0x2a +#define MMU_FAULT_AREA_INFO 0x2b +#define CPU_MONDO_SEND 0x42 +#define CONS_GETCHAR 0x60 +#define CONS_PUTCHAR 0x61 + + +/* return codes */ +#define HV_EOK 0 /**< Successful return */ +#define HV_ENOCPU 1 /**< Invalid CPU id */ +#define HV_ENORADDR 2 /**< Invalid real address */ +#define HV_ENOINTR 3 /**< Invalid interrupt id */ +#define HV_EBADPGSZ 4 /**< Invalid pagesize encoding */ +#define HV_EBADTSB 5 /**< Invalid TSB description */ +#define HV_EINVAL 6 /**< Invalid argument */ +#define HV_EBADTRAP 7 /**< Invalid function number */ +#define HV_EBADALIGN 8 /**< Invalid address alignment */ +#define HV_EWOULDBLOCK 9 /**< Cannot complete operation without blocking */ +#define HV_ENOACCESS 10 /**< No access to specified resource */ +#define HV_EIO 11 /**< I/O Error */ +#define HV_ECPUERROR 12 /**< CPU is in error state */ +#define HV_ENOTSUPPORTED 13 /**< Function not supported */ +#define HV_ENOMAP 14 /**< No mapping found */ +#define HV_ETOOMANY 15 /**< Too many items specified / limit reached */ +#define HV_ECHANNEL 16 /**< Invalid LDC channel */ +#define HV_EBUSY 17 /**< Operation failed as resource is otherwise busy */ + + +/** + * Performs a hyperfast hypervisor API call from the assembly language code. + * Expects the registers %o1-%o4 are properly filled with the arguments of the + * call. + * + * @param function_number hyperfast call function number + */ +#define __HYPERCALL_FAST(function_number) \ + set function_number, %o5; \ + ta FAST_TRAP; + +/** + * Performs a fast hypervisor API call from the assembly language code. + * Expects the registers %o1-%o4 are properly filled with the arguments of the + * call. + * + * @param sw_trap_number software trap number + */ +#define __HYPERCALL_HYPERFAST(sw_trap_number) \ + ta (sw_trap_number); + + +#ifndef __ASM__ + +#include + +/* + * Macros to be used from the C-language code; __hypercall_fastN performs + * a fast hypervisor API call taking exactly N arguments. + */ + +#define __hypercall_fast0(function_number) \ + __hypercall_fast(0, 0, 0, 0, 0, function_number) +#define __hypercall_fast1(function_number, p1) \ + __hypercall_fast(p1, 0, 0, 0, 0, function_number) +#define __hypercall_fast2(function_number, p1, p2) \ + __hypercall_fast(p1, p2, 0, 0, 0, function_number) +#define __hypercall_fast3(function_number, p1, p2, p3) \ + __hypercall_fast(p1, p2, p3, 0, 0, function_number) +#define __hypercall_fast4(function_number, p1, p2, p3, p4) \ + __hypercall_fast(p1, p2, p3, p4, 0, function_number) +#define __hypercall_fast5(function_number, p1, p2, p3, p4, p5) \ + __hypercall_fast(p1, p2, p3, p4, p5, function_number) + +/** + * Performs a fast hypervisor API call which returns no value except for the + * error status. + * + * @param p1 the 1st argument of the hypervisor API call + * @param p2 the 2nd argument of the hypervisor API call + * @param p3 the 3rd argument of the hypervisor API call + * @param p4 the 4th argument of the hypervisor API call + * @param p5 the 5th argument of the hypervisor API call + * @param function_number function number of the call + * @return error status + */ +static inline uint64_t +__hypercall_fast(const uint64_t p1, const uint64_t p2, const uint64_t p3, + const uint64_t p4, const uint64_t p5, const uint64_t function_number) +{ + register uint64_t a6 asm("o5") = function_number; + register uint64_t a1 asm("o0") = p1; + register uint64_t a2 asm("o1") = p2; + register uint64_t a3 asm("o2") = p3; + register uint64_t a4 asm("o3") = p4; + register uint64_t a5 asm("o4") = p5; + + asm volatile ( + "ta %7\n" + : "=r" (a1) + : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), + "i" (FAST_TRAP) + : "memory" + ); + + return a1; +} + +/** + * Performs a fast hypervisor API call which can return a value. + * + * @param p1 the 1st argument of the hypervisor API call + * @param p2 the 2nd argument of the hypervisor API call + * @param p3 the 3rd argument of the hypervisor API call + * @param p4 the 4th argument of the hypervisor API call + * @param p5 the 5th argument of the hypervisor API call + * @param function_number function number of the call + * @param ret1 pointer to an address where the return value + * of the hypercall should be saved, or NULL + * @return error status + */ +static inline uint64_t +__hypercall_fast_ret1(const uint64_t p1, const uint64_t p2, const uint64_t p3, + const uint64_t p4, const uint64_t p5, const uint64_t function_number, + uint64_t *ret1) +{ + register uint64_t a6 asm("o5") = function_number; + register uint64_t a1 asm("o0") = p1; + register uint64_t a2 asm("o1") = p2; + register uint64_t a3 asm("o2") = p3; + register uint64_t a4 asm("o3") = p4; + register uint64_t a5 asm("o4") = p5; + + asm volatile ( + "ta %8\n" + : "=r" (a1), "=r" (a2) + : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), + "i" (FAST_TRAP) + : "memory" + ); + + if (ret1) + *ret1 = a2; + + return a1; +} + +/** + * Performs a hyperfast hypervisor API call. + * + * @param p1 the 1st argument of the hypervisor API call + * @param p2 the 2nd argument of the hypervisor API call + * @param p3 the 3rd argument of the hypervisor API call + * @param p4 the 4th argument of the hypervisor API call + * @param p5 the 5th argument of the hypervisor API call + * @param sw_trap_number software trap number + */ +static inline uint64_t +__hypercall_hyperfast(const uint64_t p1, const uint64_t p2, const uint64_t p3, + const uint64_t p4, const uint64_t p5, const uint64_t sw_trap_number) +{ + register uint64_t a1 asm("o0") = p1; + register uint64_t a2 asm("o1") = p2; + register uint64_t a3 asm("o2") = p3; + register uint64_t a4 asm("o3") = p4; + register uint64_t a5 asm("o4") = p5; + + asm volatile ( + "ta %6\n" + : "=r" (a1) + : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), + "i" (sw_trap_number) + : "memory" + ); + + return a1; +} + +#endif /* ASM */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/sun4v/ipi.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4v/ipi.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/sun4v/ipi.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2009 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** + * @file + * @brief sun4v-specific IPI functions + */ + +#ifndef KERN_sparc64_sun4v_IPI_H_ +#define KERN_sparc64_sun4v_IPI_H_ + +#include + +extern uint64_t ipi_brodcast_to(void (*)(void), uint16_t cpu_list[], uint64_t); +extern uint64_t ipi_unicast_to(void (*)(void), uint16_t); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/sun4v/md.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4v/md.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/sun4v/md.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2009 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_MD_H_ +#define KERN_sparc64_sun4v_MD_H_ + +#include + +/** + * Data type used to iterate through MD nodes. Internally represented as + * an index to the first element of the node. + */ +typedef unsigned int md_node_t; + +/** used to iterate over children of a given node */ +typedef unsigned int md_child_iter_t; + +md_node_t md_get_root(void); +md_node_t md_get_child(md_node_t node, char *name); +md_child_iter_t md_get_child_iterator(md_node_t node); +bool md_next_child(md_child_iter_t *it); +md_node_t md_get_child_node(md_child_iter_t it); +const char *md_get_node_name(md_node_t node); +bool md_get_integer_property(md_node_t node, const char *key, + uint64_t *result); +bool md_get_string_property(md_node_t node, const char *key, + const char **result); +bool md_next_node(md_node_t *node, const char *name); +void md_init(void); + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/sun4v/regdef.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4v/regdef.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/sun4v/regdef.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * Copyright (c) 2008 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_REGDEF_H_ +#define KERN_sparc64_sun4v_REGDEF_H_ + +#define TSTATE_CWP_MASK 0x1f + +#define WSTATE_NORMAL(n) (n) +#define WSTATE_OTHER(n) ((n) << 3) + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/sun4v/register.h =================================================================== --- kernel/arch/sparc64/include/arch/sun4v/register.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/sun4v/register.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_sun4v_REGISTER_H_ +#define KERN_sparc64_sun4v_REGISTER_H_ + +#include +#include + +/** Processor State Register. */ +union pstate_reg { + uint64_t value; + struct { + uint64_t : 54; + unsigned cle : 1; /**< Current Little Endian. */ + unsigned tle : 1; /**< Trap Little Endian. */ + unsigned mm : 2; /**< Memory Model. */ + unsigned : 1; /**< RED state. */ + unsigned pef : 1; /**< Enable floating-point. */ + unsigned am : 1; /**< 32-bit Address Mask. */ + unsigned priv : 1; /**< Privileged Mode. */ + unsigned ie : 1; /**< Interrupt Enable. */ + unsigned : 1; + } __attribute__ ((packed)); +}; +typedef union pstate_reg pstate_reg_t; + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/exception.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/exception.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/exception.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** + * @file + */ + +#ifndef KERN_sparc64_EXCEPTION_H_ +#define KERN_sparc64_EXCEPTION_H_ + +#define TT_INSTRUCTION_ACCESS_EXCEPTION 0x08 +#define TT_INSTRUCTION_ACCESS_MMU_MISS 0x09 +#define TT_INSTRUCTION_ACCESS_ERROR 0x0a +#define TT_IAE_UNAUTH_ACCESS 0x0b +#define TT_IAE_NFO_PAGE 0x0c +#define TT_ILLEGAL_INSTRUCTION 0x10 +#define TT_PRIVILEGED_OPCODE 0x11 +#define TT_UNIMPLEMENTED_LDD 0x12 +#define TT_UNIMPLEMENTED_STD 0x13 +#define TT_DAE_INVALID_ASI 0x14 +#define TT_DAE_PRIVILEGE_VIOLATION 0x15 +#define TT_DAE_NC_PAGE 0x16 +#define TT_DAE_NFO_PAGE 0x17 +#define TT_FP_DISABLED 0x20 +#define TT_FP_EXCEPTION_IEEE_754 0x21 +#define TT_FP_EXCEPTION_OTHER 0x22 +#define TT_TAG_OVERFLOW 0x23 +#define TT_DIVISION_BY_ZERO 0x28 +#define TT_DATA_ACCESS_EXCEPTION 0x30 +#define TT_DATA_ACCESS_MMU_MISS 0x31 +#define TT_DATA_ACCESS_ERROR 0x32 +#define TT_MEM_ADDRESS_NOT_ALIGNED 0x34 +#define TT_LDDF_MEM_ADDRESS_NOT_ALIGNED 0x35 +#define TT_STDF_MEM_ADDRESS_NOT_ALIGNED 0x36 +#define TT_PRIVILEGED_ACTION 0x37 +#define TT_LDQF_MEM_ADDRESS_NOT_ALIGNED 0x38 +#define TT_STQF_MEM_ADDRESS_NOT_ALIGNED 0x39 + +#ifndef __ASM__ + +#include + +extern void dump_istate(istate_t *istate); + +extern void instruction_access_exception(int n, istate_t *istate); +extern void instruction_access_error(int n, istate_t *istate); +extern void illegal_instruction(int n, istate_t *istate); +extern void privileged_opcode(int n, istate_t *istate); +extern void unimplemented_LDD(int n, istate_t *istate); +extern void unimplemented_STD(int n, istate_t *istate); +extern void fp_disabled(int n, istate_t *istate); +extern void fp_exception_ieee_754(int n, istate_t *istate); +extern void fp_exception_other(int n, istate_t *istate); +extern void tag_overflow(int n, istate_t *istate); +extern void division_by_zero(int n, istate_t *istate); +extern void data_access_exception(int n, istate_t *istate); +extern void data_access_error(int n, istate_t *istate); +extern void mem_address_not_aligned(int n, istate_t *istate); +extern void LDDF_mem_address_not_aligned(int n, istate_t *istate); +extern void STDF_mem_address_not_aligned(int n, istate_t *istate); +extern void privileged_action(int n, istate_t *istate); +extern void LDQF_mem_address_not_aligned(int n, istate_t *istate); +extern void STQF_mem_address_not_aligned(int n, istate_t *istate); + +#endif /* !__ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/interrupt.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/interrupt.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/interrupt.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** + * @file + * @brief This file contains level N interrupt and inter-processor interrupt + * trap handler. + */ +#ifndef KERN_sparc64_INTERRUPT_TRAP_H_ +#define KERN_sparc64_INTERRUPT_TRAP_H_ + +#define TT_INTERRUPT_LEVEL_1 0x41 +#define TT_INTERRUPT_LEVEL_2 0x42 +#define TT_INTERRUPT_LEVEL_3 0x43 +#define TT_INTERRUPT_LEVEL_4 0x44 +#define TT_INTERRUPT_LEVEL_5 0x45 +#define TT_INTERRUPT_LEVEL_6 0x46 +#define TT_INTERRUPT_LEVEL_7 0x47 +#define TT_INTERRUPT_LEVEL_8 0x48 +#define TT_INTERRUPT_LEVEL_9 0x49 +#define TT_INTERRUPT_LEVEL_10 0x4a +#define TT_INTERRUPT_LEVEL_11 0x4b +#define TT_INTERRUPT_LEVEL_12 0x4c +#define TT_INTERRUPT_LEVEL_13 0x4d +#define TT_INTERRUPT_LEVEL_14 0x4e +#define TT_INTERRUPT_LEVEL_15 0x4f + +#define INTERRUPT_LEVEL_N_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE + +/* IMAP register bits */ +#define IGN_MASK 0x7c0 +#define INO_MASK 0x1f +#define IMAP_V_MASK (1ULL << 31) + +#define IGN_SHIFT 6 + + +#ifdef __ASM__ +.macro INTERRUPT_LEVEL_N_HANDLER n + mov \n - 1, %g2 + PREEMPTIBLE_HANDLER exc_dispatch +.endm +#endif + +#ifndef __ASM__ + +#include + +extern void interrupt(int n, istate_t *istate); +#endif /* !def __ASM__ */ + + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/mmu.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/mmu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/mmu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** + * @file + * @brief This file contains fast MMU trap handlers. + */ + +#ifndef KERN_sparc64_MMU_TRAP_H_ +#define KERN_sparc64_MMU_TRAP_H_ + +#if defined (SUN4U) +#include +#elif defined (SUN4V) +#include +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/regwin.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/regwin.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/regwin.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** + * @file + * @brief This file contains register window trap handlers. + */ + +#ifndef KERN_sparc64_REGWIN_H_ +#define KERN_sparc64_REGWIN_H_ + +#include +#include +#include + +#define TT_CLEAN_WINDOW 0x24 +#define TT_SPILL_0_NORMAL 0x80 /* kernel spills */ +#define TT_SPILL_1_NORMAL 0x84 /* userspace spills */ +#define TT_SPILL_2_NORMAL 0x88 /* spills to userspace window buffer */ +#define TT_SPILL_0_OTHER 0xa0 /* spills to userspace window buffer */ +#define TT_FILL_0_NORMAL 0xc0 /* kernel fills */ +#define TT_FILL_1_NORMAL 0xc4 /* userspace fills */ + +#define REGWIN_HANDLER_SIZE 128 + +#define CLEAN_WINDOW_HANDLER_SIZE REGWIN_HANDLER_SIZE +#define SPILL_HANDLER_SIZE REGWIN_HANDLER_SIZE +#define FILL_HANDLER_SIZE REGWIN_HANDLER_SIZE + +/* Window Save Area offsets. */ +#define L0_OFFSET 0 +#define L1_OFFSET 8 +#define L2_OFFSET 16 +#define L3_OFFSET 24 +#define L4_OFFSET 32 +#define L5_OFFSET 40 +#define L6_OFFSET 48 +#define L7_OFFSET 56 +#define I0_OFFSET 64 +#define I1_OFFSET 72 +#define I2_OFFSET 80 +#define I3_OFFSET 88 +#define I4_OFFSET 96 +#define I5_OFFSET 104 +#define I6_OFFSET 112 +#define I7_OFFSET 120 + +/* Uspace Window Buffer constants. */ +#define UWB_SIZE ((NWINDOWS - 1) * STACK_WINDOW_SAVE_AREA_SIZE) +#define UWB_ALIGNMENT 1024 +#define UWB_ASIZE ALIGN_UP(UWB_SIZE, UWB_ALIGNMENT) + +#ifdef __ASM__ + +/* + * Macro used by the nucleus and the primary context 0 during normal and other spills. + */ +.macro SPILL_NORMAL_HANDLER_KERNEL + stx %l0, [%sp + STACK_BIAS + L0_OFFSET] + stx %l1, [%sp + STACK_BIAS + L1_OFFSET] + stx %l2, [%sp + STACK_BIAS + L2_OFFSET] + stx %l3, [%sp + STACK_BIAS + L3_OFFSET] + stx %l4, [%sp + STACK_BIAS + L4_OFFSET] + stx %l5, [%sp + STACK_BIAS + L5_OFFSET] + stx %l6, [%sp + STACK_BIAS + L6_OFFSET] + stx %l7, [%sp + STACK_BIAS + L7_OFFSET] + stx %i0, [%sp + STACK_BIAS + I0_OFFSET] + stx %i1, [%sp + STACK_BIAS + I1_OFFSET] + stx %i2, [%sp + STACK_BIAS + I2_OFFSET] + stx %i3, [%sp + STACK_BIAS + I3_OFFSET] + stx %i4, [%sp + STACK_BIAS + I4_OFFSET] + stx %i5, [%sp + STACK_BIAS + I5_OFFSET] + stx %i6, [%sp + STACK_BIAS + I6_OFFSET] + stx %i7, [%sp + STACK_BIAS + I7_OFFSET] + saved + retry +.endm + +/* + * Macro used by the userspace during normal spills. + */ +.macro SPILL_NORMAL_HANDLER_USERSPACE + wr %g0, ASI_AIUP, %asi + stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi + stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi + stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi + stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi + stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi + stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi + stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi + stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi + stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi + stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi + stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi + stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi + stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi + stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi + stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi + stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi + saved + retry +.endm + +/* + * Macro used by the nucleus and the primary context 0 during normal fills. + */ +.macro FILL_NORMAL_HANDLER_KERNEL + ldx [%sp + STACK_BIAS + L0_OFFSET], %l0 + ldx [%sp + STACK_BIAS + L1_OFFSET], %l1 + ldx [%sp + STACK_BIAS + L2_OFFSET], %l2 + ldx [%sp + STACK_BIAS + L3_OFFSET], %l3 + ldx [%sp + STACK_BIAS + L4_OFFSET], %l4 + ldx [%sp + STACK_BIAS + L5_OFFSET], %l5 + ldx [%sp + STACK_BIAS + L6_OFFSET], %l6 + ldx [%sp + STACK_BIAS + L7_OFFSET], %l7 + ldx [%sp + STACK_BIAS + I0_OFFSET], %i0 + ldx [%sp + STACK_BIAS + I1_OFFSET], %i1 + ldx [%sp + STACK_BIAS + I2_OFFSET], %i2 + ldx [%sp + STACK_BIAS + I3_OFFSET], %i3 + ldx [%sp + STACK_BIAS + I4_OFFSET], %i4 + ldx [%sp + STACK_BIAS + I5_OFFSET], %i5 + ldx [%sp + STACK_BIAS + I6_OFFSET], %i6 + ldx [%sp + STACK_BIAS + I7_OFFSET], %i7 + restored + retry +.endm + +/* + * Macro used by the userspace during normal fills. + */ +.macro FILL_NORMAL_HANDLER_USERSPACE + wr %g0, ASI_AIUP, %asi + ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0 + ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1 + ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2 + ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3 + ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4 + ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5 + ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6 + ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7 + ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0 + ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1 + ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2 + ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3 + ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4 + ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5 + ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6 + ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7 + restored + retry +.endm + +.macro CLEAN_WINDOW_HANDLER + rdpr %cleanwin, %l0 + add %l0, 1, %l0 + wrpr %l0, 0, %cleanwin +#if defined(SUN4U) + mov %r0, %l0 + mov %r0, %l1 + mov %r0, %l2 + mov %r0, %l3 + mov %r0, %l4 + mov %r0, %l5 + mov %r0, %l6 + mov %r0, %l7 + mov %r0, %o0 + mov %r0, %o1 + mov %r0, %o2 + mov %r0, %o3 + mov %r0, %o4 + mov %r0, %o5 + mov %r0, %o6 + mov %r0, %o7 +#endif + retry +.endm +#endif /* __ASM__ */ + +#if defined(SUN4U) +#include +#elif defined(SUN4V) +#include +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/sun4u/interrupt.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4u/interrupt.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/sun4u/interrupt.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** + * @file + * @brief This file contains interrupt vector trap handler. + */ + +#ifndef KERN_sparc64_TRAP_SUN4U_INTERRUPT_H_ +#define KERN_sparc64_TRAP_SUN4U_INTERRUPT_H_ + +#include +#include + + +/* Interrupt ASI registers. */ +#define ASI_INTR_W 0x77 +#define ASI_INTR_DISPATCH_STATUS 0x48 +#define ASI_INTR_R 0x7f +#define ASI_INTR_RECEIVE 0x49 + +/* VA's used with ASI_INTR_W register. */ +#if defined (US) +#define ASI_UDB_INTR_W_DATA_0 0x40 +#define ASI_UDB_INTR_W_DATA_1 0x50 +#define ASI_UDB_INTR_W_DATA_2 0x60 +#elif defined (US3) +#define VA_INTR_W_DATA_0 0x40 +#define VA_INTR_W_DATA_1 0x48 +#define VA_INTR_W_DATA_2 0x50 +#define VA_INTR_W_DATA_3 0x58 +#define VA_INTR_W_DATA_4 0x60 +#define VA_INTR_W_DATA_5 0x68 +#define VA_INTR_W_DATA_6 0x80 +#define VA_INTR_W_DATA_7 0x88 +#endif +#define VA_INTR_W_DISPATCH 0x70 + +/* VA's used with ASI_INTR_R register. */ +#if defined(US) +#define ASI_UDB_INTR_R_DATA_0 0x40 +#define ASI_UDB_INTR_R_DATA_1 0x50 +#define ASI_UDB_INTR_R_DATA_2 0x60 +#elif defined (US3) +#define VA_INTR_R_DATA_0 0x40 +#define VA_INTR_R_DATA_1 0x48 +#define VA_INTR_R_DATA_2 0x50 +#define VA_INTR_R_DATA_3 0x58 +#define VA_INTR_R_DATA_4 0x60 +#define VA_INTR_R_DATA_5 0x68 +#define VA_INTR_R_DATA_6 0x80 +#define VA_INTR_R_DATA_7 0x88 +#endif + +/* Shifts in the Interrupt Vector Dispatch virtual address. */ +#define INTR_VEC_DISPATCH_MID_SHIFT 14 + +/* Bits in the Interrupt Dispatch Status register. */ +#define INTR_DISPATCH_STATUS_NACK 0x2 +#define INTR_DISPATCH_STATUS_BUSY 0x1 + +#define TT_INTERRUPT_VECTOR_TRAP 0x60 + +#define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE + +#ifdef __ASM__ +.macro INTERRUPT_VECTOR_TRAP_HANDLER + PREEMPTIBLE_HANDLER interrupt +.endm +#endif /* __ASM__ */ + + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/sun4u/mmu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** + * @file + * @brief This file contains fast MMU trap handlers. + */ + +#ifndef KERN_sparc64_SUN4U_MMU_TRAP_H_ +#define KERN_sparc64_SUN4U_MMU_TRAP_H_ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_TSB +#include +#endif + +#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 +#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 +#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c + +#define FAST_MMU_HANDLER_SIZE 128 + +#ifdef __ASM__ + +.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER + /* + * First, try to refill TLB from TSB. + */ +#ifdef CONFIG_TSB + ldxa [%g0] ASI_IMMU, %g1 ! read TSB Tag Target Register + ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2 ! read TSB 8K Pointer + ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 + cmp %g1, %g4 ! is this the entry we are looking for? + bne,pn %xcc, 0f + nop + stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG ! copy mapping from ITSB to ITLB + retry +#endif + +0: + wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate + PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss +.endm + +.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl + /* + * First, try to refill TLB from TSB. + */ + +#ifdef CONFIG_TSB + ldxa [%g0] ASI_DMMU, %g1 ! read TSB Tag Target Register + srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss? + brz,pn %g2, 0f + ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3 ! read TSB 8K Pointer + ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 + cmp %g1, %g4 ! is this the entry we are looking for? + bne,pn %xcc, 0f + nop + stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG ! copy mapping from DTSB to DTLB + retry +#endif + + /* + * Second, test if it is the portion of the kernel address space + * which is faulting. If that is the case, immediately create + * identity mapping for that page in DTLB. VPN 0 is excluded from + * this treatment. + * + * Note that branch-delay slots are used in order to save space. + */ +0: + sethi %hi(fast_data_access_mmu_miss_data_hi), %g7 + wr %g0, ASI_DMMU, %asi + ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1 ! read the faulting Context and VPN + set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 + andcc %g1, %g2, %g3 ! get Context + bnz %xcc, 0f ! Context is non-zero + andncc %g1, %g2, %g3 ! get page address into %g3 + bz %xcc, 0f ! page address is zero + ldx [%g7 + %lo(end_of_identity)], %g4 + cmp %g3, %g4 + bgeu %xcc, 0f + + ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2 + add %g3, %g2, %g2 + stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page + retry + + /* + * Third, catch and handle special cases when the trap is caused by + * the userspace register window spill or fill handler. In case + * one of these two traps caused this trap, we just lower the trap + * level and service the DTLB miss. In the end, we restart + * the offending SAVE or RESTORE. + */ +0: +.if (\tl > 0) + wrpr %g0, 1, %tl +.endif + + /* + * Switch from the MM globals. + */ + wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate + + /* + * Read the Tag Access register for the higher-level handler. + * This is necessary to survive nested DTLB misses. + */ + ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2 + + /* + * g2 will be passed as an argument to fast_data_access_mmu_miss(). + */ + PREEMPTIBLE_HANDLER fast_data_access_mmu_miss +.endm + +.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl + /* + * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. + */ + +.if (\tl > 0) + wrpr %g0, 1, %tl +.endif + + /* + * Switch from the MM globals. + */ + wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate + + /* + * Read the Tag Access register for the higher-level handler. + * This is necessary to survive nested DTLB misses. + */ + mov VA_DMMU_TAG_ACCESS, %g2 + ldxa [%g2] ASI_DMMU, %g2 + + /* + * g2 will be passed as an argument to fast_data_access_mmu_miss(). + */ + PREEMPTIBLE_HANDLER fast_data_access_protection +.endm + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/sun4u/regwin.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4u/regwin.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/sun4u/regwin.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +#ifndef KERN_sparc64_sun4u_REGWIN_H_ +#define KERN_sparc64_sun4u_REGWIN_H_ + +#ifdef __ASM__ + +/* + * Macro used to spill userspace window to userspace window buffer. + * It can be either triggered from preemptible_handler doing SAVE + * at (TL=1) or from normal kernel code doing SAVE when OTHERWIN>0 + * at (TL=0). + */ +.macro SPILL_TO_USPACE_WINDOW_BUFFER + stx %l0, [%g7 + L0_OFFSET] + stx %l1, [%g7 + L1_OFFSET] + stx %l2, [%g7 + L2_OFFSET] + stx %l3, [%g7 + L3_OFFSET] + stx %l4, [%g7 + L4_OFFSET] + stx %l5, [%g7 + L5_OFFSET] + stx %l6, [%g7 + L6_OFFSET] + stx %l7, [%g7 + L7_OFFSET] + stx %i0, [%g7 + I0_OFFSET] + stx %i1, [%g7 + I1_OFFSET] + stx %i2, [%g7 + I2_OFFSET] + stx %i3, [%g7 + I3_OFFSET] + stx %i4, [%g7 + I4_OFFSET] + stx %i5, [%g7 + I5_OFFSET] + stx %i6, [%g7 + I6_OFFSET] + stx %i7, [%g7 + I7_OFFSET] + add %g7, STACK_WINDOW_SAVE_AREA_SIZE, %g7 + saved + retry +.endm + +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/sun4v/interrupt.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** + * @file + * @brief This file contains interrupt vector trap handler. + */ + +#ifndef KERN_sparc64_TRAP_SUN4V_INTERRUPT_H_ +#define KERN_sparc64_TRAP_SUN4V_INTERRUPT_H_ + +#ifndef __ASM__ + +extern void sun4v_ipi_init(void); +extern void cpu_mondo(void); + +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/sun4v/mmu.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * Copyright (c) 2008 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** + * @file + * @brief This file contains fast MMU trap handlers. + */ + +#ifndef KERN_sparc64_sun4v_MMU_TRAP_H_ +#define KERN_sparc64_sun4v_MMU_TRAP_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_TSB +#include +#endif + +#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 +#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 +#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c +#define TT_CPU_MONDO 0x7c + +#define FAST_MMU_HANDLER_SIZE 128 + +#ifdef __ASM__ + +/* MMU fault status area data fault offset */ +#define FSA_DFA_OFFSET 0x48 + +/* MMU fault status area data context */ +#define FSA_DFC_OFFSET 0x50 + +/* offset of the target address within the TTE Data entry */ +#define TTE_DATA_TADDR_OFFSET 13 + +.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER + PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss +.endm + +/* + * Handler of the Fast Data Access MMU Miss trap. If the trap occurred in the kernel + * (context 0), an identity mapping (with displacement) is installed. Otherwise + * a higher level service routine is called. + */ +.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl + mov SCRATCHPAD_MMU_FSA, %g1 + ldxa [%g1] ASI_SCRATCHPAD, %g1 ! g1 <= RA of MMU fault status area + + /* read faulting context */ + add %g1, FSA_DFC_OFFSET, %g2 ! g2 <= RA of data fault context + ldxa [%g2] ASI_REAL, %g3 ! read the fault context + + /* read the faulting address */ + add %g1, FSA_DFA_OFFSET, %g2 ! g2 <= RA of data fault address + ldxa [%g2] ASI_REAL, %g1 ! read the fault address + srlx %g1, TTE_DATA_TADDR_OFFSET, %g1 ! truncate it to page boundary + sllx %g1, TTE_DATA_TADDR_OFFSET, %g1 + + /* service by higher-level routine when context != 0 */ + brnz %g3, 0f + nop + /* exclude page number 0 from installing the identity mapping */ + brz %g1, 0f + nop + + /* + * Installing the identity does not fit into 32 instructions, call + * a separate routine. The routine performs RETRY, hence the call never + * returns. + */ + ba,a %xcc, install_identity_mapping + +0: + + /* + * One of the scenarios in which this trap can occur is when the + * register window spill/fill handler accesses a memory which is not + * mapped. In such a case, this handler will be called from TL = 1. + * We handle the situation by pretending that the MMU miss occurred + * on TL = 0. Once the MMU miss trap is services, the instruction which + * caused the spill/fill trap is restarted, the spill/fill trap occurs, + * but this time its handler accesse memory which IS mapped. + */ + .if (\tl > 0) + wrpr %g0, 1, %tl + .endif + + /* + * Save the faulting virtual page and faulting context to the %g2 + * register. The most significant 51 bits of the %g2 register will + * contain the virtual address which caused the fault truncated to the + * page boundary. The least significant 13 bits of the %g2 register + * will contain the number of the context in which the fault occurred. + * The value of the %g2 register will be passed as a parameter to the + * higher level service routine. + */ + or %g1, %g3, %g2 + + PREEMPTIBLE_HANDLER fast_data_access_mmu_miss +.endm + +/* + * Handler of the Fast Data MMU Protection trap. Finds the trapping address + * and context and calls higher level service routine. + */ +.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl + /* + * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. + */ + .if (\tl > 0) + wrpr %g0, 1, %tl + .endif + + mov SCRATCHPAD_MMU_FSA, %g1 + ldxa [%g1] ASI_SCRATCHPAD, %g1 ! g1 <= RA of MMU fault status area + + /* read faulting context */ + add %g1, FSA_DFC_OFFSET, %g2 ! g2 <= RA of data fault context + ldxa [%g2] ASI_REAL, %g3 ! read the fault context + + /* read the faulting address */ + add %g1, FSA_DFA_OFFSET, %g2 ! g2 <= RA of data fault address + ldxa [%g2] ASI_REAL, %g1 ! read the fault address + srlx %g1, TTE_DATA_TADDR_OFFSET, %g1 ! truncate it to page boundary + sllx %g1, TTE_DATA_TADDR_OFFSET, %g1 + + /* the same as for FAST_DATA_ACCESS_MMU_MISS_HANDLER */ + or %g1, %g3, %g2 + + PREEMPTIBLE_HANDLER fast_data_access_protection +.endm +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/sun4v/regwin.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/sun4v/regwin.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/sun4v/regwin.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * Copyright (c) 2009 Pavel Rimsky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +#ifndef KERN_sparc64_sun4v_REGWIN_H_ +#define KERN_sparc64_sun4v_REGWIN_H_ + +#ifdef __ASM__ + +/* + * Saves the contents of the current window to the userspace window buffer. + * Does not modify any register window registers, but updates pointer to the + * top of the userspace window buffer. + * + * Parameters: + * \tmpreg1 global register to be used for scratching purposes + * \tmpreg2 global register to be used for scratching purposes + */ +.macro SAVE_TO_USPACE_WBUF tmpreg1, tmpreg2 + set SCRATCHPAD_WBUF, \tmpreg2 + ldxa [\tmpreg2] ASI_SCRATCHPAD, \tmpreg1 + stx %l0, [\tmpreg1 + L0_OFFSET] + stx %l1, [\tmpreg1 + L1_OFFSET] + stx %l2, [\tmpreg1 + L2_OFFSET] + stx %l3, [\tmpreg1 + L3_OFFSET] + stx %l4, [\tmpreg1 + L4_OFFSET] + stx %l5, [\tmpreg1 + L5_OFFSET] + stx %l6, [\tmpreg1 + L6_OFFSET] + stx %l7, [\tmpreg1 + L7_OFFSET] + stx %i0, [\tmpreg1 + I0_OFFSET] + stx %i1, [\tmpreg1 + I1_OFFSET] + stx %i2, [\tmpreg1 + I2_OFFSET] + stx %i3, [\tmpreg1 + I3_OFFSET] + stx %i4, [\tmpreg1 + I4_OFFSET] + stx %i5, [\tmpreg1 + I5_OFFSET] + stx %i6, [\tmpreg1 + I6_OFFSET] + stx %i7, [\tmpreg1 + I7_OFFSET] + add \tmpreg1, STACK_WINDOW_SAVE_AREA_SIZE, \tmpreg1 + stxa \tmpreg1, [\tmpreg2] ASI_SCRATCHPAD +.endm + +/* + * Macro used to spill userspace window to userspace window buffer. + * It is triggered from normal kernel code doing SAVE when + * OTHERWIN>0 at (TL=0). + */ +.macro SPILL_TO_USPACE_WINDOW_BUFFER + SAVE_TO_USPACE_WBUF %g7, %g4 + saved + retry +.endm + +#endif + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/syscall.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/syscall.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/syscall.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2006 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** + * @file + * @brief + */ + +#ifndef KERN_sparc64_SYSCALL_TRAP_H_ +#define KERN_sparc64_SYSCALL_TRAP_H_ + +#define TT_TRAP_INSTRUCTION_0 0x100 + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/trap/trap.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/trap.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/trap.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TRAP_H_ +#define KERN_sparc64_TRAP_H_ + +extern void trap_init(void); + +#endif + +/** @} + */ + Index: kernel/arch/sparc64/include/arch/trap/trap_table.h =================================================================== --- kernel/arch/sparc64/include/arch/trap/trap_table.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/trap/trap_table.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64interrupt + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TRAP_TABLE_H_ +#define KERN_sparc64_TRAP_TABLE_H_ + +#include + +#define TRAP_TABLE_ENTRY_COUNT 1024 +#define TRAP_TABLE_ENTRY_SIZE 32 +#define TRAP_TABLE_SIZE (TRAP_TABLE_ENTRY_COUNT * TRAP_TABLE_ENTRY_SIZE) + +/* + * The following needs to be in sync with the definition of the istate + * structure. The one STACK_ITEM_SIZE is counted for space holding the 7th + * argument to syscall_handler (i.e. syscall number) and the other + * STACK_ITEM_SIZE is counted because of the required alignment. + */ +#define PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE \ + (STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE + \ + (2 * STACK_ITEM_SIZE) + (12 * 8)) +#define SAVED_TSTATE -(1 * 8) +#define SAVED_TPC -(2 * 8) +#define SAVED_TNPC -(3 * 8) /* <-- istate_t begins here */ +#define SAVED_Y -(4 * 8) +#define SAVED_I0 -(5 * 8) +#define SAVED_I1 -(6 * 8) +#define SAVED_I2 -(7 * 8) +#define SAVED_I3 -(8 * 8) +#define SAVED_I4 -(9 * 8) +#define SAVED_I5 -(10 * 8) +#define SAVED_I6 -(11 * 8) +#define SAVED_I7 -(12 * 8) + +#ifndef __ASM__ + +#include + +struct trap_table_entry { + uint8_t octets[TRAP_TABLE_ENTRY_SIZE]; +} __attribute__ ((packed)); + +typedef struct trap_table_entry trap_table_entry_t; + +extern trap_table_entry_t trap_table[TRAP_TABLE_ENTRY_COUNT]; +extern trap_table_entry_t trap_table_save[TRAP_TABLE_ENTRY_COUNT]; +#endif /* !__ASM__ */ + +#ifdef __ASM__ +.macro SAVE_GLOBALS + mov %g1, %l1 + mov %g2, %l2 + mov %g3, %l3 + mov %g4, %l4 + mov %g5, %l5 + mov %g6, %l6 + mov %g7, %l7 +.endm + +.macro RESTORE_GLOBALS + mov %l1, %g1 + mov %l2, %g2 + mov %l3, %g3 + mov %l4, %g4 + mov %l5, %g5 + mov %l6, %g6 + mov %l7, %g7 +.endm + +.macro PREEMPTIBLE_HANDLER f + sethi %hi(\f), %g1 + ba %xcc, preemptible_handler + or %g1, %lo(\f), %g1 +.endm + +#endif /* __ASM__ */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/arch/types.h =================================================================== --- kernel/arch/sparc64/include/arch/types.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) +++ kernel/arch/sparc64/include/arch/types.h (revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828) @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2005 Jakub Jermar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @addtogroup sparc64 + * @{ + */ +/** @file + */ + +#ifndef KERN_sparc64_TYPES_H_ +#define KERN_sparc64_TYPES_H_ + +typedef uint64_t size_t; +typedef int64_t ssize_t; + +typedef uint64_t uintptr_t; +typedef uint64_t pfn_t; + +typedef uint64_t ipl_t; + +typedef uint64_t sysarg_t; +typedef int64_t native_t; +typedef uint64_t atomic_count_t; + +typedef struct { +} fncptr_t; + +typedef uint8_t asi_t; + +#define INTN_C(c) INT64_C(c) +#define UINTN_C(c) UINT64_C(c) + +#define PRIdn PRId64 /**< Format for native_t. */ +#define PRIun PRIu64 /**< Format for sysarg_t. */ +#define PRIxn PRIx64 /**< Format for hexadecimal sysarg_t. */ +#define PRIua PRIu64 /**< Format for atomic_count_t. */ + +#endif + +/** @} + */ Index: kernel/arch/sparc64/include/asm.h =================================================================== --- kernel/arch/sparc64/include/asm.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,557 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_ASM_H_ -#define KERN_sparc64_ASM_H_ - -#include -#include -#include -#include -#include -#include -#include -#include - -NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) -{ - *port = v; - memory_barrier(); -} - -NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) -{ - *port = v; - memory_barrier(); -} - -NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) -{ - *port = v; - memory_barrier(); -} - -NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) -{ - uint8_t rv = *port; - memory_barrier(); - return rv; -} - -NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) -{ - uint16_t rv = *port; - memory_barrier(); - return rv; -} - -NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) -{ - uint32_t rv = *port; - memory_barrier(); - return rv; -} - -/** Read Processor State register. - * - * @return Value of PSTATE register. - * - */ -NO_TRACE static inline uint64_t pstate_read(void) -{ - uint64_t v; - - asm volatile ( - "rdpr %%pstate, %[v]\n" - : [v] "=r" (v) - ); - - return v; -} - -/** Write Processor State register. - * - * @param v New value of PSTATE register. - * - */ -NO_TRACE static inline void pstate_write(uint64_t v) -{ - asm volatile ( - "wrpr %[v], %[zero], %%pstate\n" - :: [v] "r" (v), - [zero] "i" (0) - ); -} - -/** Read TICK_compare Register. - * - * @return Value of TICK_comapre register. - * - */ -NO_TRACE static inline uint64_t tick_compare_read(void) -{ - uint64_t v; - - asm volatile ( - "rd %%tick_cmpr, %[v]\n" - : [v] "=r" (v) - ); - - return v; -} - -/** Write TICK_compare Register. - * - * @param v New value of TICK_comapre register. - * - */ -NO_TRACE static inline void tick_compare_write(uint64_t v) -{ - asm volatile ( - "wr %[v], %[zero], %%tick_cmpr\n" - :: [v] "r" (v), - [zero] "i" (0) - ); -} - -/** Read STICK_compare Register. - * - * @return Value of STICK_compare register. - * - */ -NO_TRACE static inline uint64_t stick_compare_read(void) -{ - uint64_t v; - - asm volatile ( - "rd %%asr25, %[v]\n" - : [v] "=r" (v) - ); - - return v; -} - -/** Write STICK_compare Register. - * - * @param v New value of STICK_comapre register. - * - */ -NO_TRACE static inline void stick_compare_write(uint64_t v) -{ - asm volatile ( - "wr %[v], %[zero], %%asr25\n" - :: [v] "r" (v), - [zero] "i" (0) - ); -} - -/** Read TICK Register. - * - * @return Value of TICK register. - * - */ -NO_TRACE static inline uint64_t tick_read(void) -{ - uint64_t v; - - asm volatile ( - "rdpr %%tick, %[v]\n" - : [v] "=r" (v) - ); - - return v; -} - -/** Write TICK Register. - * - * @param v New value of TICK register. - * - */ -NO_TRACE static inline void tick_write(uint64_t v) -{ - asm volatile ( - "wrpr %[v], %[zero], %%tick\n" - :: [v] "r" (v), - [zero] "i" (0) - ); -} - -/** Read FPRS Register. - * - * @return Value of FPRS register. - * - */ -NO_TRACE static inline uint64_t fprs_read(void) -{ - uint64_t v; - - asm volatile ( - "rd %%fprs, %[v]\n" - : [v] "=r" (v) - ); - - return v; -} - -/** Write FPRS Register. - * - * @param v New value of FPRS register. - * - */ -NO_TRACE static inline void fprs_write(uint64_t v) -{ - asm volatile ( - "wr %[v], %[zero], %%fprs\n" - :: [v] "r" (v), - [zero] "i" (0) - ); -} - -/** Read SOFTINT Register. - * - * @return Value of SOFTINT register. - * - */ -NO_TRACE static inline uint64_t softint_read(void) -{ - uint64_t v; - - asm volatile ( - "rd %%softint, %[v]\n" - : [v] "=r" (v) - ); - - return v; -} - -/** Write SOFTINT Register. - * - * @param v New value of SOFTINT register. - * - */ -NO_TRACE static inline void softint_write(uint64_t v) -{ - asm volatile ( - "wr %[v], %[zero], %%softint\n" - :: [v] "r" (v), - [zero] "i" (0) - ); -} - -/** Write CLEAR_SOFTINT Register. - * - * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. - * - * @param v New value of CLEAR_SOFTINT register. - * - */ -NO_TRACE static inline void clear_softint_write(uint64_t v) -{ - asm volatile ( - "wr %[v], %[zero], %%clear_softint\n" - :: [v] "r" (v), - [zero] "i" (0) - ); -} - -/** Write SET_SOFTINT Register. - * - * Bits set in SET_SOFTINT register will be set in SOFTINT register. - * - * @param v New value of SET_SOFTINT register. - * - */ -NO_TRACE static inline void set_softint_write(uint64_t v) -{ - asm volatile ( - "wr %[v], %[zero], %%set_softint\n" - :: [v] "r" (v), - [zero] "i" (0) - ); -} - -/** Enable interrupts. - * - * Enable interrupts and return previous - * value of IPL. - * - * @return Old interrupt priority level. - * - */ -NO_TRACE static inline ipl_t interrupts_enable(void) { - pstate_reg_t pstate; - uint64_t value = pstate_read(); - - pstate.value = value; - pstate.ie = true; - pstate_write(pstate.value); - - return (ipl_t) value; -} - -/** Disable interrupts. - * - * Disable interrupts and return previous - * value of IPL. - * - * @return Old interrupt priority level. - * - */ -NO_TRACE static inline ipl_t interrupts_disable(void) { - pstate_reg_t pstate; - uint64_t value = pstate_read(); - - pstate.value = value; - pstate.ie = false; - pstate_write(pstate.value); - - return (ipl_t) value; -} - -/** Restore interrupt priority level. - * - * Restore IPL. - * - * @param ipl Saved interrupt priority level. - * - */ -NO_TRACE static inline void interrupts_restore(ipl_t ipl) { - pstate_reg_t pstate; - - pstate.value = pstate_read(); - pstate.ie = ((pstate_reg_t) ipl).ie; - pstate_write(pstate.value); -} - -/** Return interrupt priority level. - * - * Return IPL. - * - * @return Current interrupt priority level. - * - */ -NO_TRACE static inline ipl_t interrupts_read(void) { - return (ipl_t) pstate_read(); -} - -/** Check interrupts state. - * - * @return True if interrupts are disabled. - * - */ -NO_TRACE static inline bool interrupts_disabled(void) -{ - pstate_reg_t pstate; - - pstate.value = pstate_read(); - return !pstate.ie; -} - -/** Return base address of current stack. - * - * Return the base address of the current stack. - * The stack is assumed to be STACK_SIZE bytes long. - * The stack must start on page boundary. - * - */ -NO_TRACE static inline uintptr_t get_stack_base(void) -{ - uintptr_t unbiased_sp; - - asm volatile ( - "add %%sp, %[stack_bias], %[unbiased_sp]\n" - : [unbiased_sp] "=r" (unbiased_sp) - : [stack_bias] "i" (STACK_BIAS) - ); - - return ALIGN_DOWN(unbiased_sp, STACK_SIZE); -} - -/** Read Version Register. - * - * @return Value of VER register. - * - */ -NO_TRACE static inline uint64_t ver_read(void) -{ - uint64_t v; - - asm volatile ( - "rdpr %%ver, %[v]\n" - : [v] "=r" (v) - ); - - return v; -} - -/** Read Trap Program Counter register. - * - * @return Current value in TPC. - * - */ -NO_TRACE static inline uint64_t tpc_read(void) -{ - uint64_t v; - - asm volatile ( - "rdpr %%tpc, %[v]\n" - : [v] "=r" (v) - ); - - return v; -} - -/** Read Trap Level register. - * - * @return Current value in TL. - * - */ -NO_TRACE static inline uint64_t tl_read(void) -{ - uint64_t v; - - asm volatile ( - "rdpr %%tl, %[v]\n" - : [v] "=r" (v) - ); - - return v; -} - -/** Read Trap Base Address register. - * - * @return Current value in TBA. - * - */ -NO_TRACE static inline uint64_t tba_read(void) -{ - uint64_t v; - - asm volatile ( - "rdpr %%tba, %[v]\n" - : [v] "=r" (v) - ); - - return v; -} - -/** Write Trap Base Address register. - * - * @param v New value of TBA. - * - */ -NO_TRACE static inline void tba_write(uint64_t v) -{ - asm volatile ( - "wrpr %[v], %[zero], %%tba\n" - :: [v] "r" (v), - [zero] "i" (0) - ); -} - -/** Load uint64_t from alternate space. - * - * @param asi ASI determining the alternate space. - * @param va Virtual address within the ASI. - * - * @return Value read from the virtual address in - * the specified address space. - * - */ -NO_TRACE static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) -{ - uint64_t v; - - asm volatile ( - "ldxa [%[va]] %[asi], %[v]\n" - : [v] "=r" (v) - : [va] "r" (va), - [asi] "i" ((unsigned int) asi) - ); - - return v; -} - -/** Store uint64_t to alternate space. - * - * @param asi ASI determining the alternate space. - * @param va Virtual address within the ASI. - * @param v Value to be written. - * - */ -NO_TRACE static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) -{ - asm volatile ( - "stxa %[v], [%[va]] %[asi]\n" - :: [v] "r" (v), - [va] "r" (va), - [asi] "i" ((unsigned int) asi) - : "memory" - ); -} - -/** Flush all valid register windows to memory. */ -NO_TRACE static inline void flushw(void) -{ - asm volatile ("flushw\n"); -} - -/** Switch to nucleus by setting TL to 1. */ -NO_TRACE static inline void nucleus_enter(void) -{ - asm volatile ("wrpr %g0, 1, %tl\n"); -} - -/** Switch from nucleus by setting TL to 0. */ -NO_TRACE static inline void nucleus_leave(void) -{ - asm volatile ("wrpr %g0, %g0, %tl\n"); -} - -extern void cpu_halt(void) __attribute__((noreturn)); -extern void cpu_sleep(void); -extern void asm_delay_loop(const uint32_t usec); - -extern uint64_t read_from_ag_g6(void); -extern uint64_t read_from_ag_g7(void); -extern void write_to_ag_g6(uint64_t val); -extern void write_to_ag_g7(uint64_t val); -extern void write_to_ig_g6(uint64_t val); - -extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/atomic.h =================================================================== --- kernel/arch/sparc64/include/atomic.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,156 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_ATOMIC_H_ -#define KERN_sparc64_ATOMIC_H_ - -#include -#include -#include -#include - -/** Atomic add operation. - * - * Use atomic compare and swap operation to atomically add signed value. - * - * @param val Atomic variable. - * @param i Signed value to be added. - * - * @return Value of the atomic variable as it existed before addition. - * - */ -NO_TRACE static inline atomic_count_t atomic_add(atomic_t *val, - atomic_count_t i) -{ - atomic_count_t a; - atomic_count_t b; - - do { - volatile uintptr_t ptr = (uintptr_t) &val->count; - - a = *((atomic_count_t *) ptr); - b = a + i; - - asm volatile ( - "casx %0, %2, %1\n" - : "+m" (*((atomic_count_t *) ptr)), - "+r" (b) - : "r" (a) - ); - } while (a != b); - - return a; -} - -NO_TRACE static inline atomic_count_t atomic_preinc(atomic_t *val) -{ - return atomic_add(val, 1) + 1; -} - -NO_TRACE static inline atomic_count_t atomic_postinc(atomic_t *val) -{ - return atomic_add(val, 1); -} - -NO_TRACE static inline atomic_count_t atomic_predec(atomic_t *val) -{ - return atomic_add(val, -1) - 1; -} - -NO_TRACE static inline atomic_count_t atomic_postdec(atomic_t *val) -{ - return atomic_add(val, -1); -} - -NO_TRACE static inline void atomic_inc(atomic_t *val) -{ - (void) atomic_add(val, 1); -} - -NO_TRACE static inline void atomic_dec(atomic_t *val) -{ - (void) atomic_add(val, -1); -} - -NO_TRACE static inline atomic_count_t test_and_set(atomic_t *val) -{ - atomic_count_t v = 1; - volatile uintptr_t ptr = (uintptr_t) &val->count; - - asm volatile ( - "casx %0, %2, %1\n" - : "+m" (*((atomic_count_t *) ptr)), - "+r" (v) - : "r" (0) - ); - - return v; -} - -NO_TRACE static inline void atomic_lock_arch(atomic_t *val) -{ - atomic_count_t tmp1 = 1; - atomic_count_t tmp2 = 0; - - volatile uintptr_t ptr = (uintptr_t) &val->count; - - preemption_disable(); - - asm volatile ( - "0:\n" - "casx %0, %3, %1\n" - "brz %1, 2f\n" - "nop\n" - "1:\n" - "ldx %0, %2\n" - "brz %2, 0b\n" - "nop\n" - "ba,a %%xcc, 1b\n" - "2:\n" - : "+m" (*((atomic_count_t *) ptr)), - "+r" (tmp1), - "+r" (tmp2) - : "r" (0) - ); - - /* - * Prevent critical section code from bleeding out this way up. - */ - CS_ENTER_BARRIER(); -} - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/barrier.h =================================================================== --- kernel/arch/sparc64/include/barrier.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,150 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_BARRIER_H_ -#define KERN_sparc64_BARRIER_H_ - -#include - -/* - * Our critical section barriers are prepared for the weakest RMO memory model. - */ -#define CS_ENTER_BARRIER() \ - asm volatile ( \ - "membar #LoadLoad | #LoadStore\n" \ - ::: "memory" \ - ) - -#define CS_LEAVE_BARRIER() \ - asm volatile ( \ - "membar #StoreStore\n" \ - "membar #LoadStore\n" \ - ::: "memory" \ - ) - -#define memory_barrier() \ - asm volatile ( \ - "membar #LoadLoad | #StoreStore\n" \ - ::: "memory" \ - ) - -#define read_barrier() \ - asm volatile ( \ - "membar #LoadLoad\n" \ - ::: "memory" \ - ) - -#define write_barrier() \ - asm volatile ( \ - "membar #StoreStore\n" \ - ::: "memory" \ - ) - -#define flush(a) \ - asm volatile ( \ - "flush %[reg]\n" \ - :: [reg] "r" ((a)) \ - : "memory" \ - ) - -/** Flush Instruction pipeline. */ -NO_TRACE static inline void flush_pipeline(void) -{ - uint64_t pc; - - /* - * The FLUSH instruction takes address parameter. - * As such, it may trap if the address is not found in DTLB. - * - * The entire kernel text is mapped by a locked ITLB and - * DTLB entries. Therefore, when this function is called, - * the %pc register will always be in the range mapped by - * DTLB. - * - */ - - asm volatile ( - "rd %%pc, %[pc]\n" - "flush %[pc]\n" - : [pc] "=&r" (pc) - ); -} - -/** Memory Barrier instruction. */ -NO_TRACE static inline void membar(void) -{ - asm volatile ( - "membar #Sync\n" - ); -} - -#if defined (US) - -#define FLUSH_INVAL_MIN 4 - -#define smc_coherence(a) \ - do { \ - write_barrier(); \ - flush((a)); \ - } while (0) - -#define smc_coherence_block(a, l) \ - do { \ - unsigned long i; \ - write_barrier(); \ - \ - for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \ - flush((void *)(a) + i); \ - } while (0) - -#elif defined (US3) - -#define smc_coherence(a) \ - do { \ - write_barrier(); \ - flush_pipeline(); \ - } while (0) - -#define smc_coherence_block(a, l) \ - do { \ - write_barrier(); \ - flush_pipeline(); \ - } while (0) - -#endif /* defined(US3) */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/boot/boot.h =================================================================== --- kernel/arch/sparc64/include/boot/boot.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,96 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_BOOT_H_ -#define KERN_sparc64_BOOT_H_ - -#define VMA 0x400000 -#define LMA VMA - -#ifndef __ASM__ -#ifndef __LINKER__ - -#include -#include -#include - -#define TASKMAP_MAX_RECORDS 32 -#define MEMMAP_MAX_RECORDS 32 - -#define BOOTINFO_TASK_NAME_BUFLEN 32 - -typedef struct { - void *addr; - size_t size; - char name[BOOTINFO_TASK_NAME_BUFLEN]; -} utask_t; - -typedef struct { - size_t cnt; - utask_t tasks[TASKMAP_MAX_RECORDS]; -} taskmap_t; - -typedef struct { - void *start; - size_t size; -} memzone_t; - -typedef struct { - uint64_t total; - size_t cnt; - memzone_t zones[MEMMAP_MAX_RECORDS]; -} memmap_t; - -/** Bootinfo structure. - * - * Must be in sync with bootinfo structure used by the boot loader. - * - */ -typedef struct { - uintptr_t physmem_start; - taskmap_t taskmap; - memmap_t memmap; - ballocs_t ballocs; - ofw_tree_node_t *ofw_root; -} bootinfo_t; - -extern memmap_t memmap; - -#endif -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/console.h =================================================================== --- kernel/arch/sparc64/include/console.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,44 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_CONSOLE_H_ -#define KERN_sparc64_CONSOLE_H_ - -extern void kkbdpoll(void *arg); -extern void standalone_sparc64_console_init(void); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/context.h =================================================================== --- kernel/arch/sparc64/include/context.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,81 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_CONTEXT_H_ -#define KERN_sparc64_CONTEXT_H_ - -#include -#include -#include - -#define SP_DELTA (STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE) - -#define context_set(c, _pc, stack, size) \ - do { \ - (c)->pc = ((uintptr_t) _pc) - 8; \ - (c)->sp = ((uintptr_t) stack) + ALIGN_UP((size), \ - STACK_ALIGNMENT) - (STACK_BIAS + SP_DELTA); \ - (c)->fp = -STACK_BIAS; \ - } while (0) - -/* - * Save only registers that must be preserved across - * function calls. - */ -typedef struct { - uintptr_t sp; /* %o6 */ - uintptr_t pc; /* %o7 */ - uint64_t i0; - uint64_t i1; - uint64_t i2; - uint64_t i3; - uint64_t i4; - uint64_t i5; - uintptr_t fp; /* %i6 */ - uintptr_t i7; - uint64_t l0; - uint64_t l1; - uint64_t l2; - uint64_t l3; - uint64_t l4; - uint64_t l5; - uint64_t l6; - uint64_t l7; - ipl_t ipl; -} context_t; - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/context_offset.h =================================================================== --- kernel/arch/sparc64/include/context_offset.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,107 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef KERN_sparc64_CONTEXT_OFFSET_H_ -#define KERN_sparc64_CONTEXT_OFFSET_H_ - -#define OFFSET_SP 0x0 -#define OFFSET_PC 0x8 -#define OFFSET_I0 0x10 -#define OFFSET_I1 0x18 -#define OFFSET_I2 0x20 -#define OFFSET_I3 0x28 -#define OFFSET_I4 0x30 -#define OFFSET_I5 0x38 -#define OFFSET_FP 0x40 -#define OFFSET_I7 0x48 -#define OFFSET_L0 0x50 -#define OFFSET_L1 0x58 -#define OFFSET_L2 0x60 -#define OFFSET_L3 0x68 -#define OFFSET_L4 0x70 -#define OFFSET_L5 0x78 -#define OFFSET_L6 0x80 -#define OFFSET_L7 0x88 - -#ifndef KERNEL -# define OFFSET_TP 0x90 -#endif - -#ifdef __ASM__ - -.macro CONTEXT_SAVE_ARCH_CORE ctx:req - stx %sp, [\ctx + OFFSET_SP] - stx %o7, [\ctx + OFFSET_PC] - stx %i0, [\ctx + OFFSET_I0] - stx %i1, [\ctx + OFFSET_I1] - stx %i2, [\ctx + OFFSET_I2] - stx %i3, [\ctx + OFFSET_I3] - stx %i4, [\ctx + OFFSET_I4] - stx %i5, [\ctx + OFFSET_I5] - stx %fp, [\ctx + OFFSET_FP] - stx %i7, [\ctx + OFFSET_I7] - stx %l0, [\ctx + OFFSET_L0] - stx %l1, [\ctx + OFFSET_L1] - stx %l2, [\ctx + OFFSET_L2] - stx %l3, [\ctx + OFFSET_L3] - stx %l4, [\ctx + OFFSET_L4] - stx %l5, [\ctx + OFFSET_L5] - stx %l6, [\ctx + OFFSET_L6] - stx %l7, [\ctx + OFFSET_L7] -#ifndef KERNEL - stx %g7, [\ctx + OFFSET_TP] -#endif -.endm - -.macro CONTEXT_RESTORE_ARCH_CORE ctx:req - ldx [\ctx + OFFSET_SP], %sp - ldx [\ctx + OFFSET_PC], %o7 - ldx [\ctx + OFFSET_I0], %i0 - ldx [\ctx + OFFSET_I1], %i1 - ldx [\ctx + OFFSET_I2], %i2 - ldx [\ctx + OFFSET_I3], %i3 - ldx [\ctx + OFFSET_I4], %i4 - ldx [\ctx + OFFSET_I5], %i5 - ldx [\ctx + OFFSET_FP], %fp - ldx [\ctx + OFFSET_I7], %i7 - ldx [\ctx + OFFSET_L0], %l0 - ldx [\ctx + OFFSET_L1], %l1 - ldx [\ctx + OFFSET_L2], %l2 - ldx [\ctx + OFFSET_L3], %l3 - ldx [\ctx + OFFSET_L4], %l4 - ldx [\ctx + OFFSET_L5], %l5 - ldx [\ctx + OFFSET_L6], %l6 - ldx [\ctx + OFFSET_L7], %l7 -#ifndef KERNEL - ldx [\ctx + OFFSET_TP], %g7 -#endif -.endm - -#endif /* __ASM__ */ - -#endif Index: kernel/arch/sparc64/include/cpu.h =================================================================== --- kernel/arch/sparc64/include/cpu.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,73 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_CPU_H_ -#define KERN_sparc64_CPU_H_ - -#define MANUF_FUJITSU 0x04 -#define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */ -#define MANUF_SUN 0x3e - -#define IMPL_ULTRASPARCI 0x10 -#define IMPL_ULTRASPARCII 0x11 -#define IMPL_ULTRASPARCII_I 0x12 -#define IMPL_ULTRASPARCII_E 0x13 -#define IMPL_ULTRASPARCIII 0x14 -#define IMPL_ULTRASPARCIII_PLUS 0x15 -#define IMPL_ULTRASPARCIII_I 0x16 -#define IMPL_ULTRASPARCIV 0x18 -#define IMPL_ULTRASPARCIV_PLUS 0x19 - -#define IMPL_SPARC64V 0x5 - -#ifndef __ASM__ - -#include -#include -#include -#include - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#endif - - -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/cpu_family.h =================================================================== --- kernel/arch/sparc64/include/cpu_family.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,83 +1,0 @@ -/* - * Copyright (c) 2008 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_CPU_FAMILY_H_ -#define KERN_sparc64_CPU_FAMILY_H_ - -#include -#include -#include -#include - -/** - * Find the processor (sub)family. - * - * @return true iff the CPU belongs to the US family - */ -static inline bool is_us(void) -{ - int impl = ((ver_reg_t) ver_read()).impl; - return (impl == IMPL_ULTRASPARCI) || (impl == IMPL_ULTRASPARCII) || - (impl == IMPL_ULTRASPARCII_I) || (impl == IMPL_ULTRASPARCII_E); -} - -/** - * Find the processor (sub)family. - * - * @return true iff the CPU belongs to the US-III subfamily - */ -static inline bool is_us_iii(void) -{ - int impl = ((ver_reg_t) ver_read()).impl; - return (impl == IMPL_ULTRASPARCIII) || - (impl == IMPL_ULTRASPARCIII_PLUS) || - (impl == IMPL_ULTRASPARCIII_I); -} - -/** - * Find the processor (sub)family. - * - * @return true iff the CPU belongs to the US-IV subfamily - */ -static inline bool is_us_iv(void) -{ - int impl = ((ver_reg_t) ver_read()).impl; - return (impl == IMPL_ULTRASPARCIV) || (impl == IMPL_ULTRASPARCIV_PLUS); -} - -#endif - -/** @} - */ - Index: kernel/arch/sparc64/include/cpu_node.h =================================================================== --- kernel/arch/sparc64/include/cpu_node.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,59 +1,0 @@ -/* - * Copyright (c) 2005 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_CPU_NODE_H_ -#define KERN_sparc64_CPU_NODE_H_ - -#include - - -/** Finds the parent node of all the CPU nodes (nodes named "cpu" or "cmp"). - * - * Depending on the machine type (and possibly the OFW version), CPUs can be - * at "/" or at "/ssm@0,0". - */ -static inline ofw_tree_node_t *cpus_parent(void) -{ - ofw_tree_node_t *parent; - parent = ofw_tree_find_child(ofw_tree_lookup("/"), "ssm@0,0"); - if (parent == NULL) - parent = ofw_tree_lookup("/"); - return parent; -} - -#endif - -/** @} - */ - Index: kernel/arch/sparc64/include/cycle.h =================================================================== --- kernel/arch/sparc64/include/cycle.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,49 +1,0 @@ -/* - * Copyright (c) 2006 Martin Decky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_CYCLE_H_ -#define KERN_sparc64_CYCLE_H_ - -#include -#include - -NO_TRACE static inline uint64_t get_cycle(void) -{ - return tick_read(); -} - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/drivers/fb.h =================================================================== --- kernel/arch/sparc64/include/drivers/fb.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,41 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_FB_H_ -#define KERN_sparc64_FB_H_ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/drivers/kbd.h =================================================================== --- kernel/arch/sparc64/include/drivers/kbd.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,46 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_KBD_H_ -#define KERN_sparc64_KBD_H_ - -#include -#include - -extern void kbd_init(ofw_tree_node_t *node); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/drivers/niagara.h =================================================================== --- kernel/arch/sparc64/include/drivers/niagara.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,54 +1,0 @@ -/* - * Copyright (c) 2008 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_NIAGARA_H -#define KERN_sparc64_NIAGARA_H - -#include -#include - -typedef struct { - thread_t *thread; - indev_t *srlnin; -} niagara_instance_t; - -char niagara_getc(void); -void niagara_grab(void); -void niagara_release(void); -niagara_instance_t *niagarain_init(void); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/drivers/pci.h =================================================================== --- kernel/arch/sparc64/include/drivers/pci.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,71 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_PCI_H_ -#define KERN_sparc64_PCI_H_ - -#include -#include -#include -#include - -typedef enum pci_model pci_model_t; -typedef struct pci pci_t; -typedef struct pci_operations pci_operations_t; - -enum pci_model { - PCI_UNKNOWN, - PCI_SABRE, - PCI_PSYCHO -}; - -struct pci_operations { - void (* enable_interrupt)(pci_t *, int); - void (* clear_interrupt)(pci_t *, int); -}; - -struct pci { - pci_model_t model; - pci_operations_t *op; - volatile uint64_t *reg; /**< Registers including interrupt registers. */ -}; - -extern pci_t *pci_init(ofw_tree_node_t *); -extern void pci_enable_interrupt(pci_t *, int); -extern void pci_clear_interrupt(void *, int); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/drivers/scr.h =================================================================== --- kernel/arch/sparc64/include/drivers/scr.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,57 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_SCR_H_ -#define KERN_sparc64_SCR_H_ - -#include -#include - -typedef enum { - SCR_UNKNOWN, - SCR_ATYFB, - SCR_FFB, - SCR_CGSIX, - SCR_XVR, - SCR_QEMU_VGA -} scr_type_t; - -extern scr_type_t scr_type; - -extern void scr_init(ofw_tree_node_t *node); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/drivers/tick.h =================================================================== --- kernel/arch/sparc64/include/drivers/tick.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,58 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_TICK_H_ -#define KERN_sparc64_TICK_H_ - -#include -#include - -/* mask of the "counter" field of the Tick register */ -#define TICK_COUNTER_MASK (~(1l << 63)) - -extern void tick_init(void); -extern void tick_interrupt(unsigned int, istate_t *); - -/** - * Reads the Tick register counter. - */ -static inline uint64_t tick_counter_read(void) -{ - return TICK_COUNTER_MASK & tick_read(); -} - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/elf.h =================================================================== --- kernel/arch/sparc64/include/elf.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,45 +1,0 @@ -/* - * Copyright (c) 2006 Sergey Bondari - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_ELF_H_ -#define KERN_sparc64_ELF_H_ - -#define ELF_MACHINE EM_SPARCV9 -#define ELF_DATA_ENCODING ELFDATA2MSB -#define ELF_CLASS ELFCLASS64 - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/faddr.h =================================================================== --- kernel/arch/sparc64/include/faddr.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,45 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_FADDR_H_ -#define KERN_sparc64_FADDR_H_ - -#include - -#define FADDR(fptr) ((uintptr_t) (fptr)) - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/fpu_context.h =================================================================== --- kernel/arch/sparc64/include/fpu_context.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,50 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_FPU_CONTEXT_H_ -#define KERN_sparc64_FPU_CONTEXT_H_ - -#include - -#define FPU_CONTEXT_ALIGN 8 - -typedef struct { - uint64_t d[32]; - uint64_t fsr; -} fpu_context_t; - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/interrupt.h =================================================================== --- kernel/arch/sparc64/include/interrupt.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,55 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt sparc64 - * @ingroup interrupt - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_INTERRUPT_H_ -#define KERN_sparc64_INTERRUPT_H_ - -#include -#include - -#define IVT_ITEMS 15 -#define IVT_FIRST 1 - -/* This needs to be defined for inter-architecture API portability. */ -#define VECTOR_TLB_SHOOTDOWN_IPI 0 - -enum { - IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI -}; - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/istate.h =================================================================== --- kernel/arch/sparc64/include/istate.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,82 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt sparc64 - * @ingroup interrupt - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_ISTATE_H_ -#define KERN_sparc64_ISTATE_H_ - -#include - -#ifdef KERNEL - -#include - -#else /* KERNEL */ - -#include - -#endif /* KERNEL */ - -typedef struct istate { - uint64_t tnpc; - uint64_t tpc; - uint64_t tstate; -} istate_t; - -NO_TRACE static inline void istate_set_retaddr(istate_t *istate, - uintptr_t retaddr) -{ - istate->tpc = retaddr; -} - -NO_TRACE static inline int istate_from_uspace(istate_t *istate) -{ - return !(istate->tstate & TSTATE_PRIV_BIT); -} - -NO_TRACE static inline uintptr_t istate_get_pc(istate_t *istate) -{ - return istate->tpc; -} - -NO_TRACE static inline uintptr_t istate_get_fp(istate_t *istate) -{ - /* TODO */ - return 0; -} - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/as.h =================================================================== --- kernel/arch/sparc64/include/mm/as.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,51 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_AS_H_ -#define KERN_sparc64_AS_H_ - -#if defined (SUN4U) - -#include - -#elif defined (SUN4V) - -#include - -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/asid.h =================================================================== --- kernel/arch/sparc64/include/mm/asid.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,50 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_ASID_H_ -#define KERN_sparc64_ASID_H_ - -#include - -/* - * On SPARC, Context means the same thing as ASID trough out the kernel. - */ -typedef uint16_t asid_t; - -#define ASID_MAX_ARCH 8191 /* 2^13 - 1 */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/cache_spec.h =================================================================== --- kernel/arch/sparc64/include/mm/cache_spec.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,60 +1,0 @@ -/* - * Copyright (c) 2008 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_CACHE_SPEC_H_ -#define KERN_sparc64_CACHE_SPEC_H_ - -/* - * The following macros are valid for the following processors: - * - * UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III, - * UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+ - * - * Should we support other UltraSPARC processors, we need to make sure that - * the macros are defined correctly for them. - */ - -#if defined (US) - #define DCACHE_SIZE (16 * 1024) -#elif defined (US3) - #define DCACHE_SIZE (64 * 1024) -#endif - -#define DCACHE_LINE_SIZE 32 -#define DCACHE_TAG_SHIFT 2 - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/frame.h =================================================================== --- kernel/arch/sparc64/include/mm/frame.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,51 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_FRAME_H_ -#define KERN_sparc64_FRAME_H_ - -#if defined (SUN4U) - -#include - -#elif defined (SUN4V) - -#include - -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/km.h =================================================================== --- kernel/arch/sparc64/include/mm/km.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,48 +1,0 @@ -/* - * Copyright (c) 2011 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_KM_H_ -#define KERN_sparc64_KM_H_ - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#endif - - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/mmu.h =================================================================== --- kernel/arch/sparc64/include/mm/mmu.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,48 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_MMU_H_ -#define KERN_sparc64_MMU_H_ - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#endif - - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/page.h =================================================================== --- kernel/arch/sparc64/include/mm/page.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,80 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_PAGE_H_ -#define KERN_sparc64_PAGE_H_ - -#include - -/* - * On the TLB and TSB level, we still use 8K pages, which are supported by the - * MMU. - */ -#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH -#define MMU_PAGE_SIZE MMU_FRAME_SIZE - -/* - * On the page table level, we use 16K pages. 16K pages are not supported by - * the MMU but we emulate them with pairs of 8K pages. - */ -#define PAGE_WIDTH FRAME_WIDTH -#define PAGE_SIZE FRAME_SIZE - -#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) - -#ifndef __ASM__ - -#include - -extern uintptr_t physmem_base; - -#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) -#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) - -typedef union { - uintptr_t address; - struct { - uint64_t vpn : 51; /**< Virtual Page Number. */ - unsigned offset : 13; /**< Offset. */ - } __attribute__ ((packed)); -} page_address_t; - -extern void page_arch_init(void); - -#endif /* !def __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/pagesize.h =================================================================== --- kernel/arch/sparc64/include/mm/pagesize.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,45 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * Copyright (c) 2008 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_PAGESIZE_H -#define KERN_sparc64_PAGESIZE_H - -/** Page sizes. */ -#define PAGESIZE_8K 0 -#define PAGESIZE_64K 1 -#define PAGESIZE_512K 2 -#define PAGESIZE_4M 3 - -#endif Index: kernel/arch/sparc64/include/mm/sun4u/as.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4u/as.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,94 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4u_AS_H_ -#define KERN_sparc64_sun4u_AS_H_ - -#include - -#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1 - -#define KERNEL_ADDRESS_SPACE_START_ARCH UINT64_C(0x0000000000000000) -#define KERNEL_ADDRESS_SPACE_END_ARCH UINT64_C(0xffffffffffffffff) -#define USER_ADDRESS_SPACE_START_ARCH UINT64_C(0x0000000000000000) -#define USER_ADDRESS_SPACE_END_ARCH UINT64_C(0xffffffffffffffff) - -#ifdef CONFIG_TSB - -/** TSB Tag Target register. */ -typedef union tsb_tag_target { - uint64_t value; - struct { - unsigned invalid : 1; /**< Invalidated by software. */ - unsigned : 2; - unsigned context : 13; /**< Software ASID. */ - unsigned : 6; - uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ - } __attribute__ ((packed)); -} tsb_tag_target_t; - -/** TSB entry. */ -typedef struct tsb_entry { - tsb_tag_target_t tag; - tte_data_t data; -} __attribute__ ((packed)) tsb_entry_t; - -typedef struct { - tsb_entry_t *itsb; - tsb_entry_t *dtsb; -} as_arch_t; - -#else - -typedef struct { -} as_arch_t; - -#endif /* CONFIG_TSB */ - -#include - -#ifdef CONFIG_TSB -#include -#define as_invalidate_translation_cache(as, page, cnt) \ - tsb_invalidate((as), (page), (cnt)) -#else -#define as_invalidate_translation_cache(as, page, cnt) -#endif - -extern void as_arch_init(void); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4u/frame.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4u/frame.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,85 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_SUN4U_FRAME_H_ -#define KERN_sparc64_SUN4U_FRAME_H_ - -/* - * Page size supported by the MMU. - * For 8K there is the nasty illegal virtual aliasing problem. - * Therefore, the kernel uses 8K only internally on the TLB and TSB levels. - */ -#define MMU_FRAME_WIDTH 13 /* 8K */ -#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) - -/* - * Page size exported to the generic memory management subsystems. - * This page size is not directly supported by the MMU, but we can emulate - * each 16K page with a pair of adjacent 8K pages. - */ -#define FRAME_WIDTH 14 /* 16K */ -#define FRAME_SIZE (1 << FRAME_WIDTH) - -#ifndef __ASM__ - -#include - -union frame_address { - uintptr_t address; - struct { -#if defined (US) - unsigned : 23; - uint64_t pfn : 28; /**< Physical Frame Number. */ -#elif defined (US3) - unsigned : 21; - uint64_t pfn : 30; /**< Physical Frame Number. */ -#endif - unsigned offset : 13; /**< Offset. */ - } __attribute__ ((packed)); -}; - -typedef union frame_address frame_address_t; - -extern uintptr_t end_of_identity; - -extern void frame_low_arch_init(void); -extern void frame_high_arch_init(void); -#define physmem_print() - -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4u/km.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4u/km.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,62 +1,0 @@ -/* - * Copyright (c) 2011 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4u_KM_H_ -#define KERN_sparc64_sun4u_KM_H_ - -#include - -/* - * Be conservative and assume the 44-bit virtual address width as found - * on the UltraSPARC CPU, even when running on a newer CPU, such as - * UltraSPARC III, which has the full 64-bit virtual address width. - * - * Do not use the 4 GiB area on either side of the VA hole to meet the - * limitations of the UltraSPARC CPU. - */ - -#define KM_SPARC64_US_IDENTITY_START UINT64_C(0x0000000000000000) -#define KM_SPARC64_US_IDENTITY_SIZE UINT64_C(0x000007ff00000000) - -#define KM_SPARC64_US_NON_IDENTITY_START UINT64_C(0xfffff80100000000) -#define KM_SPARC64_US_NON_IDENTITY_SIZE UINT64_C(0x000007ff00000000) - -extern void km_identity_arch_init(void); -extern void km_non_identity_arch_init(void); -extern bool km_is_non_identity_arch(uintptr_t); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4u/mmu.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4u/mmu.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,123 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4u_MMU_H_ -#define KERN_sparc64_sun4u_MMU_H_ - -#if defined(US) -/* LSU Control Register ASI. */ -#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ -#endif - -/* I-MMU ASIs. */ -#define ASI_IMMU 0x50 -#define ASI_IMMU_TSB_8KB_PTR_REG 0x51 -#define ASI_IMMU_TSB_64KB_PTR_REG 0x52 -#define ASI_ITLB_DATA_IN_REG 0x54 -#define ASI_ITLB_DATA_ACCESS_REG 0x55 -#define ASI_ITLB_TAG_READ_REG 0x56 -#define ASI_IMMU_DEMAP 0x57 - -/* Virtual Addresses within ASI_IMMU. */ -#define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ -#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ -#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ -#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ -#if defined (US3) -#define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */ -#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */ -#endif - - -/* D-MMU ASIs. */ -#define ASI_DMMU 0x58 -#define ASI_DMMU_TSB_8KB_PTR_REG 0x59 -#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a -#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b -#define ASI_DTLB_DATA_IN_REG 0x5c -#define ASI_DTLB_DATA_ACCESS_REG 0x5d -#define ASI_DTLB_TAG_READ_REG 0x5e -#define ASI_DMMU_DEMAP 0x5f - -/* Virtual Addresses within ASI_DMMU. */ -#define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ -#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ -#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ -#define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ -#define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ -#define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ -#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ -#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ -#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ -#if defined (US3) -#define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */ -#define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */ -#define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */ -#endif - -#ifndef __ASM__ - -#include -#include -#include - -#if defined(US) -/** LSU Control Register. */ -typedef union { - uint64_t value; - struct { - unsigned : 23; - unsigned pm : 8; - unsigned vm : 8; - unsigned pr : 1; - unsigned pw : 1; - unsigned vr : 1; - unsigned vw : 1; - unsigned : 1; - unsigned fm : 16; - unsigned dm : 1; /**< D-MMU enable. */ - unsigned im : 1; /**< I-MMU enable. */ - unsigned dc : 1; /**< D-Cache enable. */ - unsigned ic : 1; /**< I-Cache enable. */ - - } __attribute__ ((packed)); -} lsu_cr_reg_t; -#endif /* US */ - -#endif /* !def __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4u/tlb.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4u/tlb.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,694 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_TLB_sun4u_H_ -#define KERN_sparc64_TLB_sun4u_H_ - -#if defined (US) -#define ITLB_ENTRY_COUNT 64 -#define DTLB_ENTRY_COUNT 64 -#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT -#endif - -/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */ -#if defined (US3) -#define DTLB_MAX_LOCKED_ENTRIES 16 -#endif - -#define MEM_CONTEXT_KERNEL 0 -#define MEM_CONTEXT_TEMP 1 - -/** Page sizes. */ -#define PAGESIZE_8K 0 -#define PAGESIZE_64K 1 -#define PAGESIZE_512K 2 -#define PAGESIZE_4M 3 - -/** Bit width of the TLB-locked portion of kernel address space. */ -#define KERNEL_PAGE_WIDTH 22 /* 4M */ - -/* TLB Demap Operation types. */ -#define TLB_DEMAP_PAGE 0 -#define TLB_DEMAP_CONTEXT 1 -#if defined (US3) -#define TLB_DEMAP_ALL 2 -#endif - -#define TLB_DEMAP_TYPE_SHIFT 6 - -/* TLB Demap Operation Context register encodings. */ -#define TLB_DEMAP_PRIMARY 0 -#define TLB_DEMAP_SECONDARY 1 -#define TLB_DEMAP_NUCLEUS 2 - -/* There are more TLBs in one MMU in US3, their codes are defined here. */ -#if defined (US3) -/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */ -#define TLB_DSMALL 0 -#define TLB_DBIG_0 2 -#define TLB_DBIG_1 3 - -/* I-MMU: one small (16-entry) TLB and one big TLB */ -#define TLB_ISMALL 0 -#define TLB_IBIG 2 -#endif - -#define TLB_DEMAP_CONTEXT_SHIFT 4 - -/* TLB Tag Access shifts */ -#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 -#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) -#define TLB_TAG_ACCESS_VPN_SHIFT 13 - -#ifndef __ASM__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -union tlb_context_reg { - uint64_t v; - struct { - unsigned long : 51; - unsigned context : 13; /**< Context/ASID. */ - } __attribute__ ((packed)); -}; -typedef union tlb_context_reg tlb_context_reg_t; - -/** I-/D-TLB Data In/Access Register type. */ -typedef tte_data_t tlb_data_t; - -/** I-/D-TLB Data Access Address in Alternate Space. */ - -#if defined (US) - -union tlb_data_access_addr { - uint64_t value; - struct { - uint64_t : 55; - unsigned tlb_entry : 6; - unsigned : 3; - } __attribute__ ((packed)); -}; -typedef union tlb_data_access_addr dtlb_data_access_addr_t; -typedef union tlb_data_access_addr dtlb_tag_read_addr_t; -typedef union tlb_data_access_addr itlb_data_access_addr_t; -typedef union tlb_data_access_addr itlb_tag_read_addr_t; - -#elif defined (US3) - -/* - * In US3, I-MMU and D-MMU have different formats of the data - * access register virtual address. In the corresponding - * structures the member variable for the entry number is - * called "local_tlb_entry" - it contrasts with the "tlb_entry" - * for the US data access register VA structure. The rationale - * behind this is to prevent careless mistakes in the code - * caused by setting only the entry number and not the TLB - * number in the US3 code (when taking the code from US). - */ - -union dtlb_data_access_addr { - uint64_t value; - struct { - uint64_t : 45; - unsigned : 1; - unsigned tlb_number : 2; - unsigned : 4; - unsigned local_tlb_entry : 9; - unsigned : 3; - } __attribute__ ((packed)); -}; -typedef union dtlb_data_access_addr dtlb_data_access_addr_t; -typedef union dtlb_data_access_addr dtlb_tag_read_addr_t; - -union itlb_data_access_addr { - uint64_t value; - struct { - uint64_t : 45; - unsigned : 1; - unsigned tlb_number : 2; - unsigned : 6; - unsigned local_tlb_entry : 7; - unsigned : 3; - } __attribute__ ((packed)); -}; -typedef union itlb_data_access_addr itlb_data_access_addr_t; -typedef union itlb_data_access_addr itlb_tag_read_addr_t; - -#endif - -/** I-/D-TLB Tag Read Register. */ -union tlb_tag_read_reg { - uint64_t value; - struct { - uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ - unsigned context : 13; /**< Context identifier. */ - } __attribute__ ((packed)); -}; -typedef union tlb_tag_read_reg tlb_tag_read_reg_t; -typedef union tlb_tag_read_reg tlb_tag_access_reg_t; - - -/** TLB Demap Operation Address. */ -union tlb_demap_addr { - uint64_t value; - struct { - uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ -#if defined (US) - unsigned : 6; /**< Ignored. */ - unsigned type : 1; /**< The type of demap operation. */ -#elif defined (US3) - unsigned : 5; /**< Ignored. */ - unsigned type: 2; /**< The type of demap operation. */ -#endif - unsigned context : 2; /**< Context register selection. */ - unsigned : 4; /**< Zero. */ - } __attribute__ ((packed)); -}; -typedef union tlb_demap_addr tlb_demap_addr_t; - -/** TLB Synchronous Fault Status Register. */ -union tlb_sfsr_reg { - uint64_t value; - struct { -#if defined (US) - unsigned long : 40; /**< Implementation dependent. */ - unsigned asi : 8; /**< ASI. */ - unsigned : 2; - unsigned ft : 7; /**< Fault type. */ -#elif defined (US3) - unsigned long : 39; /**< Implementation dependent. */ - unsigned nf : 1; /**< Non-faulting load. */ - unsigned asi : 8; /**< ASI. */ - unsigned tm : 1; /**< I-TLB miss. */ - unsigned : 3; /**< Reserved. */ - unsigned ft : 5; /**< Fault type. */ -#endif - unsigned e : 1; /**< Side-effect bit. */ - unsigned ct : 2; /**< Context Register selection. */ - unsigned pr : 1; /**< Privilege bit. */ - unsigned w : 1; /**< Write bit. */ - unsigned ow : 1; /**< Overwrite bit. */ - unsigned fv : 1; /**< Fault Valid bit. */ - } __attribute__ ((packed)); -}; -typedef union tlb_sfsr_reg tlb_sfsr_reg_t; - -#if defined (US3) - -/* - * Functions for determining the number of entries in TLBs. They either return - * a constant value or a value based on the CPU autodetection. - */ - -/** - * Determine the number of entries in the DMMU's small TLB. - */ -NO_TRACE static inline uint16_t tlb_dsmall_size(void) -{ - return 16; -} - -/** - * Determine the number of entries in each DMMU's big TLB. - */ -NO_TRACE static inline uint16_t tlb_dbig_size(void) -{ - return 512; -} - -/** - * Determine the number of entries in the IMMU's small TLB. - */ -NO_TRACE static inline uint16_t tlb_ismall_size(void) -{ - return 16; -} - -/** - * Determine the number of entries in the IMMU's big TLB. - */ -NO_TRACE static inline uint16_t tlb_ibig_size(void) -{ - if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) - return 512; - else - return 128; -} - -#endif - -/** Read MMU Primary Context Register. - * - * @return Current value of Primary Context Register. - */ -NO_TRACE static inline uint64_t mmu_primary_context_read(void) -{ - return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); -} - -/** Write MMU Primary Context Register. - * - * @param v New value of Primary Context Register. - */ -NO_TRACE static inline void mmu_primary_context_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); - flush_pipeline(); -} - -/** Read MMU Secondary Context Register. - * - * @return Current value of Secondary Context Register. - */ -NO_TRACE static inline uint64_t mmu_secondary_context_read(void) -{ - return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); -} - -/** Write MMU Primary Context Register. - * - * @param v New value of Primary Context Register. - */ -NO_TRACE static inline void mmu_secondary_context_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); - flush_pipeline(); -} - -#if defined (US) - -/** Read IMMU TLB Data Access Register. - * - * @param entry TLB Entry index. - * - * @return Current value of specified IMMU TLB Data Access - * Register. - */ -NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry) -{ - itlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_entry = entry; - return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); -} - -/** Write IMMU TLB Data Access Register. - * - * @param entry TLB Entry index. - * @param value Value to be written. - */ -NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value) -{ - itlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_entry = entry; - asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); - flush_pipeline(); -} - -/** Read DMMU TLB Data Access Register. - * - * @param entry TLB Entry index. - * - * @return Current value of specified DMMU TLB Data Access - * Register. - */ -NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry) -{ - dtlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_entry = entry; - return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); -} - -/** Write DMMU TLB Data Access Register. - * - * @param entry TLB Entry index. - * @param value Value to be written. - */ -NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value) -{ - dtlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_entry = entry; - asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); - membar(); -} - -/** Read IMMU TLB Tag Read Register. - * - * @param entry TLB Entry index. - * - * @return Current value of specified IMMU TLB Tag Read Register. - */ -NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry) -{ - itlb_tag_read_addr_t tag; - - tag.value = 0; - tag.tlb_entry = entry; - return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); -} - -/** Read DMMU TLB Tag Read Register. - * - * @param entry TLB Entry index. - * - * @return Current value of specified DMMU TLB Tag Read Register. - */ -NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry) -{ - dtlb_tag_read_addr_t tag; - - tag.value = 0; - tag.tlb_entry = entry; - return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); -} - -#elif defined (US3) - - -/** Read IMMU TLB Data Access Register. - * - * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) - * @param entry TLB Entry index. - * - * @return Current value of specified IMMU TLB Data Access - * Register. - */ -NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry) -{ - itlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_number = tlb; - reg.local_tlb_entry = entry; - return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); -} - -/** Write IMMU TLB Data Access Register. - * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) - * @param entry TLB Entry index. - * @param value Value to be written. - */ -NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry, - uint64_t value) -{ - itlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_number = tlb; - reg.local_tlb_entry = entry; - asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); - flush_pipeline(); -} - -/** Read DMMU TLB Data Access Register. - * - * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG) - * @param entry TLB Entry index. - * - * @return Current value of specified DMMU TLB Data Access - * Register. - */ -NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry) -{ - dtlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_number = tlb; - reg.local_tlb_entry = entry; - return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); -} - -/** Write DMMU TLB Data Access Register. - * - * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) - * @param entry TLB Entry index. - * @param value Value to be written. - */ -NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry, - uint64_t value) -{ - dtlb_data_access_addr_t reg; - - reg.value = 0; - reg.tlb_number = tlb; - reg.local_tlb_entry = entry; - asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); - membar(); -} - -/** Read IMMU TLB Tag Read Register. - * - * @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG) - * @param entry TLB Entry index. - * - * @return Current value of specified IMMU TLB Tag Read Register. - */ -NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry) -{ - itlb_tag_read_addr_t tag; - - tag.value = 0; - tag.tlb_number = tlb; - tag.local_tlb_entry = entry; - return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); -} - -/** Read DMMU TLB Tag Read Register. - * - * @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1) - * @param entry TLB Entry index. - * - * @return Current value of specified DMMU TLB Tag Read Register. - */ -NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry) -{ - dtlb_tag_read_addr_t tag; - - tag.value = 0; - tag.tlb_number = tlb; - tag.local_tlb_entry = entry; - return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); -} - -#endif - - -/** Write IMMU TLB Tag Access Register. - * - * @param v Value to be written. - */ -NO_TRACE static inline void itlb_tag_access_write(uint64_t v) -{ - asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); - flush_pipeline(); -} - -/** Read IMMU TLB Tag Access Register. - * - * @return Current value of IMMU TLB Tag Access Register. - */ -NO_TRACE static inline uint64_t itlb_tag_access_read(void) -{ - return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); -} - -/** Write DMMU TLB Tag Access Register. - * - * @param v Value to be written. - */ -NO_TRACE static inline void dtlb_tag_access_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); - membar(); -} - -/** Read DMMU TLB Tag Access Register. - * - * @return Current value of DMMU TLB Tag Access Register. - */ -NO_TRACE static inline uint64_t dtlb_tag_access_read(void) -{ - return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); -} - - -/** Write IMMU TLB Data in Register. - * - * @param v Value to be written. - */ -NO_TRACE static inline void itlb_data_in_write(uint64_t v) -{ - asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); - flush_pipeline(); -} - -/** Write DMMU TLB Data in Register. - * - * @param v Value to be written. - */ -NO_TRACE static inline void dtlb_data_in_write(uint64_t v) -{ - asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); - membar(); -} - -/** Read ITLB Synchronous Fault Status Register. - * - * @return Current content of I-SFSR register. - */ -NO_TRACE static inline uint64_t itlb_sfsr_read(void) -{ - return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); -} - -/** Write ITLB Synchronous Fault Status Register. - * - * @param v New value of I-SFSR register. - */ -NO_TRACE static inline void itlb_sfsr_write(uint64_t v) -{ - asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); - flush_pipeline(); -} - -/** Read DTLB Synchronous Fault Status Register. - * - * @return Current content of D-SFSR register. - */ -NO_TRACE static inline uint64_t dtlb_sfsr_read(void) -{ - return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); -} - -/** Write DTLB Synchronous Fault Status Register. - * - * @param v New value of D-SFSR register. - */ -NO_TRACE static inline void dtlb_sfsr_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); - membar(); -} - -/** Read DTLB Synchronous Fault Address Register. - * - * @return Current content of D-SFAR register. - */ -NO_TRACE static inline uint64_t dtlb_sfar_read(void) -{ - return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); -} - -/** Perform IMMU TLB Demap Operation. - * - * @param type Selects between context and page demap (and entire MMU - * demap on US3). - * @param context_encoding Specifies which Context register has Context ID for - * demap. - * @param page Address which is on the page to be demapped. - */ -NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page) -{ - tlb_demap_addr_t da; - page_address_t pg; - - da.value = 0; - pg.address = page; - - da.type = type; - da.context = context_encoding; - da.vpn = pg.vpn; - - /* da.value is the address within the ASI */ - asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); - - flush_pipeline(); -} - -/** Perform DMMU TLB Demap Operation. - * - * @param type Selects between context and page demap (and entire MMU - * demap on US3). - * @param context_encoding Specifies which Context register has Context ID for - * demap. - * @param page Address which is on the page to be demapped. - */ -NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) -{ - tlb_demap_addr_t da; - page_address_t pg; - - da.value = 0; - pg.address = page; - - da.type = type; - da.context = context_encoding; - da.vpn = pg.vpn; - - /* da.value is the address within the ASI */ - asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); - - membar(); -} - -extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *); -extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *); -extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *); - -extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); - -extern void dump_sfsr_and_sfar(void); -extern void describe_dmmu_fault(void); - -#endif /* !def __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4u/tsb.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4u/tsb.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,172 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4u_TSB_H_ -#define KERN_sparc64_sun4u_TSB_H_ - -/* - * ITSB abd DTSB will claim 64K of memory, which - * is a nice number considered that it is one of - * the page sizes supported by hardware, which, - * again, is nice because TSBs need to be locked - * in TLBs - only one TLB entry will do. - */ -#define TSB_SIZE 2 /* when changing this, change - * as.c as well */ -#define ITSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) -#define DTSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) - -#define TSB_TAG_TARGET_CONTEXT_SHIFT 48 - -#ifndef __ASM__ - -#include -#include -#include - -/** TSB Base register. */ -typedef union tsb_base_reg { - uint64_t value; - struct { - uint64_t base : 51; /**< TSB base address, bits 63:13. */ - unsigned split : 1; /**< Split vs. common TSB for 8K and 64K - * pages. HelenOS uses only 8K pages - * for user mappings, so we always set - * this to 0. - */ - unsigned : 9; - unsigned size : 3; /**< TSB size. Number of entries is - * 512 * 2^size. */ - } __attribute__ ((packed)); -} tsb_base_reg_t; - -/** Read ITSB Base register. - * - * @return Content of the ITSB Base register. - */ -static inline uint64_t itsb_base_read(void) -{ - return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE); -} - -/** Read DTSB Base register. - * - * @return Content of the DTSB Base register. - */ -static inline uint64_t dtsb_base_read(void) -{ - return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE); -} - -/** Write ITSB Base register. - * - * @param v New content of the ITSB Base register. - */ -static inline void itsb_base_write(uint64_t v) -{ - asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v); -} - -/** Write DTSB Base register. - * - * @param v New content of the DTSB Base register. - */ -static inline void dtsb_base_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v); -} - -#if defined (US3) - -/** Write DTSB Primary Extension register. - * - * @param v New content of the DTSB Primary Extension register. - */ -static inline void dtsb_primary_extension_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_DMMU_PRIMARY_EXTENSION, v); -} - -/** Write DTSB Secondary Extension register. - * - * @param v New content of the DTSB Secondary Extension register. - */ -static inline void dtsb_secondary_extension_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_DMMU_SECONDARY_EXTENSION, v); -} - -/** Write DTSB Nucleus Extension register. - * - * @param v New content of the DTSB Nucleus Extension register. - */ -static inline void dtsb_nucleus_extension_write(uint64_t v) -{ - asi_u64_write(ASI_DMMU, VA_DMMU_NUCLEUS_EXTENSION, v); -} - -/** Write ITSB Primary Extension register. - * - * @param v New content of the ITSB Primary Extension register. - */ -static inline void itsb_primary_extension_write(uint64_t v) -{ - asi_u64_write(ASI_IMMU, VA_IMMU_PRIMARY_EXTENSION, v); -} - -/** Write ITSB Nucleus Extension register. - * - * @param v New content of the ITSB Nucleus Extension register. - */ -static inline void itsb_nucleus_extension_write(uint64_t v) -{ - asi_u64_write(ASI_IMMU, VA_IMMU_NUCLEUS_EXTENSION, v); -} - -#endif - -/* Forward declarations. */ -struct as; -struct pte; - -extern void tsb_invalidate(struct as *as, uintptr_t page, size_t pages); -extern void itsb_pte_copy(struct pte *t, size_t index); -extern void dtsb_pte_copy(struct pte *t, size_t index, bool ro); - -#endif /* !def __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4u/tte.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4u/tte.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,104 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4u_TTE_H_ -#define KERN_sparc64_sun4u_TTE_H_ - -#define TTE_G (1 << 0) -#define TTE_W (1 << 1) -#define TTE_P (1 << 2) -#define TTE_E (1 << 3) -#define TTE_CV (1 << 4) -#define TTE_CP (1 << 5) -#define TTE_L (1 << 6) - -#define TTE_V_SHIFT 63 -#define TTE_SIZE_SHIFT 61 - -#ifndef __ASM__ - -#include - -/* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */ -#define VA_TAG_PAGE_SHIFT 22 - -/** Translation Table Entry - Tag. */ -union tte_tag { - uint64_t value; - struct { - unsigned g : 1; /**< Global. */ - unsigned : 2; /**< Reserved. */ - unsigned context : 13; /**< Context identifier. */ - unsigned : 6; /**< Reserved. */ - uint64_t va_tag : 42; /**< Virtual Address Tag, bits 63:22. */ - } __attribute__ ((packed)); -}; - -typedef union tte_tag tte_tag_t; - -/** Translation Table Entry - Data. */ -union tte_data { - uint64_t value; - struct { - unsigned v : 1; /**< Valid. */ - unsigned size : 2; /**< Page size of this entry. */ - unsigned nfo : 1; /**< No-Fault-Only. */ - unsigned ie : 1; /**< Invert Endianness. */ - unsigned soft2 : 9; /**< Software defined field. */ -#if defined (US) - unsigned diag : 9; /**< Diagnostic data. */ - unsigned pfn : 28; /**< Physical Address bits, bits 40:13. */ -#elif defined (US3) - unsigned : 7; /**< Reserved. */ - unsigned pfn : 30; /**< Physical Address bits, bits 42:13 */ -#endif - unsigned soft : 6; /**< Software defined field. */ - unsigned l : 1; /**< Lock. */ - unsigned cp : 1; /**< Cacheable in physically indexed cache. */ - unsigned cv : 1; /**< Cacheable in virtually indexed cache. */ - unsigned e : 1; /**< Side-effect. */ - unsigned p : 1; /**< Privileged. */ - unsigned w : 1; /**< Writable. */ - unsigned g : 1; /**< Global. */ - } __attribute__ ((packed)); -}; - -typedef union tte_data tte_data_t; - -#endif /* !def __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4v/as.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/as.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,100 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * Copyright (c) 2009 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_AS_H_ -#define KERN_sparc64_sun4v_AS_H_ - -#include -#include - -#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1 - -#define KERNEL_ADDRESS_SPACE_START_ARCH UINT64_C(0x0000000000000000) -#define KERNEL_ADDRESS_SPACE_END_ARCH UINT64_C(0xffffffffffffffff) -#define USER_ADDRESS_SPACE_START_ARCH UINT64_C(0x0000000000000000) -#define USER_ADDRESS_SPACE_END_ARCH UINT64_C(0xffffffffffffffff) - -#ifdef CONFIG_TSB - -/** - * TTE Tag. - * - * Even though for sun4v the format of the TSB Tag states that the context - * field has 16 bits, the T1 CPU still only supports 13-bit contexts and the - * three most significant bits are always zero. - */ -typedef union tte_tag { - uint64_t value; - struct { - unsigned : 3; - unsigned context : 13; /**< Software ASID. */ - unsigned : 6; - uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ - } __attribute__ ((packed)); -} tte_tag_t; - -/** TSB entry. */ -typedef struct tsb_entry { - tte_tag_t tag; - tte_data_t data; -} __attribute__ ((packed)) tsb_entry_t; - -typedef struct { - tsb_descr_t tsb_description; -} as_arch_t; - -#else - -typedef struct { -} as_arch_t; - -#endif /* CONFIG_TSB */ - -#include - -#ifdef CONFIG_TSB -#include -#define as_invalidate_translation_cache(as, page, cnt) \ - tsb_invalidate((as), (page), (cnt)) -#else -#define as_invalidate_translation_cache(as, page, cnt) -#endif - -extern void as_arch_init(void); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4v/frame.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/frame.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,57 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_FRAME_H_ -#define KERN_sparc64_sun4v_FRAME_H_ - -#define MMU_FRAME_WIDTH 13 /* 8K */ -#define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) - -#define FRAME_WIDTH 13 -#define FRAME_SIZE (1 << FRAME_WIDTH) - -#ifndef __ASM__ - -#include - -extern void frame_low_arch_init(void); -extern void frame_high_arch_init(void); -#define physmem_print() - -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4v/km.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/km.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,58 +1,0 @@ -/* - * Copyright (c) 2011 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_KM_H_ -#define KERN_sparc64_sun4v_KM_H_ - -#include - -/* - * Do not use the 4 GiB area on either side of the VA hole to meet the - * limitations of the UltraSPARC T1 CPU. - */ - -#define KM_SPARC64_T1_IDENTITY_START UINT64_C(0x0000000000000000) -#define KM_SPARC64_T1_IDENTITY_SIZE UINT64_C(0x00007fff00000000) - -#define KM_SPARC64_T1_NON_IDENTITY_START UINT64_C(0xffff800100000000) -#define KM_SPARC64_T1_NON_IDENTITY_SIZE UINT64_C(0x00007fff00000000) - -extern void km_identity_arch_init(void); -extern void km_non_identity_arch_init(void); -extern bool km_is_non_identity_arch(uintptr_t); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4v/mmu.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/mmu.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,50 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * Copyright (c) 2008 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_MMU_H_ -#define KERN_sparc64_sun4v_MMU_H_ - -#define ASI_REAL 0x14 /**< MMU bypass ASI */ - -#define VA_PRIMARY_CONTEXT_REG 0x8 /**< primary context register VA. */ -#define ASI_PRIMARY_CONTEXT_REG 0x21 /**< primary context register ASI. */ - -#define VA_SECONDARY_CONTEXT_REG 0x10 /**< secondary context register VA. */ -#define ASI_SECONDARY_CONTEXT_REG 0x21 /**< secondary context register ASI. */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4v/page.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/page.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,72 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_PAGE_H_ -#define KERN_sparc64_sun4v_PAGE_H_ - -#include - -#define MMU_PAGE_WIDTH MMU_FRAME_WIDTH -#define MMU_PAGE_SIZE MMU_FRAME_SIZE - -#define PAGE_WIDTH FRAME_WIDTH -#define PAGE_SIZE FRAME_SIZE - -#define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) - -#ifndef __ASM__ - -#include - -extern uintptr_t physmem_base; - -#define KA2PA(x) (((uintptr_t) (x)) + physmem_base) -#define PA2KA(x) (((uintptr_t) (x)) - physmem_base) - -typedef union { - uintptr_t address; - struct { - uint64_t vpn : 51; /**< Virtual Page Number. */ - unsigned offset : 13; /**< Offset. */ - } __attribute__ ((packed)); -} page_address_t; - -extern void page_arch_init(void); - -#endif /* !def __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4v/tlb.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/tlb.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,156 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * Copyright (c) 2008 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_TLB_H_ -#define KERN_sparc64_sun4v_TLB_H_ - -#define MMU_FSA_ALIGNMENT 64 -#define MMU_FSA_SIZE 128 - -#ifndef __ASM__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/** - * Structure filled by hypervisor (or directly CPU, if implemented so) when - * a MMU fault occurs. The structure describes the exact condition which - * has caused the fault. - */ -typedef struct mmu_fault_status_area { - uint64_t ift; /**< Instruction fault type (IFT) */ - uint64_t ifa; /**< Instruction fault address (IFA) */ - uint64_t ifc; /**< Instruction fault context (IFC) */ - uint8_t reserved1[0x28]; - - uint64_t dft; /**< Data fault type (DFT) */ - uint64_t dfa; /**< Data fault address (DFA) */ - uint64_t dfc; /**< Data fault context (DFC) */ - uint8_t reserved2[0x28]; -} __attribute__ ((packed)) mmu_fault_status_area_t; - -#define DTLB_MAX_LOCKED_ENTRIES 8 - -/** Bit width of the TLB-locked portion of kernel address space. */ -#define KERNEL_PAGE_WIDTH 22 /* 4M */ - -/* - * Reading and writing context registers. - * - * Note that UltraSPARC Architecture-compatible processors do not require - * a MEMBAR #Sync, FLUSH, DONE, or RETRY instruction after a store to an - * MMU register for proper operation. - * - */ - -/** Read MMU Primary Context Register. - * - * @return Current value of Primary Context Register. - */ -NO_TRACE static inline uint64_t mmu_primary_context_read(void) -{ - return asi_u64_read(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG); -} - -/** Write MMU Primary Context Register. - * - * @param v New value of Primary Context Register. - */ -NO_TRACE static inline void mmu_primary_context_write(uint64_t v) -{ - asi_u64_write(ASI_PRIMARY_CONTEXT_REG, VA_PRIMARY_CONTEXT_REG, v); -} - -/** Read MMU Secondary Context Register. - * - * @return Current value of Secondary Context Register. - */ -NO_TRACE static inline uint64_t mmu_secondary_context_read(void) -{ - return asi_u64_read(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG); -} - -/** Write MMU Secondary Context Register. - * - * @param v New value of Secondary Context Register. - */ -NO_TRACE static inline void mmu_secondary_context_write(uint64_t v) -{ - asi_u64_write(ASI_SECONDARY_CONTEXT_REG, VA_SECONDARY_CONTEXT_REG, v); -} - -/** - * Demaps all mappings in a context. - * - * @param context number of the context - * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both - */ -NO_TRACE static inline void mmu_demap_ctx(int context, int mmu_flag) { - __hypercall_fast4(MMU_DEMAP_CTX, 0, 0, context, mmu_flag); -} - -/** - * Demaps given page. - * - * @param vaddr VA of the page to be demapped - * @param context number of the context - * @param mmu_flag MMU_FLAG_DTLB, MMU_FLAG_ITLB or a combination of both - */ -NO_TRACE static inline void mmu_demap_page(uintptr_t vaddr, int context, int mmu_flag) { - __hypercall_fast5(MMU_DEMAP_PAGE, 0, 0, vaddr, context, mmu_flag); -} - -extern void fast_instruction_access_mmu_miss(sysarg_t, istate_t *); -extern void fast_data_access_mmu_miss(sysarg_t, istate_t *); -extern void fast_data_access_protection(sysarg_t, istate_t *); - -extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool); - -extern void describe_dmmu_fault(void); - -#endif /* !def __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4v/tsb.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/tsb.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,81 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * Copyright (c) 2009 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_TSB_H_ -#define KERN_sparc64_sun4v_TSB_H_ - -/* - * TSB will claim 64K of memory, which - * is a nice number considered that it is one of - * the page sizes supported by hardware, which, - * again, is nice because TSBs need to be locked - * in TLBs - only one TLB entry will do. - */ -#define TSB_SIZE 3 /* when changing this, change - * as.c as well */ -#define TSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) - -#ifndef __ASM__ - -#include -#include -#include - -/** TSB description, used in hypercalls */ -typedef struct tsb_descr { - uint16_t page_size; /**< Page size (0 = 8K, 1 = 64K,...). */ - uint16_t associativity; /**< TSB associativity (will be 1). */ - uint32_t num_ttes; /**< Number of TTEs. */ - uint32_t context; /**< Context number. */ - uint32_t pgsize_mask; /**< Equals "1 << page_size". */ - uint64_t tsb_base; /**< Real address of TSB base. */ - uint64_t reserved; -} __attribute__ ((packed)) tsb_descr_t; - - -/* Forward declarations. */ -struct as; -struct pte; - -extern void tsb_invalidate(struct as *as, uintptr_t page, uint64_t pages); -extern void itsb_pte_copy(struct pte *t); -extern void dtsb_pte_copy(struct pte *t, bool ro); - -#endif /* !def __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/sun4v/tte.h =================================================================== --- kernel/arch/sparc64/include/mm/sun4v/tte.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,83 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_TTE_H_ -#define KERN_sparc64_sun4v_TTE_H_ - -#define TTE_V_SHIFT 63 /**< valid */ -#define TTE_TADDR_SHIFT 13 /**< target address */ -#define TTE_CP_SHIFT 10 /**< cacheable physically */ -#define TTE_CV_SHIFT 9 /**< caheable virtually */ -#define TTE_P_SHIFT 8 /**< privileged */ -#define TTE_EP_SHIFT 7 /**< execute permission */ -#define TTE_W_SHIFT 6 /**< writable */ -#define TTE_SZ_SHIFT 0 /**< size */ - -#define MMU_FLAG_ITLB 2 /**< operation applies to ITLB */ -#define MMU_FLAG_DTLB 1 /**< operation applies to DTLB */ - -#ifndef __ASM__ - -#include - -/** Translation Table Entry - Data. */ -union tte_data { - uint64_t value; - struct { - unsigned v : 1; /**< Valid. */ - unsigned nfo : 1; /**< No-Fault-Only. */ - unsigned soft : 6; /**< Software defined field. */ - unsigned long ra : 43; /**< Real address. */ - unsigned ie : 1; /**< Invert endianess. */ - unsigned e : 1; /**< Side-effect. */ - unsigned cp : 1; /**< Cacheable in physically indexed cache. */ - unsigned cv : 1; /**< Cacheable in virtually indexed cache. */ - unsigned p : 1; /**< Privileged. */ - unsigned x : 1; /**< Executable. */ - unsigned w : 1; /**< Writable. */ - unsigned soft2 : 2; /**< Software defined field. */ - unsigned size : 4; /**< Page size. */ - } __attribute__ ((packed)); -}; - -typedef union tte_data tte_data_t; - -#define VA_TAG_PAGE_SHIFT 22 - -#endif /* !def __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/tlb.h =================================================================== --- kernel/arch/sparc64/include/mm/tlb.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,51 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_TLB_H_ -#define KERN_sparc64_TLB_H_ - -#if defined (SUN4U) - -#include - -#elif defined (SUN4V) - -#include - -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/tsb.h =================================================================== --- kernel/arch/sparc64/include/mm/tsb.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,47 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_TSB_H_ -#define KERN_sparc64_TSB_H_ - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/mm/tte.h =================================================================== --- kernel/arch/sparc64/include/mm/tte.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,47 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64mm - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_TTE_H_ -#define KERN_sparc64_TTE_H_ - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/proc/task.h =================================================================== --- kernel/arch/sparc64/include/proc/task.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,47 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64proc - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_TASK_H_ -#define KERN_sparc64_TASK_H_ - -typedef struct { -} task_arch_t; - -#define task_create_arch(t) -#define task_destroy_arch(t) - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/proc/thread.h =================================================================== --- kernel/arch/sparc64/include/proc/thread.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,49 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64proc - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_THREAD_H_ -#define KERN_sparc64_THREAD_H_ - -#include -#include - -typedef struct { - /** Buffer for register windows with userspace content. */ - uint8_t *uspace_window_buffer; -} thread_arch_t; - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/regdef.h =================================================================== --- kernel/arch/sparc64/include/regdef.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,67 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_REGDEF_H_ -#define KERN_sparc64_REGDEF_H_ - -#define PSTATE_IE_BIT (1 << 1) -#define PSTATE_AM_BIT (1 << 3) - -#define PSTATE_AG_BIT (1 << 0) -#define PSTATE_IG_BIT (1 << 11) -#define PSTATE_MG_BIT (1 << 10) - -#define PSTATE_PRIV_BIT (1 << 2) -#define PSTATE_PEF_BIT (1 << 4) - -#define TSTATE_PSTATE_SHIFT 8 -#define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT << TSTATE_PSTATE_SHIFT) -#define TSTATE_IE_BIT (PSTATE_IE_BIT << TSTATE_PSTATE_SHIFT) -#define TSTATE_PEF_BIT (PSTATE_PEF_BIT << TSTATE_PSTATE_SHIFT) - -#define TSTATE_CWP_MASK 0x1f - -#define WSTATE_NORMAL(n) (n) -#define WSTATE_OTHER(n) ((n) << 3) - -/* - * The following definitions concern the UPA_CONFIG register on US and the - * FIREPLANE_CONFIG register on US3. - */ -#define ICBUS_CONFIG_MID_SHIFT 17 - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/register.h =================================================================== --- kernel/arch/sparc64/include/register.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,123 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_REGISTER_H_ -#define KERN_sparc64_REGISTER_H_ - -#include -#include - -/** Version Register. */ -union ver_reg { - uint64_t value; - struct { - uint16_t manuf; /**< Manufacturer code. */ - uint16_t impl; /**< Implementation code. */ - uint8_t mask; /**< Mask set revision. */ - unsigned : 8; - uint8_t maxtl; - unsigned : 3; - unsigned maxwin : 5; - } __attribute__ ((packed)); -}; -typedef union ver_reg ver_reg_t; - -/** Processor State Register. */ -union pstate_reg { - uint64_t value; - struct { - uint64_t : 52; - unsigned ig : 1; /**< Interrupt Globals. */ - unsigned mg : 1; /**< MMU Globals. */ - unsigned cle : 1; /**< Current Little Endian. */ - unsigned tle : 1; /**< Trap Little Endian. */ - unsigned mm : 2; /**< Memory Model. */ - unsigned red : 1; /**< RED state. */ - unsigned pef : 1; /**< Enable floating-point. */ - unsigned am : 1; /**< 32-bit Address Mask. */ - unsigned priv : 1; /**< Privileged Mode. */ - unsigned ie : 1; /**< Interrupt Enable. */ - unsigned ag : 1; /**< Alternate Globals*/ - } __attribute__ ((packed)); -}; -typedef union pstate_reg pstate_reg_t; - -/** TICK Register. */ -union tick_reg { - uint64_t value; - struct { - unsigned npt : 1; /**< Non-privileged Trap enable. */ - uint64_t counter : 63; /**< Elapsed CPU clck cycle counter. */ - } __attribute__ ((packed)); -}; -typedef union tick_reg tick_reg_t; - -/** TICK_compare Register. */ -union tick_compare_reg { - uint64_t value; - struct { - unsigned int_dis : 1; /**< TICK_INT interrupt disabled flag. */ - uint64_t tick_cmpr : 63; /**< Compare value for TICK interrupts. */ - } __attribute__ ((packed)); -}; -typedef union tick_compare_reg tick_compare_reg_t; - -/** SOFTINT Register. */ -union softint_reg { - uint64_t value; - struct { - uint64_t : 47; - unsigned stick_int : 1; - unsigned int_level : 15; - unsigned tick_int : 1; - } __attribute__ ((packed)); -}; -typedef union softint_reg softint_reg_t; - -/** Floating-point Registers State Register. */ -union fprs_reg { - uint64_t value; - struct { - uint64_t : 61; - unsigned fef : 1; - unsigned du : 1; - unsigned dl : 1; - } __attribute__ ((packed)); -}; -typedef union fprs_reg fprs_reg_t; - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/smp/sun4v/smp.h =================================================================== --- kernel/arch/sparc64/include/smp/sun4v/smp.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,48 +1,0 @@ -/* - * Copyright (c) 2009 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** - * @file - * @brief sun4v smp functions - */ - -#ifndef KERN_sparc64_sun4v_SMP_H_ -#define KERN_sparc64_sun4v_SMP_H_ - -#include -#include - -extern bool calculate_optimal_nrdy(exec_unit_t *); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/sparc64.h =================================================================== --- kernel/arch/sparc64/include/sparc64.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,45 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_SPARC64_H_ -#define KERN_sparc64_SPARC64_H_ - -#include - -extern void interrupt_register(unsigned int, const char *, iroutine_t); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/stack.h =================================================================== --- kernel/arch/sparc64/include/stack.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,72 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_STACK_H_ -#define KERN_sparc64_STACK_H_ - -#define STACK_ITEM_SIZE 8 - -/** According to SPARC Compliance Definition, every stack frame is 16-byte aligned. */ -#define STACK_ALIGNMENT 16 - -/** - * 16-extended-word save area for %i[0-7] and %l[0-7] registers. - */ -#define STACK_WINDOW_SAVE_AREA_SIZE (16 * STACK_ITEM_SIZE) - -/** - * Six extended words for first six arguments. - */ -#define STACK_ARG_SAVE_AREA_SIZE (6 * STACK_ITEM_SIZE) - -/** - * By convention, the actual top of the stack is %sp + STACK_BIAS. - */ -#define STACK_BIAS 2047 - -/* - * Offsets of arguments on stack. - */ -#define STACK_ARG0 0 -#define STACK_ARG1 8 -#define STACK_ARG2 16 -#define STACK_ARG3 24 -#define STACK_ARG4 32 -#define STACK_ARG5 40 -#define STACK_ARG6 48 - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/sun4u/arch.h =================================================================== --- kernel/arch/sparc64/include/sun4u/arch.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,47 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** - * @file - * @brief Various sun4u-specific macros. - */ - -#ifndef KERN_sparc64_sun4u_ARCH_H_ -#define KERN_sparc64_sun4u_ARCH_H_ - -#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ -#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ -#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/sun4u/asm.h =================================================================== --- kernel/arch/sparc64/include/sun4u/asm.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,65 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4u_ASM_H_ -#define KERN_sparc64_sun4u_ASM_H_ - -#include - -/** Read Version Register. - * - * @return Value of VER register. - * - */ -NO_TRACE static inline uint64_t ver_read(void) -{ - uint64_t v; - - asm volatile ( - "rdpr %%ver, %[v]\n" - : [v] "=r" (v) - ); - - return v; -} - -extern uint64_t read_from_ag_g7(void); -extern void write_to_ag_g6(uint64_t); -extern void write_to_ag_g7(uint64_t); -extern void write_to_ig_g6(uint64_t); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/sun4u/cpu.h =================================================================== --- kernel/arch/sparc64/include/sun4u/cpu.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,95 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4u_CPU_H_ -#define KERN_sparc64_sun4u_CPU_H_ - -#define MANUF_FUJITSU 0x04 -#define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */ -#define MANUF_SUN 0x3e - -#define IMPL_ULTRASPARCI 0x10 -#define IMPL_ULTRASPARCII 0x11 -#define IMPL_ULTRASPARCII_I 0x12 -#define IMPL_ULTRASPARCII_E 0x13 -#define IMPL_ULTRASPARCIII 0x14 -#define IMPL_ULTRASPARCIII_PLUS 0x15 -#define IMPL_ULTRASPARCIII_I 0x16 -#define IMPL_ULTRASPARCIV 0x18 -#define IMPL_ULTRASPARCIV_PLUS 0x19 - -#define IMPL_SPARC64V 0x5 - -#ifndef __ASM__ - -#include -#include -#include -#include -#include - -typedef struct { - uint32_t mid; /**< Processor ID as read from - UPA_CONFIG/FIREPLANE_CONFIG. */ - ver_reg_t ver; - uint32_t clock_frequency; /**< Processor frequency in Hz. */ - uint64_t next_tick_cmpr; /**< Next clock interrupt should be - generated when the TICK register - matches this value. */ -} cpu_arch_t; - -/** Read the module ID (agent ID/CPUID) of the current CPU. - * - */ -NO_TRACE static inline uint32_t read_mid(void) -{ - uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0); - icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT; - -#if defined (US) - return icbus_config & 0x1f; -#elif defined (US3) - if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I) - return icbus_config & 0x1f; - else - return icbus_config & 0x3ff; -#endif -} - -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/sun4v/arch.h =================================================================== --- kernel/arch/sparc64/include/sun4v/arch.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,63 +1,0 @@ -/* - * Copyright (c) 2009 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** - * @file - * @brief Various sun4v-specific macros. - */ - -#ifndef KERN_sparc64_sun4v_ARCH_H_ -#define KERN_sparc64_sun4v_ARCH_H_ - -/* scratch pad registers ASI */ -#define ASI_SCRATCHPAD 0x20 - -/* - * Assignment of scratchpad register virtual addresses. The same convention is - * used by both Linux and Solaris. - */ - -/* register where the address of the MMU fault status area will be stored */ -#define SCRATCHPAD_MMU_FSA 0x00 - -/* register where the CPUID will be stored */ -#define SCRATCHPAD_CPUID 0x08 - -/* register where the kernel stack address will be stored */ -#define SCRATCHPAD_KSTACK 0x10 - -/* register where the userspace window buffer address will be stored */ -#define SCRATCHPAD_WBUF 0x18 - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/sun4v/asm.h =================================================================== --- kernel/arch/sparc64/include/sun4v/asm.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,41 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_ASM_H_ -#define KERN_sparc64_sun4v_ASM_H_ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/sun4v/cpu.h =================================================================== --- kernel/arch/sparc64/include/sun4v/cpu.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,76 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_CPU_H_ -#define KERN_sparc64_sun4v_CPU_H_ - -/** Maximum number of virtual processors. */ -#define MAX_NUM_STRANDS 64 - -/** Maximum number of logical processors in a processor core */ -#define MAX_CORE_STRANDS 8 - -#ifndef __ASM__ - -#include -#include - -struct cpu; - -typedef struct { - uint64_t exec_unit_id; - uint8_t strand_count; - uint64_t cpuids[MAX_CORE_STRANDS]; - struct cpu *cpus[MAX_CORE_STRANDS]; - atomic_t nrdy; - SPINLOCK_DECLARE(proposed_nrdy_lock); -} exec_unit_t; - -typedef struct cpu_arch { - uint64_t id; /**< virtual processor ID */ - uint32_t clock_frequency; /**< Processor frequency in Hz. */ - uint64_t next_tick_cmpr; /**< Next clock interrupt should be - generated when the TICK register - matches this value. */ - exec_unit_t *exec_unit; /**< Physical core. */ - unsigned long proposed_nrdy; /**< Proposed No. of ready threads - so that cores are equally balanced. */ -} cpu_arch_t; - -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/sun4v/hypercall.h =================================================================== --- kernel/arch/sparc64/include/sun4v/hypercall.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,250 +1,0 @@ -/* - * Copyright (c) 2008 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** - * @file - * @brief Macros, constants and functions needed to perform a call to the - * hypervisor API. For details and terminology see this document: - * UltraSPARC Virtual Machine Specification (The Hypervisor API - * specification for Logical Domains). - * - */ - -#ifndef KERN_sparc64_sun4v_HYPERCALL_H_ -#define KERN_sparc64_sun4v_HYPERCALL_H_ - -/* SW trap numbers for hyperfast traps */ -#define FAST_TRAP 0x80 -#define MMU_MAP_ADDR 0x83 -#define MMU_UNMAP_ADDR 0x84 - -/* function codes for fast traps */ -#define MACH_DESC 0x01 -#define CPU_START 0x10 -#define CPU_STOP 0x11 -#define CPU_YIELD 0x12 -#define CPU_QCONF 0x14 -#define CPU_MYID 0x16 -#define CPU_STATE 0x17 -#define CPU_SET_RTBA 0x18 -#define CPU_GET_RTBA 0x19 -#define MMU_TSB_CTX0 0x20 -#define MMU_TSB_CTXNON0 0x21 -#define MMU_DEMAP_PAGE 0x22 -#define MMU_DEMAP_CTX 0x23 -#define MMU_DEMAP_ALL 0x24 -#define MMU_MAP_PERM_ADDR 0x25 -#define MMU_FAULT_AREA_CONF 0x26 -#define MMU_ENABLE 0x27 -#define MMU_UNMAP_PERM_ADDR 0x28 -#define MMU_TSB_CTX0_INFO 0x29 -#define MMU_TSB_CTXNON0_INFO 0x2a -#define MMU_FAULT_AREA_INFO 0x2b -#define CPU_MONDO_SEND 0x42 -#define CONS_GETCHAR 0x60 -#define CONS_PUTCHAR 0x61 - - -/* return codes */ -#define HV_EOK 0 /**< Successful return */ -#define HV_ENOCPU 1 /**< Invalid CPU id */ -#define HV_ENORADDR 2 /**< Invalid real address */ -#define HV_ENOINTR 3 /**< Invalid interrupt id */ -#define HV_EBADPGSZ 4 /**< Invalid pagesize encoding */ -#define HV_EBADTSB 5 /**< Invalid TSB description */ -#define HV_EINVAL 6 /**< Invalid argument */ -#define HV_EBADTRAP 7 /**< Invalid function number */ -#define HV_EBADALIGN 8 /**< Invalid address alignment */ -#define HV_EWOULDBLOCK 9 /**< Cannot complete operation without blocking */ -#define HV_ENOACCESS 10 /**< No access to specified resource */ -#define HV_EIO 11 /**< I/O Error */ -#define HV_ECPUERROR 12 /**< CPU is in error state */ -#define HV_ENOTSUPPORTED 13 /**< Function not supported */ -#define HV_ENOMAP 14 /**< No mapping found */ -#define HV_ETOOMANY 15 /**< Too many items specified / limit reached */ -#define HV_ECHANNEL 16 /**< Invalid LDC channel */ -#define HV_EBUSY 17 /**< Operation failed as resource is otherwise busy */ - - -/** - * Performs a hyperfast hypervisor API call from the assembly language code. - * Expects the registers %o1-%o4 are properly filled with the arguments of the - * call. - * - * @param function_number hyperfast call function number - */ -#define __HYPERCALL_FAST(function_number) \ - set function_number, %o5; \ - ta FAST_TRAP; - -/** - * Performs a fast hypervisor API call from the assembly language code. - * Expects the registers %o1-%o4 are properly filled with the arguments of the - * call. - * - * @param sw_trap_number software trap number - */ -#define __HYPERCALL_HYPERFAST(sw_trap_number) \ - ta (sw_trap_number); - - -#ifndef __ASM__ - -#include - -/* - * Macros to be used from the C-language code; __hypercall_fastN performs - * a fast hypervisor API call taking exactly N arguments. - */ - -#define __hypercall_fast0(function_number) \ - __hypercall_fast(0, 0, 0, 0, 0, function_number) -#define __hypercall_fast1(function_number, p1) \ - __hypercall_fast(p1, 0, 0, 0, 0, function_number) -#define __hypercall_fast2(function_number, p1, p2) \ - __hypercall_fast(p1, p2, 0, 0, 0, function_number) -#define __hypercall_fast3(function_number, p1, p2, p3) \ - __hypercall_fast(p1, p2, p3, 0, 0, function_number) -#define __hypercall_fast4(function_number, p1, p2, p3, p4) \ - __hypercall_fast(p1, p2, p3, p4, 0, function_number) -#define __hypercall_fast5(function_number, p1, p2, p3, p4, p5) \ - __hypercall_fast(p1, p2, p3, p4, p5, function_number) - -/** - * Performs a fast hypervisor API call which returns no value except for the - * error status. - * - * @param p1 the 1st argument of the hypervisor API call - * @param p2 the 2nd argument of the hypervisor API call - * @param p3 the 3rd argument of the hypervisor API call - * @param p4 the 4th argument of the hypervisor API call - * @param p5 the 5th argument of the hypervisor API call - * @param function_number function number of the call - * @return error status - */ -static inline uint64_t -__hypercall_fast(const uint64_t p1, const uint64_t p2, const uint64_t p3, - const uint64_t p4, const uint64_t p5, const uint64_t function_number) -{ - register uint64_t a6 asm("o5") = function_number; - register uint64_t a1 asm("o0") = p1; - register uint64_t a2 asm("o1") = p2; - register uint64_t a3 asm("o2") = p3; - register uint64_t a4 asm("o3") = p4; - register uint64_t a5 asm("o4") = p5; - - asm volatile ( - "ta %7\n" - : "=r" (a1) - : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), - "i" (FAST_TRAP) - : "memory" - ); - - return a1; -} - -/** - * Performs a fast hypervisor API call which can return a value. - * - * @param p1 the 1st argument of the hypervisor API call - * @param p2 the 2nd argument of the hypervisor API call - * @param p3 the 3rd argument of the hypervisor API call - * @param p4 the 4th argument of the hypervisor API call - * @param p5 the 5th argument of the hypervisor API call - * @param function_number function number of the call - * @param ret1 pointer to an address where the return value - * of the hypercall should be saved, or NULL - * @return error status - */ -static inline uint64_t -__hypercall_fast_ret1(const uint64_t p1, const uint64_t p2, const uint64_t p3, - const uint64_t p4, const uint64_t p5, const uint64_t function_number, - uint64_t *ret1) -{ - register uint64_t a6 asm("o5") = function_number; - register uint64_t a1 asm("o0") = p1; - register uint64_t a2 asm("o1") = p2; - register uint64_t a3 asm("o2") = p3; - register uint64_t a4 asm("o3") = p4; - register uint64_t a5 asm("o4") = p5; - - asm volatile ( - "ta %8\n" - : "=r" (a1), "=r" (a2) - : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), - "i" (FAST_TRAP) - : "memory" - ); - - if (ret1) - *ret1 = a2; - - return a1; -} - -/** - * Performs a hyperfast hypervisor API call. - * - * @param p1 the 1st argument of the hypervisor API call - * @param p2 the 2nd argument of the hypervisor API call - * @param p3 the 3rd argument of the hypervisor API call - * @param p4 the 4th argument of the hypervisor API call - * @param p5 the 5th argument of the hypervisor API call - * @param sw_trap_number software trap number - */ -static inline uint64_t -__hypercall_hyperfast(const uint64_t p1, const uint64_t p2, const uint64_t p3, - const uint64_t p4, const uint64_t p5, const uint64_t sw_trap_number) -{ - register uint64_t a1 asm("o0") = p1; - register uint64_t a2 asm("o1") = p2; - register uint64_t a3 asm("o2") = p3; - register uint64_t a4 asm("o3") = p4; - register uint64_t a5 asm("o4") = p5; - - asm volatile ( - "ta %6\n" - : "=r" (a1) - : "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), - "i" (sw_trap_number) - : "memory" - ); - - return a1; -} - -#endif /* ASM */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/sun4v/ipi.h =================================================================== --- kernel/arch/sparc64/include/sun4v/ipi.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,48 +1,0 @@ -/* - * Copyright (c) 2009 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** - * @file - * @brief sun4v-specific IPI functions - */ - -#ifndef KERN_sparc64_sun4v_IPI_H_ -#define KERN_sparc64_sun4v_IPI_H_ - -#include - -extern uint64_t ipi_brodcast_to(void (*)(void), uint16_t cpu_list[], uint64_t); -extern uint64_t ipi_unicast_to(void (*)(void), uint16_t); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/sun4v/md.h =================================================================== --- kernel/arch/sparc64/include/sun4v/md.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,65 +1,0 @@ -/* - * Copyright (c) 2009 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_MD_H_ -#define KERN_sparc64_sun4v_MD_H_ - -#include - -/** - * Data type used to iterate through MD nodes. Internally represented as - * an index to the first element of the node. - */ -typedef unsigned int md_node_t; - -/** used to iterate over children of a given node */ -typedef unsigned int md_child_iter_t; - -md_node_t md_get_root(void); -md_node_t md_get_child(md_node_t node, char *name); -md_child_iter_t md_get_child_iterator(md_node_t node); -bool md_next_child(md_child_iter_t *it); -md_node_t md_get_child_node(md_child_iter_t it); -const char *md_get_node_name(md_node_t node); -bool md_get_integer_property(md_node_t node, const char *key, - uint64_t *result); -bool md_get_string_property(md_node_t node, const char *key, - const char **result); -bool md_next_node(md_node_t *node, const char *name); -void md_init(void); - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/sun4v/regdef.h =================================================================== --- kernel/arch/sparc64/include/sun4v/regdef.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,47 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * Copyright (c) 2008 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_REGDEF_H_ -#define KERN_sparc64_sun4v_REGDEF_H_ - -#define TSTATE_CWP_MASK 0x1f - -#define WSTATE_NORMAL(n) (n) -#define WSTATE_OTHER(n) ((n) << 3) - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/sun4v/register.h =================================================================== --- kernel/arch/sparc64/include/sun4v/register.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,62 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_sun4v_REGISTER_H_ -#define KERN_sparc64_sun4v_REGISTER_H_ - -#include -#include - -/** Processor State Register. */ -union pstate_reg { - uint64_t value; - struct { - uint64_t : 54; - unsigned cle : 1; /**< Current Little Endian. */ - unsigned tle : 1; /**< Trap Little Endian. */ - unsigned mm : 2; /**< Memory Model. */ - unsigned : 1; /**< RED state. */ - unsigned pef : 1; /**< Enable floating-point. */ - unsigned am : 1; /**< 32-bit Address Mask. */ - unsigned priv : 1; /**< Privileged Mode. */ - unsigned ie : 1; /**< Interrupt Enable. */ - unsigned : 1; - } __attribute__ ((packed)); -}; -typedef union pstate_reg pstate_reg_t; - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/trap/exception.h =================================================================== --- kernel/arch/sparc64/include/trap/exception.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,98 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -/** - * @file - */ - -#ifndef KERN_sparc64_EXCEPTION_H_ -#define KERN_sparc64_EXCEPTION_H_ - -#define TT_INSTRUCTION_ACCESS_EXCEPTION 0x08 -#define TT_INSTRUCTION_ACCESS_MMU_MISS 0x09 -#define TT_INSTRUCTION_ACCESS_ERROR 0x0a -#define TT_IAE_UNAUTH_ACCESS 0x0b -#define TT_IAE_NFO_PAGE 0x0c -#define TT_ILLEGAL_INSTRUCTION 0x10 -#define TT_PRIVILEGED_OPCODE 0x11 -#define TT_UNIMPLEMENTED_LDD 0x12 -#define TT_UNIMPLEMENTED_STD 0x13 -#define TT_DAE_INVALID_ASI 0x14 -#define TT_DAE_PRIVILEGE_VIOLATION 0x15 -#define TT_DAE_NC_PAGE 0x16 -#define TT_DAE_NFO_PAGE 0x17 -#define TT_FP_DISABLED 0x20 -#define TT_FP_EXCEPTION_IEEE_754 0x21 -#define TT_FP_EXCEPTION_OTHER 0x22 -#define TT_TAG_OVERFLOW 0x23 -#define TT_DIVISION_BY_ZERO 0x28 -#define TT_DATA_ACCESS_EXCEPTION 0x30 -#define TT_DATA_ACCESS_MMU_MISS 0x31 -#define TT_DATA_ACCESS_ERROR 0x32 -#define TT_MEM_ADDRESS_NOT_ALIGNED 0x34 -#define TT_LDDF_MEM_ADDRESS_NOT_ALIGNED 0x35 -#define TT_STDF_MEM_ADDRESS_NOT_ALIGNED 0x36 -#define TT_PRIVILEGED_ACTION 0x37 -#define TT_LDQF_MEM_ADDRESS_NOT_ALIGNED 0x38 -#define TT_STQF_MEM_ADDRESS_NOT_ALIGNED 0x39 - -#ifndef __ASM__ - -#include - -extern void dump_istate(istate_t *istate); - -extern void instruction_access_exception(int n, istate_t *istate); -extern void instruction_access_error(int n, istate_t *istate); -extern void illegal_instruction(int n, istate_t *istate); -extern void privileged_opcode(int n, istate_t *istate); -extern void unimplemented_LDD(int n, istate_t *istate); -extern void unimplemented_STD(int n, istate_t *istate); -extern void fp_disabled(int n, istate_t *istate); -extern void fp_exception_ieee_754(int n, istate_t *istate); -extern void fp_exception_other(int n, istate_t *istate); -extern void tag_overflow(int n, istate_t *istate); -extern void division_by_zero(int n, istate_t *istate); -extern void data_access_exception(int n, istate_t *istate); -extern void data_access_error(int n, istate_t *istate); -extern void mem_address_not_aligned(int n, istate_t *istate); -extern void LDDF_mem_address_not_aligned(int n, istate_t *istate); -extern void STDF_mem_address_not_aligned(int n, istate_t *istate); -extern void privileged_action(int n, istate_t *istate); -extern void LDQF_mem_address_not_aligned(int n, istate_t *istate); -extern void STQF_mem_address_not_aligned(int n, istate_t *istate); - -#endif /* !__ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/trap/interrupt.h =================================================================== --- kernel/arch/sparc64/include/trap/interrupt.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,90 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -/** - * @file - * @brief This file contains level N interrupt and inter-processor interrupt - * trap handler. - */ -#ifndef KERN_sparc64_INTERRUPT_TRAP_H_ -#define KERN_sparc64_INTERRUPT_TRAP_H_ - -#define TT_INTERRUPT_LEVEL_1 0x41 -#define TT_INTERRUPT_LEVEL_2 0x42 -#define TT_INTERRUPT_LEVEL_3 0x43 -#define TT_INTERRUPT_LEVEL_4 0x44 -#define TT_INTERRUPT_LEVEL_5 0x45 -#define TT_INTERRUPT_LEVEL_6 0x46 -#define TT_INTERRUPT_LEVEL_7 0x47 -#define TT_INTERRUPT_LEVEL_8 0x48 -#define TT_INTERRUPT_LEVEL_9 0x49 -#define TT_INTERRUPT_LEVEL_10 0x4a -#define TT_INTERRUPT_LEVEL_11 0x4b -#define TT_INTERRUPT_LEVEL_12 0x4c -#define TT_INTERRUPT_LEVEL_13 0x4d -#define TT_INTERRUPT_LEVEL_14 0x4e -#define TT_INTERRUPT_LEVEL_15 0x4f - -#define INTERRUPT_LEVEL_N_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE - -/* IMAP register bits */ -#define IGN_MASK 0x7c0 -#define INO_MASK 0x1f -#define IMAP_V_MASK (1ULL << 31) - -#define IGN_SHIFT 6 - - -#ifdef __ASM__ -.macro INTERRUPT_LEVEL_N_HANDLER n - mov \n - 1, %g2 - PREEMPTIBLE_HANDLER exc_dispatch -.endm -#endif - -#ifndef __ASM__ - -#include - -extern void interrupt(int n, istate_t *istate); -#endif /* !def __ASM__ */ - - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/trap/mmu.h =================================================================== --- kernel/arch/sparc64/include/trap/mmu.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,49 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -/** - * @file - * @brief This file contains fast MMU trap handlers. - */ - -#ifndef KERN_sparc64_MMU_TRAP_H_ -#define KERN_sparc64_MMU_TRAP_H_ - -#if defined (SUN4U) -#include -#elif defined (SUN4V) -#include -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/trap/regwin.h =================================================================== --- kernel/arch/sparc64/include/trap/regwin.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,216 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -/** - * @file - * @brief This file contains register window trap handlers. - */ - -#ifndef KERN_sparc64_REGWIN_H_ -#define KERN_sparc64_REGWIN_H_ - -#include -#include -#include - -#define TT_CLEAN_WINDOW 0x24 -#define TT_SPILL_0_NORMAL 0x80 /* kernel spills */ -#define TT_SPILL_1_NORMAL 0x84 /* userspace spills */ -#define TT_SPILL_2_NORMAL 0x88 /* spills to userspace window buffer */ -#define TT_SPILL_0_OTHER 0xa0 /* spills to userspace window buffer */ -#define TT_FILL_0_NORMAL 0xc0 /* kernel fills */ -#define TT_FILL_1_NORMAL 0xc4 /* userspace fills */ - -#define REGWIN_HANDLER_SIZE 128 - -#define CLEAN_WINDOW_HANDLER_SIZE REGWIN_HANDLER_SIZE -#define SPILL_HANDLER_SIZE REGWIN_HANDLER_SIZE -#define FILL_HANDLER_SIZE REGWIN_HANDLER_SIZE - -/* Window Save Area offsets. */ -#define L0_OFFSET 0 -#define L1_OFFSET 8 -#define L2_OFFSET 16 -#define L3_OFFSET 24 -#define L4_OFFSET 32 -#define L5_OFFSET 40 -#define L6_OFFSET 48 -#define L7_OFFSET 56 -#define I0_OFFSET 64 -#define I1_OFFSET 72 -#define I2_OFFSET 80 -#define I3_OFFSET 88 -#define I4_OFFSET 96 -#define I5_OFFSET 104 -#define I6_OFFSET 112 -#define I7_OFFSET 120 - -/* Uspace Window Buffer constants. */ -#define UWB_SIZE ((NWINDOWS - 1) * STACK_WINDOW_SAVE_AREA_SIZE) -#define UWB_ALIGNMENT 1024 -#define UWB_ASIZE ALIGN_UP(UWB_SIZE, UWB_ALIGNMENT) - -#ifdef __ASM__ - -/* - * Macro used by the nucleus and the primary context 0 during normal and other spills. - */ -.macro SPILL_NORMAL_HANDLER_KERNEL - stx %l0, [%sp + STACK_BIAS + L0_OFFSET] - stx %l1, [%sp + STACK_BIAS + L1_OFFSET] - stx %l2, [%sp + STACK_BIAS + L2_OFFSET] - stx %l3, [%sp + STACK_BIAS + L3_OFFSET] - stx %l4, [%sp + STACK_BIAS + L4_OFFSET] - stx %l5, [%sp + STACK_BIAS + L5_OFFSET] - stx %l6, [%sp + STACK_BIAS + L6_OFFSET] - stx %l7, [%sp + STACK_BIAS + L7_OFFSET] - stx %i0, [%sp + STACK_BIAS + I0_OFFSET] - stx %i1, [%sp + STACK_BIAS + I1_OFFSET] - stx %i2, [%sp + STACK_BIAS + I2_OFFSET] - stx %i3, [%sp + STACK_BIAS + I3_OFFSET] - stx %i4, [%sp + STACK_BIAS + I4_OFFSET] - stx %i5, [%sp + STACK_BIAS + I5_OFFSET] - stx %i6, [%sp + STACK_BIAS + I6_OFFSET] - stx %i7, [%sp + STACK_BIAS + I7_OFFSET] - saved - retry -.endm - -/* - * Macro used by the userspace during normal spills. - */ -.macro SPILL_NORMAL_HANDLER_USERSPACE - wr %g0, ASI_AIUP, %asi - stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi - stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi - stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi - stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi - stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi - stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi - stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi - stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi - stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi - stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi - stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi - stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi - stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi - stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi - stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi - stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi - saved - retry -.endm - -/* - * Macro used by the nucleus and the primary context 0 during normal fills. - */ -.macro FILL_NORMAL_HANDLER_KERNEL - ldx [%sp + STACK_BIAS + L0_OFFSET], %l0 - ldx [%sp + STACK_BIAS + L1_OFFSET], %l1 - ldx [%sp + STACK_BIAS + L2_OFFSET], %l2 - ldx [%sp + STACK_BIAS + L3_OFFSET], %l3 - ldx [%sp + STACK_BIAS + L4_OFFSET], %l4 - ldx [%sp + STACK_BIAS + L5_OFFSET], %l5 - ldx [%sp + STACK_BIAS + L6_OFFSET], %l6 - ldx [%sp + STACK_BIAS + L7_OFFSET], %l7 - ldx [%sp + STACK_BIAS + I0_OFFSET], %i0 - ldx [%sp + STACK_BIAS + I1_OFFSET], %i1 - ldx [%sp + STACK_BIAS + I2_OFFSET], %i2 - ldx [%sp + STACK_BIAS + I3_OFFSET], %i3 - ldx [%sp + STACK_BIAS + I4_OFFSET], %i4 - ldx [%sp + STACK_BIAS + I5_OFFSET], %i5 - ldx [%sp + STACK_BIAS + I6_OFFSET], %i6 - ldx [%sp + STACK_BIAS + I7_OFFSET], %i7 - restored - retry -.endm - -/* - * Macro used by the userspace during normal fills. - */ -.macro FILL_NORMAL_HANDLER_USERSPACE - wr %g0, ASI_AIUP, %asi - ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0 - ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1 - ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2 - ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3 - ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4 - ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5 - ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6 - ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7 - ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0 - ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1 - ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2 - ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3 - ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4 - ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5 - ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6 - ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7 - restored - retry -.endm - -.macro CLEAN_WINDOW_HANDLER - rdpr %cleanwin, %l0 - add %l0, 1, %l0 - wrpr %l0, 0, %cleanwin -#if defined(SUN4U) - mov %r0, %l0 - mov %r0, %l1 - mov %r0, %l2 - mov %r0, %l3 - mov %r0, %l4 - mov %r0, %l5 - mov %r0, %l6 - mov %r0, %l7 - mov %r0, %o0 - mov %r0, %o1 - mov %r0, %o2 - mov %r0, %o3 - mov %r0, %o4 - mov %r0, %o5 - mov %r0, %o6 - mov %r0, %o7 -#endif - retry -.endm -#endif /* __ASM__ */ - -#if defined(SUN4U) -#include -#elif defined(SUN4V) -#include -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/trap/sun4u/interrupt.h =================================================================== --- kernel/arch/sparc64/include/trap/sun4u/interrupt.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,104 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -/** - * @file - * @brief This file contains interrupt vector trap handler. - */ - -#ifndef KERN_sparc64_TRAP_SUN4U_INTERRUPT_H_ -#define KERN_sparc64_TRAP_SUN4U_INTERRUPT_H_ - -#include -#include - - -/* Interrupt ASI registers. */ -#define ASI_INTR_W 0x77 -#define ASI_INTR_DISPATCH_STATUS 0x48 -#define ASI_INTR_R 0x7f -#define ASI_INTR_RECEIVE 0x49 - -/* VA's used with ASI_INTR_W register. */ -#if defined (US) -#define ASI_UDB_INTR_W_DATA_0 0x40 -#define ASI_UDB_INTR_W_DATA_1 0x50 -#define ASI_UDB_INTR_W_DATA_2 0x60 -#elif defined (US3) -#define VA_INTR_W_DATA_0 0x40 -#define VA_INTR_W_DATA_1 0x48 -#define VA_INTR_W_DATA_2 0x50 -#define VA_INTR_W_DATA_3 0x58 -#define VA_INTR_W_DATA_4 0x60 -#define VA_INTR_W_DATA_5 0x68 -#define VA_INTR_W_DATA_6 0x80 -#define VA_INTR_W_DATA_7 0x88 -#endif -#define VA_INTR_W_DISPATCH 0x70 - -/* VA's used with ASI_INTR_R register. */ -#if defined(US) -#define ASI_UDB_INTR_R_DATA_0 0x40 -#define ASI_UDB_INTR_R_DATA_1 0x50 -#define ASI_UDB_INTR_R_DATA_2 0x60 -#elif defined (US3) -#define VA_INTR_R_DATA_0 0x40 -#define VA_INTR_R_DATA_1 0x48 -#define VA_INTR_R_DATA_2 0x50 -#define VA_INTR_R_DATA_3 0x58 -#define VA_INTR_R_DATA_4 0x60 -#define VA_INTR_R_DATA_5 0x68 -#define VA_INTR_R_DATA_6 0x80 -#define VA_INTR_R_DATA_7 0x88 -#endif - -/* Shifts in the Interrupt Vector Dispatch virtual address. */ -#define INTR_VEC_DISPATCH_MID_SHIFT 14 - -/* Bits in the Interrupt Dispatch Status register. */ -#define INTR_DISPATCH_STATUS_NACK 0x2 -#define INTR_DISPATCH_STATUS_BUSY 0x1 - -#define TT_INTERRUPT_VECTOR_TRAP 0x60 - -#define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE - -#ifdef __ASM__ -.macro INTERRUPT_VECTOR_TRAP_HANDLER - PREEMPTIBLE_HANDLER interrupt -.endm -#endif /* __ASM__ */ - - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/trap/sun4u/mmu.h =================================================================== --- kernel/arch/sparc64/include/trap/sun4u/mmu.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,184 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -/** - * @file - * @brief This file contains fast MMU trap handlers. - */ - -#ifndef KERN_sparc64_SUN4U_MMU_TRAP_H_ -#define KERN_sparc64_SUN4U_MMU_TRAP_H_ - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_TSB -#include -#endif - -#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 -#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 -#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c - -#define FAST_MMU_HANDLER_SIZE 128 - -#ifdef __ASM__ - -.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER - /* - * First, try to refill TLB from TSB. - */ -#ifdef CONFIG_TSB - ldxa [%g0] ASI_IMMU, %g1 ! read TSB Tag Target Register - ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2 ! read TSB 8K Pointer - ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 - cmp %g1, %g4 ! is this the entry we are looking for? - bne,pn %xcc, 0f - nop - stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG ! copy mapping from ITSB to ITLB - retry -#endif - -0: - wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate - PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss -.endm - -.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl - /* - * First, try to refill TLB from TSB. - */ - -#ifdef CONFIG_TSB - ldxa [%g0] ASI_DMMU, %g1 ! read TSB Tag Target Register - srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss? - brz,pn %g2, 0f - ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3 ! read TSB 8K Pointer - ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 - cmp %g1, %g4 ! is this the entry we are looking for? - bne,pn %xcc, 0f - nop - stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG ! copy mapping from DTSB to DTLB - retry -#endif - - /* - * Second, test if it is the portion of the kernel address space - * which is faulting. If that is the case, immediately create - * identity mapping for that page in DTLB. VPN 0 is excluded from - * this treatment. - * - * Note that branch-delay slots are used in order to save space. - */ -0: - sethi %hi(fast_data_access_mmu_miss_data_hi), %g7 - wr %g0, ASI_DMMU, %asi - ldxa [VA_DMMU_TAG_ACCESS] %asi, %g1 ! read the faulting Context and VPN - set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 - andcc %g1, %g2, %g3 ! get Context - bnz %xcc, 0f ! Context is non-zero - andncc %g1, %g2, %g3 ! get page address into %g3 - bz %xcc, 0f ! page address is zero - ldx [%g7 + %lo(end_of_identity)], %g4 - cmp %g3, %g4 - bgeu %xcc, 0f - - ldx [%g7 + %lo(kernel_8k_tlb_data_template)], %g2 - add %g3, %g2, %g2 - stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page - retry - - /* - * Third, catch and handle special cases when the trap is caused by - * the userspace register window spill or fill handler. In case - * one of these two traps caused this trap, we just lower the trap - * level and service the DTLB miss. In the end, we restart - * the offending SAVE or RESTORE. - */ -0: -.if (\tl > 0) - wrpr %g0, 1, %tl -.endif - - /* - * Switch from the MM globals. - */ - wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate - - /* - * Read the Tag Access register for the higher-level handler. - * This is necessary to survive nested DTLB misses. - */ - ldxa [VA_DMMU_TAG_ACCESS] %asi, %g2 - - /* - * g2 will be passed as an argument to fast_data_access_mmu_miss(). - */ - PREEMPTIBLE_HANDLER fast_data_access_mmu_miss -.endm - -.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl - /* - * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. - */ - -.if (\tl > 0) - wrpr %g0, 1, %tl -.endif - - /* - * Switch from the MM globals. - */ - wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate - - /* - * Read the Tag Access register for the higher-level handler. - * This is necessary to survive nested DTLB misses. - */ - mov VA_DMMU_TAG_ACCESS, %g2 - ldxa [%g2] ASI_DMMU, %g2 - - /* - * g2 will be passed as an argument to fast_data_access_mmu_miss(). - */ - PREEMPTIBLE_HANDLER fast_data_access_protection -.endm - -#endif /* __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/trap/sun4u/regwin.h =================================================================== --- kernel/arch/sparc64/include/trap/sun4u/regwin.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,70 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -#ifndef KERN_sparc64_sun4u_REGWIN_H_ -#define KERN_sparc64_sun4u_REGWIN_H_ - -#ifdef __ASM__ - -/* - * Macro used to spill userspace window to userspace window buffer. - * It can be either triggered from preemptible_handler doing SAVE - * at (TL=1) or from normal kernel code doing SAVE when OTHERWIN>0 - * at (TL=0). - */ -.macro SPILL_TO_USPACE_WINDOW_BUFFER - stx %l0, [%g7 + L0_OFFSET] - stx %l1, [%g7 + L1_OFFSET] - stx %l2, [%g7 + L2_OFFSET] - stx %l3, [%g7 + L3_OFFSET] - stx %l4, [%g7 + L4_OFFSET] - stx %l5, [%g7 + L5_OFFSET] - stx %l6, [%g7 + L6_OFFSET] - stx %l7, [%g7 + L7_OFFSET] - stx %i0, [%g7 + I0_OFFSET] - stx %i1, [%g7 + I1_OFFSET] - stx %i2, [%g7 + I2_OFFSET] - stx %i3, [%g7 + I3_OFFSET] - stx %i4, [%g7 + I4_OFFSET] - stx %i5, [%g7 + I5_OFFSET] - stx %i6, [%g7 + I6_OFFSET] - stx %i7, [%g7 + I7_OFFSET] - add %g7, STACK_WINDOW_SAVE_AREA_SIZE, %g7 - saved - retry -.endm - -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/trap/sun4v/interrupt.h =================================================================== --- kernel/arch/sparc64/include/trap/sun4v/interrupt.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,50 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -/** - * @file - * @brief This file contains interrupt vector trap handler. - */ - -#ifndef KERN_sparc64_TRAP_SUN4V_INTERRUPT_H_ -#define KERN_sparc64_TRAP_SUN4V_INTERRUPT_H_ - -#ifndef __ASM__ - -extern void sun4v_ipi_init(void); -extern void cpu_mondo(void); - -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/trap/sun4v/mmu.h =================================================================== --- kernel/arch/sparc64/include/trap/sun4v/mmu.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,175 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * Copyright (c) 2008 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -/** - * @file - * @brief This file contains fast MMU trap handlers. - */ - -#ifndef KERN_sparc64_sun4v_MMU_TRAP_H_ -#define KERN_sparc64_sun4v_MMU_TRAP_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_TSB -#include -#endif - -#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 -#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 -#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c -#define TT_CPU_MONDO 0x7c - -#define FAST_MMU_HANDLER_SIZE 128 - -#ifdef __ASM__ - -/* MMU fault status area data fault offset */ -#define FSA_DFA_OFFSET 0x48 - -/* MMU fault status area data context */ -#define FSA_DFC_OFFSET 0x50 - -/* offset of the target address within the TTE Data entry */ -#define TTE_DATA_TADDR_OFFSET 13 - -.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER - PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss -.endm - -/* - * Handler of the Fast Data Access MMU Miss trap. If the trap occurred in the kernel - * (context 0), an identity mapping (with displacement) is installed. Otherwise - * a higher level service routine is called. - */ -.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl - mov SCRATCHPAD_MMU_FSA, %g1 - ldxa [%g1] ASI_SCRATCHPAD, %g1 ! g1 <= RA of MMU fault status area - - /* read faulting context */ - add %g1, FSA_DFC_OFFSET, %g2 ! g2 <= RA of data fault context - ldxa [%g2] ASI_REAL, %g3 ! read the fault context - - /* read the faulting address */ - add %g1, FSA_DFA_OFFSET, %g2 ! g2 <= RA of data fault address - ldxa [%g2] ASI_REAL, %g1 ! read the fault address - srlx %g1, TTE_DATA_TADDR_OFFSET, %g1 ! truncate it to page boundary - sllx %g1, TTE_DATA_TADDR_OFFSET, %g1 - - /* service by higher-level routine when context != 0 */ - brnz %g3, 0f - nop - /* exclude page number 0 from installing the identity mapping */ - brz %g1, 0f - nop - - /* - * Installing the identity does not fit into 32 instructions, call - * a separate routine. The routine performs RETRY, hence the call never - * returns. - */ - ba,a %xcc, install_identity_mapping - -0: - - /* - * One of the scenarios in which this trap can occur is when the - * register window spill/fill handler accesses a memory which is not - * mapped. In such a case, this handler will be called from TL = 1. - * We handle the situation by pretending that the MMU miss occurred - * on TL = 0. Once the MMU miss trap is services, the instruction which - * caused the spill/fill trap is restarted, the spill/fill trap occurs, - * but this time its handler accesse memory which IS mapped. - */ - .if (\tl > 0) - wrpr %g0, 1, %tl - .endif - - /* - * Save the faulting virtual page and faulting context to the %g2 - * register. The most significant 51 bits of the %g2 register will - * contain the virtual address which caused the fault truncated to the - * page boundary. The least significant 13 bits of the %g2 register - * will contain the number of the context in which the fault occurred. - * The value of the %g2 register will be passed as a parameter to the - * higher level service routine. - */ - or %g1, %g3, %g2 - - PREEMPTIBLE_HANDLER fast_data_access_mmu_miss -.endm - -/* - * Handler of the Fast Data MMU Protection trap. Finds the trapping address - * and context and calls higher level service routine. - */ -.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl - /* - * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. - */ - .if (\tl > 0) - wrpr %g0, 1, %tl - .endif - - mov SCRATCHPAD_MMU_FSA, %g1 - ldxa [%g1] ASI_SCRATCHPAD, %g1 ! g1 <= RA of MMU fault status area - - /* read faulting context */ - add %g1, FSA_DFC_OFFSET, %g2 ! g2 <= RA of data fault context - ldxa [%g2] ASI_REAL, %g3 ! read the fault context - - /* read the faulting address */ - add %g1, FSA_DFA_OFFSET, %g2 ! g2 <= RA of data fault address - ldxa [%g2] ASI_REAL, %g1 ! read the fault address - srlx %g1, TTE_DATA_TADDR_OFFSET, %g1 ! truncate it to page boundary - sllx %g1, TTE_DATA_TADDR_OFFSET, %g1 - - /* the same as for FAST_DATA_ACCESS_MMU_MISS_HANDLER */ - or %g1, %g3, %g2 - - PREEMPTIBLE_HANDLER fast_data_access_protection -.endm -#endif /* __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/trap/sun4v/regwin.h =================================================================== --- kernel/arch/sparc64/include/trap/sun4v/regwin.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,86 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * Copyright (c) 2009 Pavel Rimsky - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -#ifndef KERN_sparc64_sun4v_REGWIN_H_ -#define KERN_sparc64_sun4v_REGWIN_H_ - -#ifdef __ASM__ - -/* - * Saves the contents of the current window to the userspace window buffer. - * Does not modify any register window registers, but updates pointer to the - * top of the userspace window buffer. - * - * Parameters: - * \tmpreg1 global register to be used for scratching purposes - * \tmpreg2 global register to be used for scratching purposes - */ -.macro SAVE_TO_USPACE_WBUF tmpreg1, tmpreg2 - set SCRATCHPAD_WBUF, \tmpreg2 - ldxa [\tmpreg2] ASI_SCRATCHPAD, \tmpreg1 - stx %l0, [\tmpreg1 + L0_OFFSET] - stx %l1, [\tmpreg1 + L1_OFFSET] - stx %l2, [\tmpreg1 + L2_OFFSET] - stx %l3, [\tmpreg1 + L3_OFFSET] - stx %l4, [\tmpreg1 + L4_OFFSET] - stx %l5, [\tmpreg1 + L5_OFFSET] - stx %l6, [\tmpreg1 + L6_OFFSET] - stx %l7, [\tmpreg1 + L7_OFFSET] - stx %i0, [\tmpreg1 + I0_OFFSET] - stx %i1, [\tmpreg1 + I1_OFFSET] - stx %i2, [\tmpreg1 + I2_OFFSET] - stx %i3, [\tmpreg1 + I3_OFFSET] - stx %i4, [\tmpreg1 + I4_OFFSET] - stx %i5, [\tmpreg1 + I5_OFFSET] - stx %i6, [\tmpreg1 + I6_OFFSET] - stx %i7, [\tmpreg1 + I7_OFFSET] - add \tmpreg1, STACK_WINDOW_SAVE_AREA_SIZE, \tmpreg1 - stxa \tmpreg1, [\tmpreg2] ASI_SCRATCHPAD -.endm - -/* - * Macro used to spill userspace window to userspace window buffer. - * It is triggered from normal kernel code doing SAVE when - * OTHERWIN>0 at (TL=0). - */ -.macro SPILL_TO_USPACE_WINDOW_BUFFER - SAVE_TO_USPACE_WBUF %g7, %g4 - saved - retry -.endm - -#endif - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/trap/syscall.h =================================================================== --- kernel/arch/sparc64/include/trap/syscall.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,45 +1,0 @@ -/* - * Copyright (c) 2006 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -/** - * @file - * @brief - */ - -#ifndef KERN_sparc64_SYSCALL_TRAP_H_ -#define KERN_sparc64_SYSCALL_TRAP_H_ - -#define TT_TRAP_INSTRUCTION_0 0x100 - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/trap/trap.h =================================================================== --- kernel/arch/sparc64/include/trap/trap.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,44 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_TRAP_H_ -#define KERN_sparc64_TRAP_H_ - -extern void trap_init(void); - -#endif - -/** @} - */ - Index: kernel/arch/sparc64/include/trap/trap_table.h =================================================================== --- kernel/arch/sparc64/include/trap/trap_table.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,112 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64interrupt - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_TRAP_TABLE_H_ -#define KERN_sparc64_TRAP_TABLE_H_ - -#include - -#define TRAP_TABLE_ENTRY_COUNT 1024 -#define TRAP_TABLE_ENTRY_SIZE 32 -#define TRAP_TABLE_SIZE (TRAP_TABLE_ENTRY_COUNT * TRAP_TABLE_ENTRY_SIZE) - -/* - * The following needs to be in sync with the definition of the istate - * structure. The one STACK_ITEM_SIZE is counted for space holding the 7th - * argument to syscall_handler (i.e. syscall number) and the other - * STACK_ITEM_SIZE is counted because of the required alignment. - */ -#define PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE \ - (STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE + \ - (2 * STACK_ITEM_SIZE) + (12 * 8)) -#define SAVED_TSTATE -(1 * 8) -#define SAVED_TPC -(2 * 8) -#define SAVED_TNPC -(3 * 8) /* <-- istate_t begins here */ -#define SAVED_Y -(4 * 8) -#define SAVED_I0 -(5 * 8) -#define SAVED_I1 -(6 * 8) -#define SAVED_I2 -(7 * 8) -#define SAVED_I3 -(8 * 8) -#define SAVED_I4 -(9 * 8) -#define SAVED_I5 -(10 * 8) -#define SAVED_I6 -(11 * 8) -#define SAVED_I7 -(12 * 8) - -#ifndef __ASM__ - -#include - -struct trap_table_entry { - uint8_t octets[TRAP_TABLE_ENTRY_SIZE]; -} __attribute__ ((packed)); - -typedef struct trap_table_entry trap_table_entry_t; - -extern trap_table_entry_t trap_table[TRAP_TABLE_ENTRY_COUNT]; -extern trap_table_entry_t trap_table_save[TRAP_TABLE_ENTRY_COUNT]; -#endif /* !__ASM__ */ - -#ifdef __ASM__ -.macro SAVE_GLOBALS - mov %g1, %l1 - mov %g2, %l2 - mov %g3, %l3 - mov %g4, %l4 - mov %g5, %l5 - mov %g6, %l6 - mov %g7, %l7 -.endm - -.macro RESTORE_GLOBALS - mov %l1, %g1 - mov %l2, %g2 - mov %l3, %g3 - mov %l4, %g4 - mov %l5, %g5 - mov %l6, %g6 - mov %l7, %g7 -.endm - -.macro PREEMPTIBLE_HANDLER f - sethi %hi(\f), %g1 - ba %xcc, preemptible_handler - or %g1, %lo(\f), %g1 -.endm - -#endif /* __ASM__ */ - -#endif - -/** @} - */ Index: kernel/arch/sparc64/include/types.h =================================================================== --- kernel/arch/sparc64/include/types.h (revision 2277e03b97a6950736870a381ad825874af27449) +++ (revision ) @@ -1,66 +1,0 @@ -/* - * Copyright (c) 2005 Jakub Jermar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** @addtogroup sparc64 - * @{ - */ -/** @file - */ - -#ifndef KERN_sparc64_TYPES_H_ -#define KERN_sparc64_TYPES_H_ - -typedef uint64_t size_t; -typedef int64_t ssize_t; - -typedef uint64_t uintptr_t; -typedef uint64_t pfn_t; - -typedef uint64_t ipl_t; - -typedef uint64_t sysarg_t; -typedef int64_t native_t; -typedef uint64_t atomic_count_t; - -typedef struct { -} fncptr_t; - -typedef uint8_t asi_t; - -#define INTN_C(c) INT64_C(c) -#define UINTN_C(c) UINT64_C(c) - -#define PRIdn PRId64 /**< Format for native_t. */ -#define PRIun PRIu64 /**< Format for sysarg_t. */ -#define PRIxn PRIx64 /**< Format for hexadecimal sysarg_t. */ -#define PRIua PRIu64 /**< Format for atomic_count_t. */ - -#endif - -/** @} - */