Index: boot/arch/arm32/Makefile.inc
===================================================================
--- boot/arch/arm32/Makefile.inc	(revision 2e5544302c20e9f67992b1890d361a5388c55c64)
+++ boot/arch/arm32/Makefile.inc	(revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828)
@@ -54,5 +54,5 @@
 RD_SRVS_ESSENTIAL += \
 	$(USPACE_PATH)/srv/hid/s3c24xx_ts/s3c24xx_ts \
-	$(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24xx_uart
+	$(USPACE_PATH)/srv/hw/char/s3c24xx_uart/s3c24ser
 endif
 
Index: boot/arch/arm32/src/asm.S
===================================================================
--- boot/arch/arm32/src/asm.S	(revision 2e5544302c20e9f67992b1890d361a5388c55c64)
+++ boot/arch/arm32/src/asm.S	(revision 05bab88f6a2578787b9598ccdf1e856cfdbd2828)
@@ -97,34 +97,3 @@
 	nop
 #endif
-	
-#TODO:This should not be necessary
-
-#if defined(MACHINE_gta02)
-
-#define CP15_C7_SEG_SHIFT	5
-#define CP15_C7_SEG_SIZE	3
-#define CP15_C7_IDX_SHIFT	26
-
-	# Now clean D-cache to guarantee coherency between I-cache and D-cache.
-
-	# D-cache clean and invalidate procedure.
-	# See ARM920T TRM pages 2-17, 4-17.
-
-	# Initialize segment
-	mov	r4, #0
-	# Initialize index
-1:	mov	r5, #0
-2:	orr	r6, r4, r5
-	# Clean and invalidate a single line
-	mcr	p15, 0, r6, c7, c10, 2
-	# Increment index
-	add	r5, r5, #(1 << CP15_C7_IDX_SHIFT)
-	cmp	r5, #0
-	bne	2b
-	# Increment segment
-	add	r4, #(1 << CP15_C7_SEG_SHIFT)
-	tst	r4, #(1 << (CP15_C7_SEG_SHIFT + CP15_C7_SEG_SIZE))
-	beq	1b
-#endif
-
 	mov pc, r0