Index: kernel/arch/mips32/src/debugger.c
===================================================================
--- kernel/arch/mips32/src/debugger.c	(revision 0abc2aea144199fee5fb2b5b1ffcf9f0ac6528ce)
+++ kernel/arch/mips32/src/debugger.c	(revision 036e97cf14fc9f9a4783fbb16419e5aaf0793b2d)
@@ -147,4 +147,10 @@
 }
 
+static inline void write_inst(uintptr_t addr, uint32_t inst)
+{
+	*((uint32_t *) addr) = inst;
+	smc_coherence((uint32_t *) addr, 4);
+}
+
 #ifdef CONFIG_KCONSOLE
 
@@ -212,6 +218,5 @@
 
 	/* Set breakpoint */
-	*((sysarg_t *) cur->address) = 0x0d;
-	smc_coherence(cur->address, 4);
+	write_inst(cur->address, 0x0d);
 
 	irq_spinlock_unlock(&bkpoint_lock, true);
@@ -245,8 +250,6 @@
 	}
 
-	((uint32_t *) cur->address)[0] = cur->instruction;
-	smc_coherence(((uint32_t *) cur->address)[0], 4);
-	((uint32_t *) cur->address)[1] = cur->nextinstruction;
-	smc_coherence(((uint32_t *) cur->address)[1], 4);
+	write_inst(cur->address, cur->instruction);
+	write_inst(cur->address + 4, cur->nextinstruction);
 
 	cur->address = (uintptr_t) NULL;
@@ -357,10 +360,8 @@
 		if (cur->flags & BKPOINT_REINST) {
 			/* Set breakpoint on first instruction */
-			((uint32_t *) cur->address)[0] = 0x0d;
-			smc_coherence(((uint32_t *)cur->address)[0], 4);
+			write_inst(cur->address, 0x0d);
 
 			/* Return back the second */
-			((uint32_t *) cur->address)[1] = cur->nextinstruction;
-			smc_coherence(((uint32_t *) cur->address)[1], 4);
+			write_inst(cur->address + 4, cur->nextinstruction);
 
 			cur->flags &= ~BKPOINT_REINST;
@@ -379,10 +380,9 @@
 
 		/* Return first instruction back */
-		((uint32_t *)cur->address)[0] = cur->instruction;
-		smc_coherence(cur->address, 4);
+		write_inst(cur->address, cur->instruction);
 
 		if (!(cur->flags & BKPOINT_ONESHOT)) {
 			/* Set Breakpoint on next instruction */
-			((uint32_t *)cur->address)[1] = 0x0d;
+			write_inst(cur->address + 4, 0x0d);
 			cur->flags |= BKPOINT_REINST;
 		}
Index: kernel/arch/mips32/src/smc.c
===================================================================
--- kernel/arch/mips32/src/smc.c	(revision 036e97cf14fc9f9a4783fbb16419e5aaf0793b2d)
+++ kernel/arch/mips32/src/smc.c	(revision 036e97cf14fc9f9a4783fbb16419e5aaf0793b2d)
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2005 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ *   derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <barrier.h>
+
+void smc_coherence(void *a, size_t l)
+{
+	// TODO
+	compiler_barrier();
+}
+