Index: boot/arch/arm32/Makefile.inc
===================================================================
--- boot/arch/arm32/Makefile.inc	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ boot/arch/arm32/Makefile.inc	(revision 029e3ccb036744485e317fa89603ce023fc7f6b3)
@@ -49,5 +49,5 @@
 BITS = 32
 ENDIANESS = LE
-EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
+EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR_ARCH)) -mno-unaligned-access
 
 ifeq ($(MACHINE), gta02)
Index: boot/arch/arm32/src/mm.c
===================================================================
--- boot/arch/arm32/src/mm.c	(revision b5a3b50c5e0e757d7f292db4541d06a2e1c042d6)
+++ boot/arch/arm32/src/mm.c	(revision 029e3ccb036744485e317fa89603ce023fc7f6b3)
@@ -130,5 +130,5 @@
 		"mcr p15, 0, r0, c3, c0, 0\n"
 		
-#ifdef PROCESSOR_armv7_a
+#ifdef PROCESSOR_ARCH_armv7_a
 		/* Read Auxiliary control register */
 		"mrc p15, 0, r0, c1, c0, 1\n"
@@ -142,7 +142,14 @@
 		"mrc p15, 0, r0, c1, c0, 0\n"
 		
-#ifdef PROCESSOR_armv7_a
-		/* Mask to enable paging, caching */
-		"ldr r1, =0x00000005\n"
+#ifdef PROCESSOR_cortex_a8
+		/* Mask to enable paging, I-cache D-cache and branch predict
+		 * See kernel/arch/arm32/include/regutils.h for bit values.
+		 * It's safe because Cortex-A8 implements IVIPT extension
+		 * See Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
+		"ldr r1, =0x00001805\n"
+#elif defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
+		/* Enable paging, data cache and branch prediction
+		 * see arch/arm32/src/cpu/cpu.c for reasoning */
+		"ldr r1, =0x00000805\n"
 #else
 #ifdef MACHINE_gta02
@@ -151,6 +158,6 @@
 		"ldr r1, =0x00001005\n"
 #else
-		/* Mask to enable paging */
-		"ldr r1, =0x00000001\n"
+		/* Mask to enable paging and branch prediction */
+		"ldr r1, =0x00000801\n"
 #endif
 #endif