Index: arch/sparc64/include/atomic.h
===================================================================
--- arch/sparc64/include/atomic.h	(revision 0fad93a170a506b86673f51b26524b7baaa817a7)
+++ arch/sparc64/include/atomic.h	(revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80)
@@ -54,5 +54,5 @@
 		"casx %0, %1, %2\n"
 		"cmp %1, %2\n"
-		"bne 0b\n"
+		"bne 0b\n"		/* The operation failed and must be attempted again if a != b. */
 		"nop\n"
 		: "=m" (*((__u64 *)x)), "=r" (a), "=r" (b)
Index: arch/sparc64/include/mm/tlb.h
===================================================================
--- arch/sparc64/include/mm/tlb.h	(revision 0fad93a170a506b86673f51b26524b7baaa817a7)
+++ arch/sparc64/include/mm/tlb.h	(revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80)
@@ -269,3 +269,7 @@
 }
 
+extern void fast_instruction_access_mmu_miss(void);
+extern void fast_data_access_mmu_miss(void);
+extern void fast_data_access_protection(void);
+
 #endif
Index: arch/sparc64/src/mm/tlb.c
===================================================================
--- arch/sparc64/src/mm/tlb.c	(revision 0fad93a170a506b86673f51b26524b7baaa817a7)
+++ arch/sparc64/src/mm/tlb.c	(revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80)
@@ -37,4 +37,5 @@
 #include <config.h>
 #include <arch/trap/trap.h>
+#include <panic.h>
 
 /** Initialize ITLB and DTLB.
@@ -98,4 +99,22 @@
 }
 
+/** ITLB miss handler. */
+void fast_instruction_access_mmu_miss(void)
+{
+	panic("%s\n", __FUNCTION__);
+}
+
+/** DTLB miss handler. */
+void fast_data_access_mmu_miss(void)
+{
+	panic("%s\n", __FUNCTION__);
+}
+
+/** DTLB protection fault handler. */
+void fast_data_access_protection(void)
+{
+	panic("%s\n", __FUNCTION__);
+}
+
 /** Print contents of both TLBs. */
 void tlb_print(void)
Index: arch/sparc64/src/trap/trap_table.S
===================================================================
--- arch/sparc64/src/trap/trap_table.S	(revision 0fad93a170a506b86673f51b26524b7baaa817a7)
+++ arch/sparc64/src/trap/trap_table.S	(revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80)
@@ -50,4 +50,5 @@
 #include <arch/trap/interrupt.h>
 #include <arch/trap/exception.h>
+#include <arch/trap/mmu.h>
 #include <arch/stack.h>
 
@@ -176,4 +177,22 @@
 	INTERRUPT_VECTOR_TRAP_HANDLER
 
+/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
+.org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
+.global fast_instruction_access_mmu_miss_handler
+fast_instruction_access_mmu_miss_handler:
+	FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
+
+/* TT = 0x68, TL = 0, fast_data_access_MMU_miss */
+.org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE
+.global fast_data_access_mmu_miss_handler
+fast_data_access_mmu_miss_handler:
+	FAST_DATA_ACCESS_MMU_MISS_HANDLER
+
+/* TT = 0x6c, TL = 0, fast_data_access_protection */
+.org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE
+.global fast_data_access_protection_handler
+fast_data_access_protection_handler:
+	FAST_DATA_ACCESS_PROTECTION_HANDLER
+
 /* TT = 0x80, TL = 0, spill_0_normal handler */
 .org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE
@@ -209,4 +228,22 @@
 mem_address_not_aligned_high:
 	SIMPLE_HANDLER do_mem_address_not_aligned
+
+/* TT = 0x64, TL > 0, fast_instruction_access_MMU_miss */
+.org trap_table + (TT_FAST_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE
+.global fast_instruction_access_mmu_miss_handler_high
+fast_instruction_access_mmu_miss_handler_high:
+	FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
+
+/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
+.org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE
+.global fast_data_access_mmu_miss_handler_high
+fast_data_access_mmu_miss_handler_high:
+	FAST_DATA_ACCESS_MMU_MISS_HANDLER
+
+/* TT = 0x6c, TL > 0, fast_data_access_protection */
+.org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE
+.global fast_data_access_protection_handler_high
+fast_data_access_protection_handler_high:
+	FAST_DATA_ACCESS_PROTECTION_HANDLER
 
 /* TT = 0x80, TL > 0, spill_0_normal handler */