Index: arch/ppc32/Makefile.inc =================================================================== --- arch/ppc32/Makefile.inc (revision 37c8975a5116482f4bdd559722bb5883196b0b85) +++ arch/ppc32/Makefile.inc (revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80) @@ -56,5 +56,5 @@ arch/$(ARCH)/src/context.S \ arch/$(ARCH)/src/debug/panic.s \ - arch/$(ARCH)/src/fpu_context.c \ + arch/$(ARCH)/src/fpu_context.S \ arch/$(ARCH)/src/ppc32.c \ arch/$(ARCH)/src/dummy.s \ Index: arch/ppc32/include/context_offset.h =================================================================== --- arch/ppc32/include/context_offset.h (revision 37c8975a5116482f4bdd559722bb5883196b0b85) +++ arch/ppc32/include/context_offset.h (revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80) @@ -1,25 +1,45 @@ /* This file is automatically generated by gencontext.c. */ /* struct context */ -#define OFFSET_SP 0x0 -#define OFFSET_PC 0x4 -#define OFFSET_R2 0x8 -#define OFFSET_R13 0xc -#define OFFSET_R14 0x10 -#define OFFSET_R15 0x14 -#define OFFSET_R16 0x18 -#define OFFSET_R17 0x1c -#define OFFSET_R18 0x20 -#define OFFSET_R19 0x24 -#define OFFSET_R20 0x28 -#define OFFSET_R21 0x2c -#define OFFSET_R22 0x30 -#define OFFSET_R23 0x34 -#define OFFSET_R24 0x38 -#define OFFSET_R25 0x3c -#define OFFSET_R26 0x40 -#define OFFSET_R27 0x44 -#define OFFSET_R28 0x48 -#define OFFSET_R29 0x4c -#define OFFSET_R30 0x50 -#define OFFSET_R31 0x54 -#define OFFSET_CR 0x58 +#define OFFSET_SP 0x0 +#define OFFSET_PC 0x4 +#define OFFSET_R2 0x8 +#define OFFSET_R13 0xc +#define OFFSET_R14 0x10 +#define OFFSET_R15 0x14 +#define OFFSET_R16 0x18 +#define OFFSET_R17 0x1c +#define OFFSET_R18 0x20 +#define OFFSET_R19 0x24 +#define OFFSET_R20 0x28 +#define OFFSET_R21 0x2c +#define OFFSET_R22 0x30 +#define OFFSET_R23 0x34 +#define OFFSET_R24 0x38 +#define OFFSET_R25 0x3c +#define OFFSET_R26 0x40 +#define OFFSET_R27 0x44 +#define OFFSET_R28 0x48 +#define OFFSET_R29 0x4c +#define OFFSET_R30 0x50 +#define OFFSET_R31 0x54 +#define OFFSET_CR 0x58 + +#define OFFSET_FR14 0x0 +#define OFFSET_FR15 0x8 +#define OFFSET_FR16 0x10 +#define OFFSET_FR17 0x18 +#define OFFSET_FR18 0x20 +#define OFFSET_FR19 0x28 +#define OFFSET_FR20 0x30 +#define OFFSET_FR21 0x38 +#define OFFSET_FR22 0x40 +#define OFFSET_FR23 0x48 +#define OFFSET_FR24 0x50 +#define OFFSET_FR25 0x58 +#define OFFSET_FR26 0x60 +#define OFFSET_FR27 0x68 +#define OFFSET_FR28 0x70 +#define OFFSET_FR29 0x78 +#define OFFSET_FR30 0x80 +#define OFFSET_FR31 0x88 +#define OFFSET_FPSCR 0x90 Index: arch/ppc32/include/cpu.h =================================================================== --- arch/ppc32/include/cpu.h (revision 37c8975a5116482f4bdd559722bb5883196b0b85) +++ arch/ppc32/include/cpu.h (revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80) @@ -33,4 +33,6 @@ struct cpu_arch { + int version; + int revision; }; Index: arch/ppc32/include/cpuid.h =================================================================== --- arch/ppc32/include/cpuid.h (revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80) +++ arch/ppc32/include/cpuid.h (revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80) @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2006 Martin Decky + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ppc32_CPUID_H__ +#define __ppc32_CPUID_H__ + +#include + +struct cpu_info { + __u16 version; + __u16 revision; +} __attribute__ ((packed)); + +static inline void cpu_version(struct cpu_info *info) +{ + __asm__ volatile ( + "mfspr %0, 287\n" + : "=r" (*info) + ); +} + +#endif Index: arch/ppc32/include/fpu_context.h =================================================================== --- arch/ppc32/include/fpu_context.h (revision 37c8975a5116482f4bdd559722bb5883196b0b85) +++ arch/ppc32/include/fpu_context.h (revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80) @@ -30,8 +30,29 @@ #define __ppc32_FPU_CONTEXT_H__ -#include +#ifndef __ppc32_TYPES_H__ +# include +#endif struct fpu_context { -}; + __u64 fr14; + __u64 fr15; + __u64 fr16; + __u64 fr17; + __u64 fr18; + __u64 fr19; + __u64 fr20; + __u64 fr21; + __u64 fr22; + __u64 fr23; + __u64 fr24; + __u64 fr25; + __u64 fr26; + __u64 fr27; + __u64 fr28; + __u64 fr29; + __u64 fr30; + __u64 fr31; + __u32 fpscr; +} __attribute__ ((packed)); #endif Index: arch/ppc32/src/asm.S =================================================================== --- arch/ppc32/src/asm.S (revision 37c8975a5116482f4bdd559722bb5883196b0b85) +++ arch/ppc32/src/asm.S (revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80) @@ -86,4 +86,62 @@ memcpy: - # TODO + srwi. r7, r5, 3 + addi r6, r3, -4 + addi r4, r4, -4 + beq 2f + + andi. r0, r6, 3 + mtctr r7 + bne 5f + + 1: + + lwz r7, 4(r4) + lwzu r8, 8(r4) + stw r7, 4(r6) + stwu r8, 8(r6) + bdnz 1b + + andi. r5, r5, 7 + + 2: + + cmplwi 0, r5, 4 + blt 3f + + lwzu r0, 4(r4) + addi r5, r5, -4 + stwu r0, 4(r6) + + 3: + + cmpwi 0, r5, 0 + beqlr + mtctr r5 + addi r4, r4, 3 + addi r6, r6, 3 + + 4: + + lbzu r0, 1(r4) + stbu r0, 1(r6) + bdnz 4b blr + + 5: + + subfic r0, r0, 4 + mtctr r0 + + 6: + + lbz r7, 4(r4) + addi r4, r4, 1 + stb r7, 4(r6) + addi r6, r6, 1 + bdnz 6b + subf r5, r0, r5 + rlwinm. r7, r5, 32-3, 3, 31 + beq 2b + mtctr r7 + b 1b Index: arch/ppc32/src/cpu/cpu.c =================================================================== --- arch/ppc32/src/cpu/cpu.c (revision 37c8975a5116482f4bdd559722bb5883196b0b85) +++ arch/ppc32/src/cpu/cpu.c (revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80) @@ -28,4 +28,5 @@ #include +#include #include @@ -41,8 +42,13 @@ void cpu_identify(void) { + cpu_info_t info; + + cpu_version(&info); + CPU->arch.version = info.version; + CPU->arch.revision = info.revision; } void cpu_print_report(cpu_t *m) { - printf("cpu%d:\n", m->id); + printf("cpu%d: version=%d, revision=%d\n", m->id, m->arch.version, m->arch.revision); } Index: arch/ppc32/src/fpu_context.S =================================================================== --- arch/ppc32/src/fpu_context.S (revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80) +++ arch/ppc32/src/fpu_context.S (revision 008029d66eb4ff7b6479bbb71cdd04acc031bb80) @@ -0,0 +1,93 @@ +# +# Copyright (C) 2006 Martin Decky +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# - Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# - The name of the author may not be used to endorse or promote products +# derived from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +#include +#include + +.text + +.global fpu_context_save +.global fpu_context_restore + +.macro FPU_CONTEXT_STORE r + stfd fr14, OFFSET_FR14(\r) + stfd fr15, OFFSET_FR15(\r) + stfd fr16, OFFSET_FR16(\r) + stfd fr17, OFFSET_FR17(\r) + stfd fr18, OFFSET_FR18(\r) + stfd fr19, OFFSET_FR19(\r) + stfd fr20, OFFSET_FR20(\r) + stfd fr21, OFFSET_FR21(\r) + stfd fr22, OFFSET_FR22(\r) + stfd fr23, OFFSET_FR23(\r) + stfd fr24, OFFSET_FR24(\r) + stfd fr25, OFFSET_FR25(\r) + stfd fr26, OFFSET_FR26(\r) + stfd fr27, OFFSET_FR27(\r) + stfd fr28, OFFSET_FR28(\r) + stfd fr29, OFFSET_FR29(\r) + stfd fr30, OFFSET_FR30(\r) + stfd fr31, OFFSET_FR31(\r) +.endm + +.macro FPU_CONTEXT_LOAD r + lfd fr14, OFFSET_FR14(\r) + lfd fr15, OFFSET_FR15(\r) + lfd fr16, OFFSET_FR16(\r) + lfd fr17, OFFSET_FR17(\r) + lfd fr18, OFFSET_FR18(\r) + lfd fr19, OFFSET_FR19(\r) + lfd fr20, OFFSET_FR20(\r) + lfd fr21, OFFSET_FR21(\r) + lfd fr22, OFFSET_FR22(\r) + lfd fr23, OFFSET_FR23(\r) + lfd fr24, OFFSET_FR24(\r) + lfd fr25, OFFSET_FR25(\r) + lfd fr26, OFFSET_FR26(\r) + lfd fr27, OFFSET_FR27(\r) + lfd fr28, OFFSET_FR28(\r) + lfd fr29, OFFSET_FR29(\r) + lfd fr30, OFFSET_FR30(\r) + lfd fr31, OFFSET_FR31(\r) +.endm + +fpu_context_save: + FPU_CONTEXT_STORE r3 + + mffs fr0 + stfd fr0, OFFSET_FPSCR(r3) + + blr + +fpu_context_restore: + FPU_CONTEXT_LOAD r3 + + lfd fr0, OFFSET_FPSCR(r3) + mtfsf 7, fr0 + + blr Index: arch/ppc32/src/fpu_context.c =================================================================== --- arch/ppc32/src/fpu_context.c (revision 37c8975a5116482f4bdd559722bb5883196b0b85) +++ (revision ) @@ -1,39 +1,0 @@ -/* - * Copyright (C) 2005 Jakub Vana - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include - -void fpu_context_save(fpu_context_t *fctx) -{ -} - - -void fpu_context_restore(fpu_context_t *fctx) -{ -}