Virtual address spaces per architecture

Below are the various situations as dictated by hardware of each supported architecture and as currently used by HelenOS. The address space split is described from the kernel's point of view.

---

amd64

48-bit virtual address width

Starting address	Size	HW limitation	HelenOS use
FFFF800000000000	128 TiB	none	kernel identity (2)
0000800000000000	16776960 TiB	VA hole (1)
0000000000000000	128 TiB	none	uspace non-identity

1. depends on implementation, but in practice current implementations use 48 bits
2. physical addresses beyond the limit of physical memory are mapped non-identity

---

arm32

Starting address	Size	HW limitation	HelenOS use
80000000	2 GiB	none	kernel identity (1)
00000000	2 GiB	none	uspace non-identity

1. physical addresses beyond the limit of physical memory are mapped non-identity

---

ia32

Starting address	Size	HW limitation	HelenOS use
80000000	2 GiB	none	kernel identity (1)
00000000	2 GiB	none	uspace non-identity

1. physical addresses beyond the limit of physical memory are mapped non-identity

---

ia64

TBD

---

mips32

Starting address	Size	HW limitation	HelenOS use
E0000000	512 MiB	kseg3, kernel	unused
C0000000	512 MiB	ksseg, kernel	unused
A0000000	512 MiB	kseg1, kernel uncached (1)	hw_map()
80000000	512 MiB	kseg0, kernel identity (2)	kernel identity
00000000	2 GiB	kuseg, uspace	uspace non-identity

1. maps to physical 0, uncached, bypasses TLB
2. maps to physical 0, cacheable, bypasses TLB

---

ppc32

TBD

---

sparc64

UltraSPARC I, II, IIi

44-bit virtual address width

Starting address	Size	HW limitation	HelenOS use
FFFFF80000000000	8 TiB	kernel (1)	kernel identity (3)
0000080000000000	16777200 TiB	VA hole (2)
0000000000000000	8 TiB	kernel (1)	kernel identity (3)

UltraSPARC III, IIIi, IV and IV+

64-bit virtual address width

Starting address	Size	HW limitation	HelenOS use
0000000000000000	16 EiB	kernel (1)	kernel identity (3)

UltraSPARC T1, T2

48-bit virtual address width

Starting address	Size	HW limitation	HelenOS use
FFFF800000000000	128 TiB	kernel (1)	kernel identity (3)
0000800000000000	16776960 TiB	VA hole (4), (5)
0000000000000000	128 TiB	kernel (1)	kernel identity (3)

1. both kernel and uspace run in separated 64-bit address spaces
2. no code within 4GiB reach of the VA hole on UltraSPARC I and II
3. physical addresses beyond the limit of physical memory are identity mapped, uncachable
4. no code within 4GiB reach of the VA hole on T1
5. no code within 8KiB below VA hole on T2