= Virtual address spaces per architecture = == amd64 == 48-bit VAS || 0xffff800000000000 || 128TiB || kernel non-identity || || 0x0000800000000000 || 16776960TiB || VA hole || || 0x0000000000000000 || 128TiB || uspace non-identity || == mips32 == || 0xe0000000 || 512MiB || kernel non-identity || kseg3 || || 0xc0000000 || 512MiB || kernel non-identity || ksseg || || 0xa0000000 || 512MiB || spec || kseg1 || 1. || || 0x80000000 || 512MiB|| kernel identity || kseg0 || 2. || || 0x00000000 || 2GiB|| uspace non-identity || kuseg || 1. maps to physical 0, uncached, bypasses TLB 2. maps to physical 0, cacheable, bypasses TLB == sparc64 == === UltraSPARC I, II, IIi === 44-bit VAS || 0xfffff80000000000 || 8TiB || kernel non-identity || || 0x0000080000000000 || 16777200TiB || VA hole || 1. || || 0x0000000000000000 || 8TiB || kernel non-identity || 1. no code within 4GiB reach of the VA hole on UltraSPARC I and II === UltraSPARC III, IIIi, IV and IV+ === 64-bit VAS || 0x0000000000000000 || 16EiB || kernel non-identity || === UltraSPARC T1, T2 === 48-bit VAS || 0xffff800000000000 || 128TiB || kernel non-identity || || 0x0000800000000000 || 16776960TiB || VA hole || 1., 2. || || 0x0000000000000000 || 128TiB || kernel non-identity || 1. no code within 4GiB reach of the VA hole on T1 2. no code within 8KiB below VA hole on T2