| | 1 | = Virtual address spaces per architecture = |
| | 2 | |
| | 3 | == mips32 == |
| | 4 | |
| | 5 | || 0xe0000000 || 512MiB || || kernel non-identity || kseg3 || |
| | 6 | || 0xc0000000 || 512MiB || kernel non-identity || ksseg || |
| | 7 | || 0xa0000000 || 512MiB || spec || kseg1 || (maps to physical 0 uncached) || |
| | 8 | || 0x80000000 || 512MiB|| kernel identity || kseg0 || (maps to physical 0 cacheable) || |
| | 9 | || 0x00000000 || 2GiB|| uspace non-identity || kuseg || |
| | 10 | |
| | 11 | == sparc64 == |
| | 12 | |
| | 13 | === UltraSPARC I, II, IIi === |
| | 14 | |
| | 15 | VAS is 44-bits wide. |
| | 16 | |
| | 17 | || 0xfffff80000000000 || 8TiB || kernel non-identity || |
| | 18 | || 0x0000080000000000 || 16777200TiB || VA hole || no code within 4GiB reach of the VA hole on I and II || |
| | 19 | || 0x0000000000000000 || 8TiB || kernel non-identity || |
| | 20 | |
| | 21 | |
| | 22 | === UltraSPARC III, IIIi, IV and IV+ ==== |
| | 23 | |
| | 24 | Full 64-bit VAS |
| | 25 | |
| | 26 | || 0x0000000000000000 || 16EiB || kernel non-identity || |
| | 27 | |
| | 28 | |
| | 29 | === UltraSPARC T1, T2 === |
| | 30 | |
| | 31 | VAS is 48-bits wide. |
| | 32 | |
| | 33 | |
| | 34 | || 0xffff800000000000 || 128TiB || kernel non-identity || |
| | 35 | || 0x0000800000000000 || 16776960TiB || VA hole || no code within 4GiB reach of the VA hole on T1, no code below 8KiB on T2 || |
| | 36 | || 0x0000000000000000 || 128TiB || kernel non-identity || |