= Programming Neo !FreeRunner LEDs = Neo !FreeRunner has three LED indicators: || '''Color''' || '''Location''' || '''IO Port/pin''' || || orange || behind power button || GPB0 || || blue || behind power button || GPB1 || || red || behind aux button || GPB2 || Combination of orange and blue behind the power button should give purple. == Port B Control Registers == || '''Register''' || '''Address''' || '''Description''' || '''Reset value''' || || GPBCON || 0x56000010 || Pin configuration || 0x0 || || GPBDAT || 0x56000014 || Data in/out || undefined || || GPBDN || 0x56000018 || Pull-down disable || 0x0 || GPB has 11 pins (GPB0 through GPB11 inclusive). '''Register descriptions:''' * GPBCON: Two configuration bits per pin (GPBCON![1:0] for GPB0, GPBCON![3:2] for GPB1, etc.), 00 = Input, 01 = Output, 10 = XXX, 11 = reserved. XXX refers to internal signals, different for each pin. * GPBDAT![10:0]: Write GPB10..GPB0 in output mode and read GPB10..GPB0 in input mode. * GPBDN![10:0]: 0 = pull-down enabled, 1 = pull-down disabled in GPB10..GPB0. For blinking LEDs, we select output mode (0b01) for GPB0..GPB2. Pull-down should be disabled. Then write to GPBDAT![0:2]. To turn the LED on, set the pin value to 1 (H level), to turn it off set pin value to 0 (L level). '''References:''' * [http://www.opatnet.cz/elektronika/datasheet/U/um_s3c2442b_rev12.pdf Samsung S3C2442B Processor Datasheet] Port B Control Registers, Page 9-10. * [http://downloads.openmoko.org/developer/schematics/GTA02/Schematics_Freerunner-GTA02_A5-A7cumulative_public_RC0.pdf Neo FreeRunner Schematics] MCU, sheet 3. '''Notes:''' * Could not find in datasheet whether H drive is coded as 1 or 0. From experiments 1 is H because 1 lights the LED. == I/O registers vs. endianity == All the I/O registers on the S3C24xx are naturally 32-bit. This means if you access them as 32-bit memory locations, you needn't worry about endianity (recommended). If you need to access them as 8-bit memory locations, the GTA02 memory system is little-endinan. You would thus use the same address for the 8-bit access as for the 32-bit access in order to read or write the least significant byte.