= Comparison of ARM Cortex-A series CPU cores = This page serves as a quick reference for the differences between different armv7a Cortex-A cores that are relevant for software support implementation. The cores are ordered left to right in order of release date. TODO ||= Core =|| A8 || A9 || A5 || A15 || A7 || A12 || A17 || || Instruction set || Thumb-2, ThumbEE, security extensions, NEON, VFPv3 || || L1 cache || icache IVIPT, dcache PIPT, 64B lines, 4-way set associative, 16kB or 32kB || || L2 cache || unified PIPT, internal, 64B lines, 8-way set associative, up to 1MB, parity, ECC, PLE || || TLB || separate, 32 entries each || || BP || "dynamic branch prediction with branch target address cache, global history buffer, and 8-entry return stack" || || notes || all caches are normally invalidated on reset ||