Changes between Initial Version and Version 1 of CortexAComparison


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Timestamp:
2018-03-09T16:59:17Z (6 years ago)
Author:
Jiří Zárevúcky
Comment:

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  • CortexAComparison

    v1 v1  
     1= Comparison of ARM Cortex-A series CPU cores =
     2
     3This page serves as a quick reference for the differences between different armv7a Cortex-A cores that are relevant for software support implementation.
     4The cores are ordered left to right in order of release date.
     5
     6TODO
     7
     8||= Core                 =|| A8                || A9 || A5 || A15 || A7 || A12 || A17 ||
     9||  Instruction set       || Thumb-2, ThumbEE, security extensions, NEON, VFPv3   ||
     10||  L1 cache              || icache IVIPT, dcache PIPT, 64B lines, 4-way set associative, 16kB or 32kB ||
     11||  L2 cache              || unified PIPT, internal, 64B lines, 8-way set associative, up to 1MB, parity, ECC, PLE ||
     12||  TLB                   || separate, 32 entries each ||
     13||  BP                    || "dynamic branch prediction with branch target address cache, global history buffer, and 8-entry return stack" ||
     14||  notes                 || all caches are normally invalidated on reset ||