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Opened 4 years ago

Closed 4 years ago

#636 closed defect (fixed)

Do not use DCCMVAU (c11, 1) on ARM920T

Reported by: Jakub Jermář Owned by: Jiri Svoboda
Priority: major Milestone: 0.7.0
Component: helenos/kernel/arm32 Version: mainline
Keywords: ARM920T, ARMv4, gta02 Cc:
Blocker for: Depends on:
See also:

Description

ARM920T does not implement the DCCMVAU / Clean ID cache entry operation, yet smc_coherence() and pt_coherence_m() use it:

CONTROL_REG_GEN_WRITE(DCCMVAU, c7, 0, c11, 1);
 #define smc_coherence(a) \
 do { \
        DCCMVAU_write((uint32_t)(a));  /* Flush changed memory */\
        write_barrier();               /* Wait for completion */\
        ICIALLU_write(0);              /* Flush ICache */\
        inst_barrier();                /* Wait for Inst refetch */\
#define pt_coherence_m(pt, count) \
 do { \
        for (unsigned i = 0; i < count; ++i) \
                DCCMVAU_write((uintptr_t)(pt + i)); \
        read_barrier(); \
 } while (0)

Change History (1)

comment:1 Changed 4 years ago by Jakub Jermář

Resolution: fixed
Status: newclosed

Fix merged in mainline,2399.
A new set of cache-management macros was defined for ARMv6-.

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