id,summary,reporter,owner,description,type,status,priority,milestone,component,version,resolution,keywords,cc,field_blocks,field_dependson,field_seealso 635,Wrong alignment of CP15 register 7 MVA on ARM920T,Jakub Jermář,Jiri Svoboda,"On ARM920T, register 7 MVA needs to be 32-bytes aligned (bits 0-4 should be zero), yet the code in boot/arch/arm32/src/main.c uses 4-byte increments. {{{ static inline void clean_dcache_poc(void *address, size_t size) { const uintptr_t addr = (uintptr_t)address; for (uintptr_t a = addr; a < addr + size; a += 4) { /* DCCMVAC - clean by address to the point of coherence */ asm volatile (""mcr p15, 0, %[a], c7, c10, 1\n"" :: [a]""r""(a) : ); } }}}",defect,closed,major,0.7.0,helenos/boot/arm32,mainline,fixed,"ARM920T, ARMv4, gta02",,,,