Wrong alignment of CP15 register 7 MVA on ARM920T

[Jakub Jermář]

On ARM920T, register 7 MVA needs to be 32-bytes aligned (bits 0-4 should be zero), yet the code in boot/arch/arm32/src/main.c uses 4-byte increments.

static inline void clean_dcache_poc(void *address, size_t size)
 {
        const uintptr_t addr = (uintptr_t)address;
        for (uintptr_t a = addr; a < addr + size; a += 4) {
                /* DCCMVAC - clean by address to the point of coherence */
                asm volatile ("mcr p15, 0, %[a], c7, c10, 1\n" :: [a]"r"(a) : );
        }

[Jakub Jermář]

Fix merged in mainline,2399.